1279571 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種積體電路测試方 =與一種可達到降低成本以及操控容易之方法及裝置i 【先前技術】 =隨著科技曰趨發達’各式各樣的電子產品均以極 快的速度推陳出新’因此，應用於電子產品内之各式J c (積體電路、晶片）’不僅種類、數量、功能愈來愈多且速 度越來越快，且其體積大小亦有明顯之進步。而一般工c 在出貨前，必須做品質檢測，藉以判定此批I C之良率（y 1 e 1 d )以及將正常與異常的！ c分類避免因品質不 良而遭客戶退貨抽單或求償。目前市面上一般^ c測試 裴置1 ’其方塊圖如第一圖所示，係利用一測試機台1工 〗配合一裝卸裝置i 2將Ϊ 〇：插入於一測試插座i 3内，並 對其輸入測試向量以及利用ATE測試程式進行測試，将測 .試完畢後，再利用裝卸裝置1 2將I C依正常/異常分 類，完成此次測試。請參閱第二圖，係為習知測試機台外 觀不意圖’如圖所示：由於一般測試裝置2内的測試機台 2 2僅提供測量訊號的功能，故必須連接一台微電腦控制 為2 1以控制整個測試裝置2之動作，並將測試機台2 2 與一訊號分析單元2 3連接，用以接收測試機台2 2與I C所接觸而感應之數據，並將數據分析之，以判斷I ◦之 5 1279571 正常與否。 測試向量之基本定義是：向量是每個時脈周期應用於 元件接腳用於輸入或輸出的邏輯1和邏輯〇數據。因為邏 輯1和邏輯0是由帶定時特性和電平特性的波形代表的， . 與波形形狀、脈衝寬度、脈衝邊緣或斜率以及上升沿和下 降沿的位置都有關係。在ATE(自動測試設備）語言中，這 些波形是透過上升和下降緣加上元件接腳對設立時間和保 持時間的要求這種格式化描述方式表示的。現代測試程式 中使用的測試向量有三個基本來源：（1 )大多數功能向量 由循環模擬（cycle-ized simulation)生成；（2 )幾乎所 有掃描向量均由測試模式自動生成（ATPG)或工程設計自動 化（EDA)工具生成；（3 ) HAG、邏輯BIST和記憶體BIST 這類專門技術向量則由目標EDA工具生成。 由於一般習知之測試裝置非常昂貪，且其内之訊號分 析單元多為特別設計製造，且雄修昂貪，測試向量多由軟 體產生，而不是實際1C工作條件，，導致無法完全測試出 1C的缺陷，無法滿足高階品質的需求。此外，為了測試頻 率越來越快、功能越來越復雜的1C，必須不斷將訊號分析 單元汰舊換新，且測試程式的開發越來越困難，不僅設備 昂貴且影響交期。又，使用者必須操作微電腦控制器以及 訊號分析單元，操作不甚方便；甚者，當測試裝置出現故 障時，使用者不易得知是測試裝置内的哪個部分出現故 障，非常難以處理。 有鑑於上述一般測試方法及裝置之缺憾，發明人有感 1279571 其未壤於b Μ ^ 。’遂竭其心智悉心研究克服，憑其從事該項 及壯 Ί貝！驗，進而研發出一種積體電路測試方法 衣 係利用一個人電腦主機以操控積體電路之測試， 到降低成本以及操控容易之功效者。 【發明内容】 >、 尺本發明之主要目的，即在設計一種積體電路測 )二伊置可達到節省成本、操作簡便與提供足夠的錯誤覆 率之力放者。概因本發明採用一台個人電腦主機、至少 測忒機台與至少配置的一測試模組，此一模组即為週 邊應用電路、和一裝卸裝置這樣簡單的組合，並設計相關 的軟硬體及控制系統，即可達成習知技術昂貴的的測試裝 置所進行的測試功能，並因著組合簡單，而操作非常簡便。 且如前所述，本發明係可依據所欲測試的積體電路進行實 際1C焊接在pCB狀態完全相同的模擬設計，其測試條件可 )完全和客戶端PCB狀況相同。故可以解決無法提供足夠的 錯誤覆蓋率，導致有時無法測試出所有缺陷的問題，與為 了滿足測試之需求而不斷將訊號分析單元汰舊換新，亦不 符合經濟效益的問題。 本發明之另一目的，即在設計一個人電腦系統，可避 免量產時當機的困擾，且當測試裝置出現故障時，使用者 可輕易得知是測試裝置内的哪個部分出現故障之功效者。 概因本發明的測試方法具有一個步驟是判斷與該測試模組 連接之測試機台狀態是否異常，若為異常，則將該測試機 1279571 台回復至可測試之狀態。如此可以使整個量產測試過程順 利進行。 為達上述目的，本發明之實現技術如下： 一種積體電路測試方法及裝置，其係利用一電腦主機 以操控積體電路之測試。當測試啟動時，電腦主機則驅動 一裝卸裝置將待測之積體電路置於一測試模組上，並輪詢 與測試模組連接之測試機台狀態是否異常，若無異常，則 驅動測試機台對積體電路進行測試，並將測試結果正常以 及異常之積體電路分類收集，完成此次測試。藉由電腦主 機操控積體電路之測試，可達到降低成本以及操控容易之 功效者。 為使本發明之上述和其他目的、特徵及功效能更明顯 易懂，茲藉由下述具體之實施例，並配合所附之圖式，對 本發明做一詳細說明如下。 【實施方式】 請參閱第三圖，係為本發明之實施流程圖，如圖所示： 本發明之積體電路測試方法，係於測試啟動3 0時，電腦 主機則驅動一裝卸裝置將待測之積體電路置於測試模組上 3 1，並判斷與測試模組連接之測試機台狀態是否異常3 2，若為異常，則將測試機台回復至可測試之狀態3 2 1， 並重複步驟3 2，若無異常，則驅動測試機台對測試模組 上之積體電路進行測試3 3，並判斷積體電路是否正常3 4，且將正常之積體電路分類收集3 5，亦將異常之積體 1279571 收集3 6，再判斷是否繼續測試3 7 —、 驟3 i，若為否，則結束3 8本次之=為是’則回到步 體電路是否正常3 4係為利㈣電其中，判斷積 既有之測試向量以及測試程式，對機進仃，利用其内 自動分析；將正常之積體電路分類收隹^路之感應輸出做 積體電路分類收集3 6係為利用該^ 5以及將異常之 其分別收集置於不同的收集_ ; #；；，置進行’並可將 一丄 ^斷是否繼續測試^ 7 係為利用該電腦主機進行，電齡機可自動判斷是否還有 =之積體電路尚未測試。此外’使用個人電腦並開發相 關軟硬體可降狀備購買的成本支出，且將lc置於模組板 内實際測試其功能，亦可以提高測試之覆蓋率，符合所有 的測試需求。又，使用者於測試時僅需操作電腦主機的單 一介面，操控非常方便，且一但發生故障時，電腦主機將 自動偵測出是哪部分故幛，讓維修人員可以快速進行維修。 請參閱第五圖，係為本發明之方塊圖，如圖所示：本 發明之積體電路測試裝置4，至少包含有：一電腦主機4 1 ; 一測試機台4 3，係與該電腦主機41連接，可接收 該電腦主機4 1所傳來:之測試訊號以及將測試數據回傳至 該電腦主機4 1 ; 一測試模組4 4，係與該測試機台4 3 連接，且可將待測之該積體電路置放其上，並配合該積體 電路之腳位進行測試；以及一裝卸裝置4 2，係與該電腦 主機4 1連接，且其將該積體電路自該測試模組4 4上裝 卸之動作係受該電腦主機4 1所控制。其中，該電腦主機 4 1係可透過一TTL (電晶體一電晶體邏輯）單元與該 1279571 裝卸裝置4 2連接，藉以控制該裝卸裝置4 2之動作；該 裝卸裝置4 2係可為一機械手臂者，可用吸放或是推夾之 方式將該積體電路裝卸於該測試模組4 4上；該電腦主機 4 1係可透過一 R S 2 3 2介面與該測試機台4 3連接， 以執行資料之互傳，並可於該測試機台4 3異常時，透過 該電腦主機4 1將該測試機台4 3回復至正常之狀態者。 故當使用者於測試時僅需操作電腦主機的單一介面，操控 }非常方便，且一但發生異常時，電腦主機將自動偵測出是 哪部分故障，讓維修人員可以快速進行維修。 請參閱第六圖，係為本發明之另一方塊圖，如圖所示： 本發明之積體電路測試裝置4，至少包含有：一電腦主機 4 1 ; 一測試機台4 3，係與該電腦主機4 1連接，可接 收該電腦主機4 1所傳來之測試訊號以及將測試數據回傳 至該電腦主機4 1 ; 一測試模組4 4，係分別與該測試機 台4 3以及該電腦主機4 1連接，且可將待測之該積體電 )路置放其上，並配合該積體電路之腳位進行測試；一裝卸 裝置4 2，係與該電腦主機4 1連接，且其將該積體電路 自該測試模組4 4上裝卸之動作係受該電腦主機4 1所控 制；以及一電源供應裝置4 5，係分別與該電腦主機4 1、 該測試機台4 3、該測試模組4 4以及該裝卸裝置4 2連 接，提供其動作所需之電源。其中，該測試模组4 4與該 電腦主機41連接係為使該電腦主機41直接控制該測試 模組4 4之啟閉，可待一切準備就緒後再使其啟動，以節 省電力。該電腦主機4 1係可透過一TTL (電晶體一電 11 1279571 晶體邏輯）單元與該裝卸裝置4 2連接，藉以控制該裝卸 裝置4 2之動作；該裝卸裝置4 2係可為一機械手臂者， 可用吸放或是推夾之方式將該積體電路裝卸於該測試模組 4 4上；該電腦主機4 1係可透過一R S232介面與該 測試機台4 3連接，以執行資料之互傳，並可於該測試機 台4 3異常時，透過該電腦主機4 1將該測試機台4 3回 復至正常之狀態者。故當使用者於測試時僅需操作電腦主 機的單一介面，操控非常方便，且一但發生異常時，電腦 主機將自動偵測出是哪部分故障，讓維修人員可以快速進 行維修。 此種利用個人電腦主機進行積體電路測試之方法與裝 置，不但不需要常常汰舊換新，且使用者僅需要操作一種 介面，達到降低成本以及操控容易之功效者。 綜前所述，由本發明一種積體電路測試方法與裝置之 設計確實可行，且改善了習用技術之各種缺失，實為創新 並符合產業需求之高度發明，而且具有新穎性以及進步 性，完全符合發明專利之法定要件，爰依法提出發明專利 申請。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍以及特定使用方式；凡其他未脫 離本發明所揭示之精神下所完成之等效改變或修飾，均應 包含在下述之申請專利範圍内。 【圖式簡單說明】 12 1279571 第一圖係為習知測試裝置之方塊圖。 第二圖係為習知測試裝置之外觀示意圖。。 第三圖係為本發明之實施流程圖。 第四圖係為本發明之另一實施流程圖。 第五圖係為本發明之方塊圖。 第六圖係為本發明之另一方塊圖。 【主要元件符號說明】 1 .....測試裝置 1 1 · · · ·測試機台 12····裝卸裝置 13····測試插座 2 .....測試裝置 2 1 ··微電腦控制器 2 2 · · · ·測試機台 2 3 ··訊號分析單元 3 0·········.....•測試啟動 3 1 ···將待測.之積體電路置於一測試模组上 3 2 ·······判斷測試機台狀態是否正常 )321····將測試機台回復至可測試之狀態 3 3 ····對測試模組上之積體電路進行測試 3 4 ········‘判斷積體電路是否正常 3 5 ···.···將正常之積體電路分類收集 3 6.......將異常之積體電路分類收集 3 7···....... · · ·是否繼續測試 3 8.................結束 3 9.....對測試模組提供啟動所需之電源 4 · · · · ·測試裝置 4 1 · · · ·電腦主機 13 1279571 4 2··· •裝卸裝置 4 4 4··· •測试核組 4 • · · ·測試機台 ••電源供應裝置 141279571 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an integrated circuit tester = and a method and apparatus for achieving cost reduction and easy handling. [Prior Art] = With technology The development of 'all kinds of electronic products are introduced at a very fast speed'. Therefore, various types of J c (integrated circuits, wafers) used in electronic products are not only more and more types, speeds, functions, and speeds. It is getting faster and faster, and its size has also improved significantly. In general, before the shipment, the quality must be tested to determine the yield of the batch of I C (y 1 e 1 d ) and normal and abnormal! The c classification avoids the return of a customer's bill or claim due to poor quality. At present, the general ^ c test device 1 'the block diagram is as shown in the first figure, using a test machine 1 work with a loading and unloading device i 2 to insert Ϊ 〇: into a test socket i 3, and The test vector is input and tested by the ATE test program. After the test is completed, the IC is sorted according to normal/abnormal using the loading and unloading device 12 to complete the test. Please refer to the second figure for the conventional test machine. The appearance is not intended as shown in the figure: Since the test machine 2 in the general test device 2 only provides the function of measuring signals, it is necessary to connect a microcomputer to 2 1 to control the action of the entire test device 2, and connect the test machine 2 2 with a signal analysis unit 23 for receiving data sensed by the test machine 2 and the IC, and analyzing the data to Determine if I 5 5 1279571 is normal or not. The basic definition of a test vector is that the vector is the logical 1 and logical 〇 data that each clock cycle applies to the component pins for input or output. Because Logic 1 and Logic 0 are represented by waveforms with timing and level characteristics, they are related to waveform shape, pulse width, pulse edge or slope, and the position of the rising and falling edges. In the ATE (Automated Test Equipment) language, these waveforms are represented by a formatted description of the rise and fall edges plus the component pin setup time and hold time requirements. There are three basic sources of test vectors used in modern test programs: (1) most function vectors are generated by cycle-ized simulations; (2) almost all scan vectors are automatically generated by test patterns (ATPG) or engineering Automated (EDA) tool generation; (3) specialized technical vectors such as HAG, logical BIST, and memory BIST are generated by the target EDA tool. Because the conventional test device is very greedy, and the signal analysis unit in it is mostly designed and manufactured, and the test is more rigorous, the test vector is mostly generated by software, instead of the actual 1C working condition, which makes it impossible to fully test 1C. Defects cannot meet the needs of high-end quality. In addition, in order to test 1C with faster and more complex functions, it is necessary to continuously replace the signal analysis unit, and the development of test programs becomes more and more difficult, which is not only expensive but also affects delivery. Moreover, the user must operate the microcomputer controller and the signal analysis unit, which is not convenient to operate; even when the test device fails, it is difficult for the user to know which part of the test device is faulty, which is very difficult to handle. In view of the shortcomings of the above general test methods and devices, the inventor felt that 1279571 was not soiled in b Μ ^. ‘Don’t exhaust your mind and study it, and rely on it to engage in this and strong mussels! Test, and then developed a test method of integrated circuit. The use of a human computer to control the integrated circuit test, to reduce cost and easy to control the effect. SUMMARY OF THE INVENTION >, the main purpose of the invention is to design an integrated circuit to measure the two-element to achieve cost savings, ease of operation and provide sufficient error coverage. The invention adopts a personal computer host, at least a test machine and at least one test module, which is a simple combination of a peripheral application circuit and a loading and unloading device, and is designed to be related to soft and hard. The body and the control system can realize the test function performed by the test device which is expensive in the prior art, and the operation is very simple because of the simple combination. As described above, the present invention can perform the actual 1C soldering in the same analog design of the pCB state according to the integrated circuit to be tested, and the test conditions can be completely the same as the client PCB condition. Therefore, it can solve the problem that it is impossible to provide sufficient error coverage, and sometimes it is impossible to test all the defects, and it is not economical to continuously replace the signal analysis unit in order to meet the test requirements. Another object of the present invention is to design a personal computer system to avoid the trouble of mass production, and when the test device fails, the user can easily know which part of the test device is malfunctioning. . The test method of the present invention has a step of determining whether the state of the test machine connected to the test module is abnormal. If it is abnormal, the test machine 1279571 is returned to the testable state. This allows the entire mass production test process to proceed smoothly. In order to achieve the above object, the implementation technology of the present invention is as follows: An integrated circuit test method and apparatus, which utilizes a computer host to control the test of the integrated circuit. When the test is started, the computer host drives a loading and unloading device to place the integrated circuit to be tested on a test module, and polls whether the test machine connected to the test module is in an abnormal state. If there is no abnormality, the drive test is performed. The machine tests the integrated circuit, and collects the normal and abnormal integrated circuit samples to complete the test. By controlling the integrated circuit test by the computer host, it is possible to achieve cost reduction and easy handling. The above and other objects, features, and advantages of the present invention will become more apparent from the understanding of the appended claims appended claims [Embodiment] Please refer to the third figure, which is a flowchart of the implementation of the present invention. As shown in the figure: The integrated circuit test method of the present invention is when the test starts 30, the computer host drives a loading and unloading device to be treated. The measured integrated circuit is placed on the test module 3 1, and it is judged whether the test machine connected to the test module is in an abnormal state 3 2, and if it is abnormal, the test machine is returned to the testable state 3 2 1, And repeat step 3 2, if there is no abnormality, drive the test machine to test the integrated circuit on the test module 3 3, and determine whether the integrated circuit is normal 3 4, and collect the normal integrated circuit classification 3 5 It also collects the abnormal integrated body 1279551, and then judges whether to continue testing 3 7 -, step 3 i, if not, then end 3 8 this time = yes is 'return to the step circuit is normal 3 4 It is the profit of the (four) electricity, which determines the test vector and the test program of the product, and uses the automatic analysis in the machine; the normal integrated circuit is divided into the induction output of the circuit to make the integrated circuit classification. 6 series is to use the ^ 5 and the difference of the difference The set is placed in a different collection _; #;;, set to 'can be a 丄 ^ ^ ^ to continue testing ^ 7 is to use the computer host, the computer can automatically determine whether there is still = integrated circuit yet test. In addition, the use of personal computers and the development of related software and hardware can reduce the cost of purchase, and the actual test of lc in the module board can also improve the coverage of the test and meet all testing needs. In addition, the user only needs to operate a single interface of the computer host during the test, and the control is very convenient, and once the fault occurs, the computer host will automatically detect which part of the fault is caused, so that the maintenance personnel can quickly perform the repair. Please refer to the fifth figure, which is a block diagram of the present invention. As shown in the figure, the integrated circuit testing device 4 of the present invention comprises at least: a computer main unit 4 1 ; a testing machine 4 3 , and the computer The host computer 41 is connected to receive the test signal transmitted from the computer host 4 1 and transmit the test data back to the computer host 4 1 ; a test module 4 4 is connected to the test machine 4 3 and can be connected The integrated circuit to be tested is placed thereon and tested in conjunction with the pin of the integrated circuit; and a loading and unloading device 42 is connected to the host computer 41, and the integrated circuit is self-contained The loading and unloading action of the test module 44 is controlled by the host computer 41. The computer main unit 4 1 can be connected to the 1275971 loading and unloading device 42 through a TTL (Crystal-Crystal Logic) unit to control the operation of the loading and unloading device 42; the loading and unloading device 42 can be a mechanical device. In the arm, the integrated circuit can be mounted on the test module 44 by means of a suction or push clamp; the host computer 4 1 can be connected to the test machine 43 through an RS 2 3 2 interface. In order to perform the mutual transfer of the data, the test machine 4 3 can be returned to the normal state through the host computer 4 1 when the test machine 4 is abnormal. Therefore, when the user only needs to operate a single interface of the computer host during the test, the control is very convenient, and once an abnormality occurs, the computer host will automatically detect which part of the fault, so that the maintenance personnel can quickly perform the repair. Please refer to the sixth figure, which is another block diagram of the present invention. As shown in the figure, the integrated circuit testing device 4 of the present invention includes at least: a computer host 4 1 ; a testing machine 4 3 The computer host 41 is connected to receive the test signal transmitted from the host computer 4 1 and return the test data to the host computer 4 1 ; a test module 44 is respectively associated with the test machine 4 3 The computer host 41 is connected, and the integrated circuit) to be tested is placed thereon, and tested according to the position of the integrated circuit; a loading and unloading device 4 2 is connected to the computer host 4 1 And the action of loading and unloading the integrated circuit from the test module 4 4 is controlled by the computer host 41; and a power supply device 45 is respectively associated with the computer host 4 1 and the test machine 4 3. The test module 44 and the loading and unloading device 42 are connected to provide the power required for the operation. The test module 44 is connected to the computer host 41 so that the computer host 41 directly controls the opening and closing of the test module 44, and can be started after everything is ready to save power. The computer main unit 4 1 is connected to the loading and unloading device 42 through a TTL (Cell-Electrical 11 1279571 Crystal Logic) unit, thereby controlling the action of the loading and unloading device 42; the loading and unloading device 42 can be a robot arm The integrated circuit can be loaded and unloaded on the test module 44 by means of a suction or push clamp; the host computer 4 1 can be connected to the test machine 43 through an R S232 interface to execute data. The mutual transfer is performed, and when the test machine 4 is abnormal, the test machine 4 3 is returned to the normal state through the host computer 4 1 . Therefore, when the user only needs to operate a single interface of the computer host during the test, the control is very convenient, and when an abnormality occurs, the computer host will automatically detect which part of the fault, so that the maintenance personnel can quickly perform the repair. Such a method and device for performing integrated circuit testing using a personal computer host not only does not require frequent replacement, but also requires the user to operate only one interface to achieve cost reduction and easy handling. As mentioned above, the design of the integrated circuit test method and device of the present invention is indeed feasible, and the various defects of the conventional technology are improved, which is a novel invention which is innovative and meets the industrial requirements, and is novel and progressive, and fully conforms to The statutory requirements of the invention patent, and the invention patent application is filed according to law. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention and the specific use of the invention; all other equivalent changes or modifications which are not departing from the spirit of the invention It should be included in the scope of the patent application below. [Simple description of the diagram] 12 1279571 The first diagram is a block diagram of a conventional test device. The second figure is a schematic view of the appearance of a conventional test device. . The third figure is a flowchart of the implementation of the present invention. The fourth figure is a flow chart of another embodiment of the present invention. The fifth figure is a block diagram of the present invention. The sixth figure is another block diagram of the present invention. [Explanation of main component symbols] 1 ..... Test apparatus 1 1 · · · · Test machine 12····Loading and unloading device 13····Test socket 2 .....Testing device 2 1 ··Microcomputer Controller 2 2 · · · · Test machine 2 3 ··Signal analysis unit 3 0············•Test start 3 1 ···The integrated circuit to be tested Placed on a test module 3 2 ·······Check if the test machine status is normal. 321····Return the test machine to the testable state 3 3 ···· on the test module The integrated circuit is tested. 3 4 ·········Check if the integrated circuit is normal. 3 5 ·································· Abnormal integrated circuit classification collection 3 7···....... · · ·Continue to test 3 8.................End 3 9... .. provide the test module with the power supply required for startup 4 · · · · · Test device 4 1 · · · · Computer host 13 1279571 4 2 ··· • Loading and unloading device 4 4 4··· • Test core group 4 • · · · Test machine • Power supply unit 14