TW561604B - Optically and electrically programmable silicided polysilicon fuse device - Google Patents
Optically and electrically programmable silicided polysilicon fuse device Download PDFInfo
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- TW561604B TW561604B TW091117508A TW91117508A TW561604B TW 561604 B TW561604 B TW 561604B TW 091117508 A TW091117508 A TW 091117508A TW 91117508 A TW91117508 A TW 91117508A TW 561604 B TW561604 B TW 561604B
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Description
561604 五、發明說明(ι) 本發明係有關於一種積體電路 於在半導體積體電路中的可熔 牛且更特別地是闕 對金屬層而形成雷射炫絲, 令在複晶石夕層相 上。 ,向乂此夠被安置於氧化物之 目前,一般言,積體電路在製 部之連結。然而,因高度發展作序中被製成帶有内 以及這些電路之高加工成:,炊^的電導引時間, 疇被規劃的電路。這此電路A ^ ^ 1用者優選能在此範 其經常帶有可規劃Μ路典型地有關可規劃的電路,當 可規劃的連結是電學被士 ^ -1,,, τ,,« Λ ^ -- 在藉由最終使用者所選擇的節;;生 :疋被加以創•。如此例中,可規割的壞或 於可規劃的唯讀記憶體元件咖):在這:使用 :出可規劃的連結最普遍的 ’被 ^ ”,車°亥點陣包含一個在導電連結之交叉點 :作為-可熔融連結’丨將一電晶體連接於此點:,而 ^規劃P_,該可溶融連結在所選擇的節點處^路。 創坆了-個開放的電路。膨脹與非膨脹的钍而 〜和零之一個數位位元圖,1组成數據,π = δ組成了 PMMt。 …且成數據❿使用” 可熔融連結PROM系統的一些主要缺點,因 電材料之特性,高電壓以及高電流層級在規‘、、、連,中導 - π 中是經 第5頁 561604
以為了使溶絲連 常地被需要 對高的導電性,故。η膨脹。因為該連結相 夺电庇故其要求相當的粉末溢散量來吹製。 進一步地,可熔融連結的尺寸以及型態 :::不膨脹該連結將有效地作為導二使 完全地開啟電流。 石八私脹而 可規劃連結的第二種型式亦*敏 第二種mΓ 繁被使用。可規劃連結的 相:的使:H抗熔融連結’而在積體電路應用有 路或者是低阻抗連結。該抗炫融連結之組 兩個以及/或者是半導體絲枓 蛛古φ八+ ,、 ^ ^ ^ ^ 石疋千v體材枓,f有電介質或者是絕 在其間。在規劃過程巾,絕緣或者是電介質材料在 導電材料之間所選擇點處,藉由加 半導體材料電^妾在而被㈣。 *體成者疋 一種矽化凝聚熔絲元件在美國專利第五七〇八二九一號中 被加以揭示。可熔融的連結元件被沉積在半導體基材1, 其包含: 一複晶石夕層,該複晶矽層具有一第一阻抗; 夕化層’遺石夕化層在該複晶石夕層上被形成,該石夕化層具 有比該第一阻抗低的一第二阻抗,使該矽化層凝聚而形成 一電學非連續性,回應所正被施於該矽化層之預定規劃電 位’使得可溶融連結元件之阻抗能夠選擇性地被增加;以
^〇1604
561604 五、發明說明(4) 層 吴國專利第六一〇四〇七九號相近地揭曰 絲,以及其製造方法。玆古汰田从4 ·、斜之複日日石夕炼 絲 度 容 疊 式 以及其製造方法。該方法用於減;;複:曰:矽熔 鎢P早礙相鄰於熔絲單元且鎢障礙之 、针 鎢在裂#站中技總思二此 t k /、力口工程序相 以2 f ! 頂部所經過的層面被堆 及層,、及之間電介質被用作為炼絲覆蓋。 鎢熔絲障礙程序與複晶石夕炼 =種方 被揭Γ。!導體炼絲被設置於連接至 亚且熔絲單元在間隔之間被設 置, 間的間隔包含第-寬卜〇含田連接佈線在導體之 這個熔碎有一個小於該第一寬度的第二寬度。 ;;Γ元件免受過電壓以及/或是電流或者 元件Ϊ;妾;不與連長接期不變地-個半導體元綱^ 美國專利第五-丄 — — 抗炫融單元。號揭示—電可規㈣低電阻抗, 極以及一個之=Γ 70組成類電容結構’其具有一個第一電 前藉由一個f極’其間帶有電介質| ’並在規劃之 個低阻抗來與極低的漏電流’與規劃之後藉由— 被沉積,並=特性。複數個抗熔絲在半導體積體電路中 置產生連接=建擇性可能膨脹而在積體電路中所選擇的位 抖姑4二丄點間低電阻抗。該抗熔絲無論在積體電路模之 河我之刖或杏Η 考疋之後可能被膨脹。
第8頁 561604 五、發明說明(5) -ϋ ί Γ ί五八八二九九八號揭示-種低能可規書吻 、、、口構Μ及其製造方法。該方法包含· 一 j込4 ”:基材,該基材具有一排列氧化區域; ,已乜雜之複晶矽帶覆蓋形成—罩,使瞧 複晶矽帶的窗,在該已摻二二=杉雜 義; 日日7贡大約中央處被加以定 加加增加的植入量在該罩以及播訊兮办士、士 雜複晶”,4已摻雜複晶石夕帶產: = 皮:露之已摻 區域,已增加的電阻抗量介於大約曰σ 雜濃度 X 1015公分-2之間;以及 ^ 10么为2與大約6 f已摻雜之複晶矽帶覆蓋形成—矽化 摻雜物濃度區域之上被形== 二屬之-較厚層在已推雜複…之其它區域= 使用可規劃炼絲之習知技藝中的-個需要, ,要減;以除了在最終金屬層面使個而要, 電流法職κ的損害,在其中有些對 步的需要,是能夠使用當知技藝中-個進-里並且減少在規劃過程中對鄰近結構之傾:
第9頁 典㈣例子當在溶絲被電r劃構之物理性損害’-如 在提供用於積體電路中可 561604 五、發明說明(6) 與損害。 最後,在提供可規劃的熔絲而用於積體電路的 中’需要排除耐火的金屬材料,一般地需要作 連線物,而能夠使用較短的波長,並且因而緊隹ς 置,導致降低傾斜度,但亦使其電學性地被上書二 而提供改進影響利用光能或者是電能來加以規劃的彈性。 發明要旨 本發明的一個目的在提供在 藉由避免使用最終金屬層面 絲,而減少電介質層面之間 中有些對結構的損害仍然發 積體電路中可規劃之熔絲,其 (其可以被設置氧化物)中的炫 與相鄰結構的損害,並且在其 生0
本發明的另一個目 熔絲連結,不像所有目 結構之物理損害。 的在提供用於積體電路中可規劃之 前常用已知的規劃方法,且免除對 本發明-個進-步的目的在提供用於積體電路中可規劃之 溶絲,其使用與炫損或者是炼融技術相比而更小的能量, 並且減少在規劃過程中對鄰近結構之傾斜盥損宝。
本發明更進-步的目的在提供用於積體電路中可規劃之炫 絲,其能夠藉由光學褒置來加以規劃,較短波長光因而減 少光學光束焦點’導致減小了的傾斜度,但其亦使其自身 被電規劃及光規劃。 本發明優選實施例之詳細說明:
第10頁 561604 五、發明說明(7「 一·" -- 介電^丨:所不一炫絲連接之顯微光學圖’其中在氧化物/低 的半I料上的金屬線證實由高能需求所規劃此熔絲所產生 ^ 1目告丨厶 JL , , y 田規里彳在習知技藝中所見類似熔絲連接時,一個 大"的傾斜县骨西人人 點。^ K而要的,而這是使用此熔絲連接所附帶的缺 於該^大的傾斜所帶來的進一步缺點是損壞造成該層低 區) 系 並且°亥k絲會離開溶絲匣(而這造成一損壞 當使此地,在背面末端積體中具有一些困難,例如, ΰ沾這¥知技藝以複晶矽為基礎的溶絲連結時之翻轉晶 乃、$吉合。 田規劃習知技藝炫絲連接時,除了由高能量產生溢散之 ,尚還有另外的缺點,即是,在規劃過程中所產生的裂 縫,如圖2之顯微光學圖中所示。 本發明以矽化複晶矽為基礎的熔絲元件,可以光學地 芳“ ¥地來加以規劃,如圖3所示。在這個圖中,包含以 石 H匕複晶石夕為基礎的熔絲元件之一俯視圖及一剖面圖,其 3帶-絕緣層Π層積其上的―石夕基材2G。在該炫絲元件 的貫施例中,熔絲元件部份FDS被層積於絕緣層21上,作 為較大的積體電路元件的一卹八 _ ^ Q s. 〇 〇 吩兀忏旳·。卩伤。该複晶層22可以被摻雜 成P型,然而,其它實施例或者是配置可以包含其它型式 的摻雜包含n-型或者是在複晶層22中p-η接合之形成。熔 絲元件部份FDS ’在被規劃或者是吹製之前,利用在石夕化 祓晶矽,之阻抗來特性化。如圖3所可以觀察到的,在規 劃的狀態中,因為在一些區域中移除c〇Si2而穫得較高的 阻抗。明顯的{’㈣絲連接不在有物理性地破裂,使達
561604 五、發明說明(8) 成此較高的阻抗狀態。再者, 中不受干擾。能被相信的是,=化層24在整個加工過程 任何地殘留傳導,亦使其因石夕中的換雜物可利於 能為封裝或者是障礙層,而达:非活性化。t化矽層功 化複晶石夕層之阻抗變化,而;光能傳送肖,允許石夕 在本發明的内容中,c〇Si a破裂。 的矽化物例如是鈦的矽化物、2 :二土作為矽化物。其它 化物同等地可被使用。同時,化物、或者是翻的石夕 優選地為封裝層。㉟而,任何♦=内容中,氮化石夕 亦將能滿足。 彳7相,封裝,或者是阻礙層 圖4顯示本發明結構之顯微 甘—人 絲連結陣列,顯示被規劃的矽化予/ ’〃已έ 一大的熔 此實施例中規劃是在3.3V,並且大t :優選地,在 2 0 0微秒·,該電流在相接觸處3〇之間二女1下維持大約 流經熔點融連結而使熔融連社 机 口 "所不。電流 結31裂開。換句㈣,基; 土足|且抗熔絲連結已被改變。本發 明中以石夕化複晶為基礎的溶絲元件,可以藉由施加 以及近紅化光NIR範圍使局部阻抗增加之光能,來加以規 晝:;亦無任何裂痕。* 一步地’在層與層之間之電介 質,氧化物與氮化物並無吸收。 新穎之創造性的結才冓,去除了金屬連結雷射熔絲的缺 點,提供了在產品選擇性及測試流動的彈性,並且允利 用雷射或者是電學裳置來加以規劃,並且如此進行時°,引 起超過105歐姆(Ohms)大的阻抗變化,且無連結的破裂。 第12頁 561604 圖式簡單說明 圖1在習知技藝中熔絲連接的顯微光學圖,其中在 物/低介電常數材料上具有金屬線,以及具有一濺出物。 圖2在習知技藝中熔絲連接的顯微光學圖,其 物/低介電常數材料上具有金屬線,以及具有一裂痕。 圖3為本發明經規劃後以矽化複晶矽為 微光學圖。 疋心熔、、、糸的顯 圖4為本發明包含一大熔絲組之歹纟、^ 物來加以規劃。 ®㈠石夕化複晶矽線藉由厚氧化 圖5為本發明包含熔絲之單一可 — 學俯視圖,其中矽外…θ汾括# 融連接几件的顯微光 化稷日日矽線糟由厚氧化物來加以規劃。 元件符號說明: FDS炼絲元件部份 2 2複晶層 2 4鈍化層 PR0M唯讀記憶體元件 2〇矽基材 21絕緣層 3 0相接觸處3 1連結
第13頁
Claims (1)
- 561604曰石Λ:種以矽化複晶矽為基礎之熔絲元件,該元件在 ,杜破壞附近結構而藉由光能及電能可規劃 的,该兀件包含: 一個碎基材; 一個在所述基材上沉積的絕緣層;以及 -個包含複晶矽/ -矽化物/與一障礙層的熔絲元件部份, 所述溶絲兀件部份因所施加於該元件部份之電脈衝,或 於該兀件部份之光束,而使得局部增加阻抗。 2.如申請專利範圍第!項所述以石夕化複晶石夕為基礎之 熔絲元件,其中該障礙層為氮化石夕。 3 ·如申請專利範圍第丨項所述以矽化複晶矽為基礎之 熔絲元件,其中所述絕緣層為二氧化石夕。 4·如申請專利範圍第3項所述以矽化複晶矽為基礎之 熔絲元件’其中所述絕緣層為氮化矽。 5 ·如申請專利範圍第1項所述以矽化複晶矽為基礎之 熔絲元件,其中所述矽化物係選自由矽化鈷,矽化鈦, 化组以及石夕化始所組成之族群。 6 ·如申請專利範圍第3項所述以矽化複晶矽為基礎之 熔絲元件,其中所述矽化物為矽化鈷。 7 ·如申請專利範圍第3項所述以矽化複晶矽為基礎之 熔絲元件,其中所述矽化物為矽化鈦。 8 ·如申請專利範圍第3項所述以矽化複晶矽為基礎之 熔絲元件,其中所述矽化物為矽化鎢。 9 ·如申請專利範圍第3項所述以矽化複晶矽為基礎之561604 六、申請專利範圍 炫絲元件,其中所述矽化物為矽化钽。 I 0 ·如申請專利範圍第3項所述以矽化複晶矽為基礎之 炫絲元件,其中所述矽化物為矽化鉑。 II ·如申請專利範圍第2項所述以矽化複晶矽為基礎 之炫絲元件,其中所述矽化物係選自由矽化鈷,矽化鈦, 石夕化鎢,矽化鈕以及矽化鉑所組成之族群。 12·如申請專利範圍第11項所述以矽化複晶矽為基礎 之炫絲元件,其中所述碎化物為石夕化始。 1 3 ·如申請專利範圍第11項所述以矽化複晶矽為基礎 之炼絲元件,其中所述石夕化物為石夕化鈦。 14·如申請專利範圍第π項所述以矽化複晶矽為基礎 之炫絲元件,其中所述矽化物為矽化鎢。 1 5 ·如申請專利範圍第丨丨項所述以矽化複晶矽為基礎 之炫絲元件,其中所述石夕化物為石夕化组。 1 6 ·如申請專利範圍第丨丨項所述以矽化複晶矽為基礎 之炫絲元件,其中所述矽化物為矽化鉑。 1 7 ·如申請專利範圍第丨丨項所述以矽化複晶矽為基礎 之炼絲元件,其中規劃電位約為3. 3伏特。 1 8 ·如申請專利範圍第丨丨項所述以矽化複晶矽為基礎 之溶絲元件,其中規劃藉由一光束來進行。第15頁
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US09/921,136 US20030025177A1 (en) | 2001-08-03 | 2001-08-03 | Optically and electrically programmable silicided polysilicon fuse device |
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TW561604B true TW561604B (en) | 2003-11-11 |
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TW091117508A TW561604B (en) | 2001-08-03 | 2002-08-02 | Optically and electrically programmable silicided polysilicon fuse device |
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US (2) | US20030025177A1 (zh) |
EP (1) | EP1412981A1 (zh) |
CN (1) | CN1547773A (zh) |
TW (1) | TW561604B (zh) |
WO (1) | WO2003015168A1 (zh) |
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US7857510B2 (en) * | 2003-11-08 | 2010-12-28 | Carl F Liepold | Temperature sensing circuit |
US20050127475A1 (en) * | 2003-12-03 | 2005-06-16 | International Business Machines Corporation | Apparatus and method for electronic fuse with improved esd tolerance |
US7106164B2 (en) * | 2003-12-03 | 2006-09-12 | International Business Machines Corporation | Apparatus and method for electronic fuse with improved ESD tolerance |
US6946718B2 (en) * | 2004-01-05 | 2005-09-20 | Hewlett-Packard Development Company, L.P. | Integrated fuse for multilayered structure |
CN1324679C (zh) * | 2004-11-24 | 2007-07-04 | 联华电子股份有限公司 | 电气硅熔丝组件的使用方法 |
US20060267136A1 (en) * | 2005-05-24 | 2006-11-30 | International Business Machines Corporation | Integrated circuit (ic) with on-chip programmable fuses |
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US20070111403A1 (en) * | 2005-11-15 | 2007-05-17 | Chun Jiang | Polycide fuse with reduced programming time |
US7732898B2 (en) * | 2007-02-02 | 2010-06-08 | Infineon Technologies Ag | Electrical fuse and associated methods |
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US7713792B2 (en) | 2007-10-10 | 2010-05-11 | International Business Machines Corporation | Fuse structure including monocrystalline semiconductor material layer and gap |
US7924597B2 (en) * | 2007-10-31 | 2011-04-12 | Hewlett-Packard Development Company, L.P. | Data storage in circuit elements with changed resistance |
JP5430879B2 (ja) * | 2008-06-03 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | 電気ヒューズ、半導体装置、および電気ヒューズの切断方法 |
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-
2001
- 2001-08-03 US US09/921,136 patent/US20030025177A1/en not_active Abandoned
-
2002
- 2002-08-02 WO PCT/EP2002/008647 patent/WO2003015168A1/en active Application Filing
- 2002-08-02 EP EP02751171A patent/EP1412981A1/en not_active Ceased
- 2002-08-02 TW TW091117508A patent/TW561604B/zh not_active IP Right Cessation
- 2002-08-02 CN CNA028167856A patent/CN1547773A/zh active Pending
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2003
- 2003-09-23 US US10/669,026 patent/US7029955B2/en not_active Expired - Fee Related
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EP1412981A1 (en) | 2004-04-28 |
US20040056325A1 (en) | 2004-03-25 |
CN1547773A (zh) | 2004-11-17 |
WO2003015168A1 (en) | 2003-02-20 |
US20030025177A1 (en) | 2003-02-06 |
US7029955B2 (en) | 2006-04-18 |
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