TW556265B - Laser-mark printing method of SOI wafer, SOI wafer and method for manufacturing the same - Google Patents

Laser-mark printing method of SOI wafer, SOI wafer and method for manufacturing the same Download PDF

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Publication number
TW556265B
TW556265B TW091119431A TW91119431A TW556265B TW 556265 B TW556265 B TW 556265B TW 091119431 A TW091119431 A TW 091119431A TW 91119431 A TW91119431 A TW 91119431A TW 556265 B TW556265 B TW 556265B
Authority
TW
Taiwan
Prior art keywords
wafer
soi
layer
base wafer
laser mark
Prior art date
Application number
TW091119431A
Other languages
English (en)
Chinese (zh)
Inventor
Shinichi Tomizawa
Kouichi Tanaka
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Application granted granted Critical
Publication of TW556265B publication Critical patent/TW556265B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Laser Beam Processing (AREA)
  • Thermal Transfer Or Thermal Recording In General (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
TW091119431A 2001-08-30 2002-08-27 Laser-mark printing method of SOI wafer, SOI wafer and method for manufacturing the same TW556265B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001262236A JP2003078115A (ja) 2001-08-30 2001-08-30 Ｓｏｉウェーハのレーザーマーク印字方法、及び、ｓｏｉウェーハ

Publications (1)

Publication Number Publication Date
TW556265B true TW556265B (en) 2003-10-01

Family

ID=19089162

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091119431A TW556265B (en) 2001-08-30 2002-08-27 Laser-mark printing method of SOI wafer, SOI wafer and method for manufacturing the same

Country Status (3)

Country Link
JP (1) JP2003078115A (ja)
TW (1) TW556265B (ja)
WO (1) WO2003021681A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JPWO2005086212A1 (ja) * 2004-03-08 2008-01-24 日東電工株式会社 半導体装置用クリーニング部材、及びその製造方法
FR2899594A1 (fr) 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
JP5618521B2 (ja) 2008-11-28 2014-11-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5846727B2 (ja) * 2009-09-04 2016-01-20 株式会社半導体エネルギー研究所 半導体基板の作製方法
JP5933289B2 (ja) * 2012-02-23 2016-06-08 三菱電機株式会社 Ｓｏｉウエハおよびその製造方法
CN102610494A (zh) * 2012-03-27 2012-07-25 上海宏力半导体制造有限公司 标记晶圆的方法、具有标记的晶圆
JP5896810B2 (ja) * 2012-03-30 2016-03-30 オリンパス株式会社 半導体装置
JP6155745B2 (ja) * 2013-03-26 2017-07-05 住友電気工業株式会社 半導体装置の製造方法及び半導体基板の製造方法
JP2013191893A (ja) * 2013-07-02 2013-09-26 Nikon Corp 積層半導体装置の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3328975B2 (ja) * 1992-12-24 2002-09-30 関西日本電気株式会社 半導体ウェーハ
JPH0837137A (ja) * 1994-05-16 1996-02-06 Sony Corp Ｓｏｉ構造の半導体基板管理方法、識別マーク印字装置および識別マーク読取装置
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
JP3635200B2 (ja) * 1998-06-04 2005-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
TW587332B (en) * 2000-01-07 2004-05-11 Canon Kk Semiconductor substrate and process for its production

Also Published As

Publication number Publication date
JP2003078115A (ja) 2003-03-14
WO2003021681A1 (fr) 2003-03-13

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