TW550734B - High dielectric constant gate oxides for silicon-based devices - Google Patents

High dielectric constant gate oxides for silicon-based devices Download PDF

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TW550734B
TW550734B TW090102046A TW90102046A TW550734B TW 550734 B TW550734 B TW 550734B TW 090102046 A TW090102046 A TW 090102046A TW 90102046 A TW90102046 A TW 90102046A TW 550734 B TW550734 B TW 550734B
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semiconductor device
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Minghwei Hong
Ahmet Refik Kortan
Jueinai Raynien Kwo
Joseph Petrus Mannaerts
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Lucent Technologies Inc
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
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Description

550734 ⑴ .^,.；：^i：：：-：:x：：〇 ΐ|：:· B'^i：：：:：;；::1ν：：；?：：;：ΐ:：·:：::;'ΐ:;:：ΐ：：·:·:::;i:' ::·:::：ΐ：: ·;:ίί: :::ΐ:：·ν ：：-：-：:； :； ； .；I； 玖、發明說明 (發〜明itt、▲明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 技術領域 本發明係關於一種改良閘極氧化物物質及其形成方法 供矽基裝置，特別是關於使用稀土氧化物如Gd2〇3或 Y 2〇 3(顯示介電常數£約為1 8 )以形成具有所欲絕緣性而 保持厚度大於隧穿深度為約1 〇 A之閘極氧化物。 發明之昔景 隨著積體電路技術之進展，MOSFETs之閘極長度變得更 小。另外，閘極介電質，通常為·閘極氧化物之厚度變得愈 來愈薄。次微米MOS裝置時常需要極薄閘極氧化物（即， 低於50A)。 由於裝置尺寸因技術進展而迅速按比例縮減，薄閘極肩 化物中之電場持續增加。該增加之電場之部份結果為在肩 化物界面或薄氧化物内之增加的截留產生。截留產生及多 道電子因味之截捕導致低頻率（1/f)噪音與跨導（gm)降^ 《增加。對於低於5GA之超薄問極氧化物，㈣電流亦§ 得顯著並引起裝置特性之加速降低。的確，傳統抓間法 虱化物之"薄度"現接近量子隧穿限度為i〇a。 二代替企圖持續減少閘極氧化物之Si〇2厚纟，若干團體〆 試發現具有介電常數（ε )實質 ^ Κ貝上大於Sl〇2( ε =3.9)之取十 &緣體，使介電厚度可按比 讽签a仏、 9刀1猎以減少隧穿電流i 定，偟可除^也 疋”私貝對矽表面為熱動力上奇 卑了防止反應導致在高溫火 物A念衧/入Λ 入课作時Sl〇2或金屬矽乂 物在底材/介電界面之形成。 战&今，若干，，高介電”氧化4 -6- 550734
(2) (2) 已被考慮（如Al2〇3，Ta203，Ti02)，但在各情況下， 在· Μ 極氧化物之生長時，至少10Α厚之界面Si〇2層形〜 JLJU 寻羡 替代方式使用相當薄SiNx障壁層，其首先沈積在碎表面 以防止天然氧化物之生長。然而，使用障壁+ 上 ▼兩要全部，丨 有效，，氧化物厚度超過1 5 A，另一種可接受的結果 因此，在此技藝中仍需一種介電物質用作”薄，，閘極介个 質在碎基裝置上，其可防止天然Si〇2層之形成，但亦顯: 靠近10A之有效厚度。 /、不
概述 習知技藝中尚待之需要由本發明實現，其係關於一種$ 良間極氧化物物質及其形成方法供矽基裝置，特別是關' 使用稀土氧化物如GhO3或Yew顯示介電常數ε明顯； 於Si〇2者（大約4)，例如約為1 8)以形成具有所欲絕緣性 保持厚度大於隧穿深度為約1 〇 A之閘極氧化物。
Gd2〇3或Υ2〇3之膜係使用超高真空（UHV)蒸氣沈積法， 據本發明生長在”乾淨，，矽底材表面上。頃發現在生長時
藉限制氧分壓低於1〇_7，碎底材表面之氧化會完全避A 磊晶及非晶膜被發現形成具有所欲高介電常數特性、— 化物。 '^氧 根據本發明，較佳使用鄰近（100)之矽底材，俾可 trtr 進 早區’（110)—定向之Gd2〇3或Y2〇3膜之形成。在較佳 #丨士 丹體 U中’可使用4 °誤切底材。 後如工氣體回火法亦可使用以改良漏電流密 1(ri 句反目例如 A/cm2至l〇-5A/cm2之值，在1V供Gd203層，在本田。 3 q 杜 * T Si〇2 550734 (3) 厚度為19A。 在以下說明中及參照附圖當可更加明白本發明之其他 態樣。 附圖之簡單說明 現參照附圖， 圖1顯示一典型連位矽底材，其較佳供支持本發明之高 介電閘極氧化物之生長； 圖2包含X射線衍射掃描過一組為三種不同（110) Gd203 單區膜之圖表； 圖3顯示由Gd20 3膜之變質定向造成之{222}反射，例示 膜厚與較佳定向之區間之關係； 圖4包含結晶Gd203膜之漏電流密度（JL)對電壓（V)之圖 表； 圖5為非晶系Y203膜之漏電流密度對電壓之圖表； 圖6例不比電客作為早晶G d 2〇 3生長在連位碎底材上之 電壓之涵數；及 圖7例示比電容作為非晶系Y203生長在傳統矽底材上之 電壓之涵數。 詳細說明 基於熱動力能量之考慮，稀土氧化物為各種半導體應用 之適當候選。根據本發明，頃發現可形成介電質Gd203( ε 〜12)或Υ2Ο 3( ε〜18)作為閘極氧化物在碎（100)表面上。二 物質均顯示所需”高π介電質，當比較於Si02( ε =3.9)者， 但Υ 2〇 3被認為較佳，由於其較高介電常數及磁性離子不存 550734 (4) 在於氧化物内。 本發明之一重要態樣為使用鄰近（100)之矽底材以消除 不宜區於生長氧化物内之形成，因此提供單區，（110) — 定向之閘極氧化物。圖1例示一典型鄰近（100)之矽底材 10，其在預定傾斜角度被”誤切”，其中範圍為4-6°之傾 斜角度被發現為較佳。誤切表面1 2暴露雙原子層之表面步 驟14，因此提供空間大約80A(對4°誤切）之單區矽台供長 晶化Gd203或Y203之單一變異體之生長。 在形成本發明之高介電閘極氧化物結構中，可使用多室 超高真空系統。在生長介電質以前，清潔矽晶元，然後使 氫鈍化（使用緩衝HF酸，例如）以形成不具雜質之表面。然 後，底材被加熱至溫度範圍為，例如，4 5 0 - 5 0 0 °C，容許 不具雜質或氧化物之矽表面之產生。然後，Gd203或Y203 之電力包裝之陶瓷源在UHV系統内用作電子來源，以提供 所欲磊晶介電膜之沈積。根據本發明之一態樣，UHV室内 之氧分壓必須在生長時保持在低於10·7托爾，其中該壓力 被發現實質上可除去天然Si02層在底材與介電質間之界 面之形成。如上所述，控制在原子層標度之界面之結構及 化學性很重要。 該天然氧化物膜之存在/不存在係藉實施Gd203氧化物 膜及用下方矽底材之缔合界面之紅外線吸收分析來研 究。在分析時為了保持Gd203膜之整合性，薄非晶矽膜在 大氣暴露前在原位沈積在Gd203膜上。此矽膜之存在可HF 蚀刻非晶前及結晶後碎表面，使之留下Η終端且僅確保界 550734 , (5) 面天然氧化物會促進IR吸收光譜。為了比較起見，含Gd203 介電膜之各晶元稱為類似HF蝕刻之矽底材-沒有Gd203膜 沈積。吸收結果清楚顯示Gd203聲子帶在600cm·1，其中其 強度按膜厚度調整。對結晶及非晶Gd203樣品，在8丨〇2之 TOClOSOcnT1)或 LOCUOO-USOcm·1)頻率，有缺少任何可 測定Si02相關之特性.。
Gd2〇3或Y2〇3之晶體具有大晶格常數（分別為lo.giA及 1 0.6 0 Α)之同晶Μη2〇3結構。研究顯示二倍對稱性之（丨！ 〇) 定向之G d 2〇3及Y 2〇3會生長在傳統四倍對稱性之（丨〇 〇)碎 表面，導致相等或然率之二（11 ·〇)變異體於生長平面内之 不宜形成。特別是，此二具有相等或然率之變異體之生長 導致具有相當南漏電流之氧化物，顯然對裝置上考慮不 利。根據本發明，二倍變質係使用連位矽底材除去，如圖 1所示。 後生長加工亦可應用於本發明之方法中，如以下將詳細 說明，後形成氣體回火顯示提供漏電流密度之改良自 lO^A/cm2 至 l(T5A/cm2 在 iv 供 Gd2〇j，在等價 Si〇i厚度為 19A。非晶系Y2〇3膜可形成在傳統碎表面上，其顯示漏電 流低至l(T6A/cm2在1 V供Si〇2等價厚度為10Α。 圖2例示沿三個不同Gd2〇3膜之表面之縱向X射線衍射掃 描。圖2之掃描A與厚度34A之Gd2〇3膜相關，掃描B與厚度 125人之0(12〇3膜相關，而掃描（：與具有厚度為196人之〇(1203 膜相關。參照圖2 ’在各掃描上之邊緣圖案歸因於空氣/ 氧化物與氧化物/碎界面間之相干干涉。雖然邊緣期間與 -10· (6) (6)550734 膜厚度成反比，邊緣振幅之衰變為膜厚度均勻性之測定。 因此，緩慢衰變，如各掃描所示，導致各生長GhO3膜為 極均勻。有關圖2 (以及下圖）討論之各種氧化物厚度被視 為僅為例示性。通常，根據本發明形成之高介電氧化物可 包含厚度範圍為，例如，1 〇 - 5 0 〇 A内並提供所欲閘極介電 特性供所有預期裝置應用。 根據本發明生長在連位（100)矽底材上之Gd2〇3閘極介 電膜被發現顯示寬峰接近20 =47.5。供（440)反射，峰隨著 增加之膜厚變得更尖。圖3特別例示一組為3 6 〇。0掃插， 有關垂直於{222}反射之平面内·組件供圖2相關之三種不 同Gd2〇3膜之組。在各情況下，生長之介電質主要定向於 一類區，與平行於矽步驟緣16(參照圖丨）之Gd2〇;之㈧ 軸線，即，誤切底材10之[1 10]軸線。圖3所示對各介電質 厚度之{222 }反射例示與二定向相關之尖峰。二個弱導， 圖3標示為1及W2，對二個強峰，標示為％及％，係由疋 所分離。圖3數據之分析得結論為，幾乎34人厚〇(12〇3介= 質之95%以較佳（”強”）定向生長，對較厚之196人膜，百Z 比增至約9 9 %。此分析導致結論為，除了有些”臨界”厚度 (大約1〇〇A)以外，具有不希望定向之區開始埋入仍生長二 氧化物下方。 圖4為漏電泥密度，JL，作為閘極電壓之涵數，在各種 條件下供各種GhO3介電層之圖表。二區與單區膜被呈 現，並包括於圖4内為隨後在溫度4〇〇。〇下後形成氣體回火 1小時（圖4標示為”D)之單區34人厚Gd2〇3膜之漏電流/閉極 -11 - 550734
(7) 電壓又圖表。參照圖4，顯然漏電流密度對未偏壓間極 (即〇 V施加之電壓）基本上為對稱。二區介電膜之漏電流 备度顯7F明顯高於單區膜相關者，特別對薄於丨〇〇 A之介 電〶。如所示，對二區膜44A厚之漏電流密度可在〇編壓 下咼至l〇-3A/Cm2。單區介電質之漏電流密度會顯著改 良’特別在較小膜厚度。例如，對34A厚膜在1^之jL係自 對二區膜約-l〇-iA/cm2之值降至對單區介電質約 10 °A/Cm2之值。如上所述，將生長之介電質實施後形成 之氣體回火（N2與η2之組合）會進一步改良（即，減少）漏電 流密度。如圖4所示，在單區34 Α膜上之形成氣體回火導 致進一步改良漏電流密度至值為約1CT5 A / c m2。 非晶系介電膜之研究提出，由於區邊界之不存在及較後 表面或界面應力之缺乏，此等膜會較結晶膜更適合裝置鹿 用。此外，雖然非晶系Gd2〇3膜之漏電流可比較於非晶系 Y2〇3膜，但Y2〇3顯示較Gd2〇3更一致性介電行為，即，Y2〇: 之介電常數實質上仍恒定在約1 8，而與厚度減少無關。圖 5頜不JL依附在ν上供一系列非晶系Υ2〇3膜用。如所示，如 此沈積之非晶系丫2〇3膜45Α厚可得相當低漏電流密度為 10 6A/cm2在IV對等價Si〇2厚度（"teq")僅為ΐ〇Α。漏電流密 度在开^成之氣體回火（例如，在溫度為4 0 0 °C下約1小時） 後由另一數量級改良。所得值約為5數量級優於與傳統 15A厚Si〇2介電質相關之最佳數據。除了此漏電流密度以 外在1 〇⑽C下實施快速熱回火（RTA)约1分鐘顯示丫2〇^ 膜實質上仍穩定。 -12- 550734
包括GhO3單區196A厚間極介電質（在形成之氣體回火 後）之MOS二極管之比電容（C/A)對電壓數據示於圖6作為 範圍為100 Hz至1 MHz之頻率涵數。該膜之介電常數（己） 被測定以顯示值約為20。如所示，M〇s二極管行為自累積 至耗盡模式之轉變在約2V下發生。載體（孔）之反轉明顯貝 接者AC信號到達頻率為1〇 kHz。圖7例示45人厚非晶系 Y2〇3膜（在後生長形成之氣體回火後）之C/A對v數據。電容 器比較於10A厚Si〇2等價（或更佳）具有c/Α值高達35_4〇fF/ # m2。須知與此物質相關之介電常數仍在值為丨8下，即 使在此薄層亦然。 · 本發明已參照特殊較佳具體例說明，但熟悉此技藝者可 在本發明之精神及範圍内作各種改變。例如，雖然Gd2〇3 及Y2〇3已詳述’亦可使用單晶及非晶形式之形式Mn2〇3之 其他稀土氧化物，以根據本發明之原理產生高介電閘極氧 化物。
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Claims (1)

  1. 550734 拾、申請專利範圍 1. 一種半導體裝置，包括 鄰近（10 0)之矽底材，顯示預定角度誤切，俾可沿[110] 方向形成顯示樓梯圖案之頂主表面；及 形式Μη 20 3之稀土氧化物，顯示介電常數ε ^4，在 氧分壓低於10-7托爾下沈積至預定厚度t在該連位矽底 材之樓梯狀主表面上而未在其間形成Si〇2膜。 2 .根據申請專利範圍第1項之半導體裝置，其中稀土氧化 物包括G d2〇 3。 3.根據申請專利範圍第2項之半導體裝置，其中Gd203包 括羞晶G d 2〇 3。 4 .根據申請專利範圍第2項之半導體裝置，其中稀土氧化 物包括二區（100)Gd203結構。 5 .根據申請專利範圍第2項之半導體裝置，其中稀土氧化 物包括單區（100)Gd2O3結構。 6. 根據申請專利範圍第1項之半導體裝置，其中稀土氧化 物包括Y2〇3。 7. 根據申請專利範圍第6項之半導體裝置，其中Υ203包括 羞晶 Υ 2〇 3 〇 8 .根據申請專利範圍第6項之半導體裝置，其中稀土氧化 物包括二區（100)Υ2〇3結構。 9.根據申請專利範圍第6項之半導體裝置，其中稀土氧化 物包括單區（100)Υ2〇3結構。 10·根據申請專利範圍第1項之半導體裝置，其中稀土氧化 550734
    物被形成以包括厚度範圍為1〇Α至5 00A。 11. 根據申請專利範圍第1項之半導體裝置，其中連位矽底 材包括預定角度誤切範圍為4-6° 。 12. 根據申請專利範圍第1 1項之半導體裝置，其中預定角 度誤切為約4° ，在矽底材主表面為約80A上形成平台 空間。 13. —種半導體裝置，包括 界定為包含頂主表面之矽底材；及 形式Μη203之非晶系稀土氧化物並顯示介電常數ε -4,在氧分壓低於1(Γ7托爾下沈積至預定厚度t在矽底 材之頂主表面上而未在其間形成Si02膜。 14·根據申請專利範圍第1 3項之半導體裝置，其中非晶系 稀土氧化物包括Gd203。 15·根據申請專利範圍第1 3項之半導體裝置，其中非晶系 稀土氧化物包括Y203。 16. —種形成包含高介電氧化物層之半導體裝置之方法， 該方法包括之步驟為： a) 提供鄰近（100)之矽底材，在其主表面上例示預定 角度誤切，俾可在該主表面上形成樓梯圖案； b) 清潔該矽主表面以除去雜質及氧化物； c) 將該底材插入包含氧周圍氛圍之超高真空系統内； d) 提供陶瓷稀土氧化物源； e) 減少該超高真空系統内之氧分壓至低於或等於 1 0 - 7托爾之位準； 550734
    f) 在該連位矽底材之該樓梯圖案主表面上以電子束 蒸發預定厚度之該陶瓷稀土氧化物。 17. 根據申請專利範圍第1 6項之方法，其中在實施步驟a) 中，鄰近（100)之矽底材被誤切至預定角度範圍為4-6 〇 〇 18. 根據申請專利範圍第1 7項之方法，其中在實施步驟a) 中，鄰近（100)之矽底材被誤切至預定角度為約4° ，形 成具有階段高度為約80A之樓梯圖案。 19. 根據申請專利範圍第1 6項之方法，其中在實施步驟b) 中，珍底材係由緩衝H F溶液純化之氫清潔。 20·根據申請專利範圍第1 6項之方法，其中在實施步驟d) 中，提供陶瓷Gd203。 21·根據申請專利範圍第1 6項之方法，其中在實施步驟d) 中，提供陶瓷Y2〇3。 22·根據申請專利範圍第1 6項之方法，其中在實施步驟f) 中，形成具有厚度範圍為10 A-5 00 A之稀土氧化物層。 23. 根據申請專利範圍第1 6項之方法，其中該方法進一步 包括步驟為： g) 在預定溫度下氣體回火稀土氧化物介電層一段預 定時間足以減少漏電流密度至預界定值。 24. 根據申請專利範圍第23項之方法，其中在實施步驟g) 中，裝置被加熱至溫度為約4 0 0 °C歷約1小時。 25. 根據申請專利範圍第2 3項之方法，其中在實施步驟g) 中，氣體回火為預界定之H2與N2混合物。 550734
    26. 根據申請專利範圍第23項之方法，其中在實施步驟g) 中，進行在溫度為約1 0 0 0 °C下快速熱回火約1分鐘。 27. —種形成包含高介電氧化物層之半導體裝置之方法， 該方法包括之步騾為： a) 提供界定為包含頂主表面之矽（100); b) 清潔該矽主表面以除去雜質及氧化物； c) 將該底材插入包含氧周圍氛圍之超高真空系統内； d) 提供陶瓷稀土氧化物源； e) 減少該超高真空系統内之氧分壓至低於或等於 10-7托爾之位準； · 0以電子束蒸發預定厚度之該陶瓷稀土氧化物以碎 頂主表面上形成非晶系稀土氧化物層。 28. 根據申請專利範圍第2 7項之方法，其中在實施步騾d) 中，提供陶瓷Gd203。 29. 根據申請專利範圍第27項之方法，其中在實施步驟d) 中，提供陶瓷Y203。
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