TW546744B - Method for the fabrication of a DMOS transistor - Google Patents
Method for the fabrication of a DMOS transistor Download PDFInfo
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- TW546744B TW546744B TW090126394A TW90126394A TW546744B TW 546744 B TW546744 B TW 546744B TW 090126394 A TW090126394 A TW 090126394A TW 90126394 A TW90126394 A TW 90126394A TW 546744 B TW546744 B TW 546744B
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 61
- 239000011241 protective layer Substances 0.000 claims abstract description 17
- 210000000746 body region Anatomy 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 230000010354 integration Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
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- 238000010438 heat treatment Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
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- 239000007943 implant Substances 0.000 description 2
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- 241000293849 Cordylanthus Species 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
546744 A7 B7 五、發明説明(1 ) 本發明與製造DMOS電晶體的方法有關,尤其是與已經 在半導體組件内和CMOS邏輯整合的DMOS電晶體之製造方 法有關。 在許多現代電子產品的應用中,除了純資料處理以外, 電子產品必須與其週遭環境融合在一起,這種應用包含非 常廣泛的產品範圍‘。有一個可以提及的範例就是氣囊的控 制系統,它一方面要評估來自加速感知氣的測量訊號,而 另一方面在碰撞事故中,還要負責引爆氣囊。進一步的範 例為充電電池的智慧型充電器。 為了成本因素,最好的方式就是將所有不同功能都整合 到一個半導體產品内。不過當製造這種「聰明功率」產品 時,在製造過程上就會加諸許多高級要求。例如,許多種 組件(像是CMOS電晶體、DMOS電晶體、DMOS功率電晶體 以及雙極電晶體)都必須將高封裝密度整合在晶片上。而 .整合方式、應該是個別組件種類要儘可能有理想的組件參數 ,不過在此同時,製作處理應該牽涉到最少的處理步驟數 量,尤其是少量的光罩等級。 一或多個DM〇S功率電晶體以及CMOS邏輯的整合通常牽 涉到兩楂不同閘氧化物/閘聚合復合體的使用。在此方法中 ,可依照特定需求將DMOS電晶體的裝'置參數以及CMOS 電晶體的裝置參數設定成大體上彼此獨立。在此將似圖1 a 至If内DMOS電晶體♦區域内圖解截面圖為基礎,來概略描述 兩閘氧化物/閘聚合複合體整合所牽涉到的典型處理順序。 為了製造DMOS電晶體,將提供半導體基板1,其上已經 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 546744 A7 B7 五、發明説明(2 ) 產生個別電晶體2與閘氧化物3之間的絕緣體。然後沉積一 多晶矽層4,並在此多晶矽層4上沉積一絕緣層5,然後藉由 光微影蝕刻在多晶矽層4以及絕緣層5上製作圖樣,形成 DMOS閘堆疊(圖la)。 然後覆蓋上用第二光微影蝕刻平面製作圖樣的光致抗蝕 劑6,藉由將DMOS電晶體本體8與源極9的摻雜物植入 DMOS電晶體源極區域(圖lb)之幫助,光致抗蝕劑6的圖樣 會形成光罩。 在經過熱處理之後,植入的摻雜物會擴散出來並且形成 DMOS電晶體的本體8與源極9(圖lc)。無結晶源極植入通常 會導致晶體缺陷。在DMOS電晶體的本體8與源極9形成之後 ,除了連接植入以外,DMOS電晶體的製造大體上已經完成 。不過,之後仍舊會接著用於製造CMOS電晶體(未顯示) 的進一步處理步驟,而這些步驟當然會影響大體上完成的 DMOS電晶體。 , 然後將作用區域蝕刻乾淨。在DMOS電晶體的區域内, 這會造成將DMOS電晶體的源極蝕刻乾淨。在此會將 CMOS電晶體區域内作用區域蝕刻乾淨的步驟當成製作 CMOS電-晶體的閘氧化物之準備,此蝕刻步驟會進行 DMOS閘堆疊下DMOS閘氧化物的蝕刻體10之過度切割(圖 Id)。 , 然後製造CMOS的閘氧化物,並且在此CMOS閘氧化期間 ,曝露出來的DMO?閘聚合側邊會在DMOS電晶體的區域内 氧化,並且增加過度切割蝕刻體10區域内以及到源極9過度 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 546744 五、發明説明(3 ) 區内的DMOS電晶體之閘氧化物厚度(「鳥缘」)。這具有臨 界電壓無法控制的影響’而大幅增加其散射。之後接著另 一個多晶石夕層11的;;冗積,沉積在CM〇s電晶體的區域内,用 來製造CMOS閘堆疊(圖ie)。 在後續CMOS閘電極的圖樣製作中,已知的間隔裝置12 留在DMOS閘電極的側邊上(圖lf),並且因為多晶矽突出的 緣故而無法完全去除。這些高度摻雜的多晶矽間隔裝置12 對於DMOS電晶體臨界電壓的散射以及可達成的生產都有不 利的影響。 從先前技藝中可以看出,製作CMOS電晶體會對已經產生 的DMOS電晶體造成許多不利的影響,並且對於DM〇s電晶 體裝置參數是相當不利的影響,甚至有可能使整個積體組 件失效。 因此,本發明的目的就是提供一種可降低或完全避免上 •述問題的DMOS電晶體結構製造方法。 由申請專利範圍早1項内說明的方法可達成此目的,本發 明進一步有利的具體實施例、組態以及領域都附加在附屬 項、說明以及圖式中。 本發明提供一種用於製造DMOS電晶體結構的方法,該 方法包含下列步驟: , a) 提供具備閘氧化物的半導體基板, , b) 在該閘氧化物上覆蓋一導電層, c) 對該導電層製作圖樣,大體上只將位於源極區域上的' 導電層部分去除, -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱) 546744 A7 B7 五、發明説明(4 ) d) 產生本體區域以及源極區域’ e) 供應至少一保護層, f) 在該保護層以及導電層上製作圖樣,如此會產生閘電 極,以及 g) 去除至少該源極區域上的保護層。 本發明具有一項優點,就是透過使用保護層來保護大體 上已經完成的DMOS電晶體結構,避免受到進一步處理步驟 不利的影響。根據本發明,DMOS閘電極並不像先前步驟一 樣用單一光微影步驟來製作圖樣,而是將DMOS閘電極的圖 樣製作分成兩個光微影步驟。在第一個先微影步驟内,大 體上只會開啟DMOS電晶體結構的源極區域。因此,就可使 用仍舊存在的電極層當成後續本體區域製作的光罩。 在製造對於DMOS電晶體結構來說非常重要的本體與源 極之過程部分執行後,在藉由進一步光微影步驟做DMOS閘 _電極最終結構化期間,將供應保護層並且維持在源極區域 上,在進一步處理(例如製造CMOS電晶體或雙極電晶體) 期間保護後者。儘管有DMOS閘電極的圖樣製作分成兩個光 微影等級之事實,彳旦還是可在不增加光微影步驟的情況下 執行依照本發明的方法,這是因為省略了先前技藝内用於 本體植入的光罩。 ’ , 在此所使用的導電層最好是多晶矽層。更進一步〃保護 層較好电一氧化 <夕層、一氮化^夕層、一氧化碎層所構成。 在此情況下,更好是所使用的氧化矽層是TEOS層。 根據較佳具體實施例,DMOS電晶體與CMOS電晶體整合 本紙張尺;度適用中國國家標準(CNS) A4規格(210 X 297公釐) 546744 A7 ___ B7_ 五、發明説明(5 ) 在半導體組件内。在此情況下,保護層特別用來保護大體 上已經完成的DMOS電晶體結構,避免受到進一步用來製造 CMOS電晶體的閘氡化物/閘電極處理步驟之不利影響。 因此最好是’在步驟f)與步驟g)之間產生CMOS電晶體的 閘氧化物。更進一步,較好在步驟f)與步驟g)之間產生 CMOS電晶體的閘電極。依照進一步較佳具體實施例,將執 行蝕刻以便去除源極區域上剩餘的CMOS電晶體閘電極。 下面將參考圖式以便更詳細說明本發明,其中: 圖1 a到1 f圖解說明依照本發明的方法, 圖2a到2f圖解說明依照本發明的方法。 圖2a到2f圖解說明依照本發明用來製造DMOS電晶體結構 的方法。為了製造DMOS電晶體結構,將提供半導體基板 1 ’其上已經產生個別電晶體與閘氧化物3之間的絕緣體2。 更進一步,所有用來完整製造DMOS電晶體以及CMOS電晶 •體的井區、掩埋區以及深擴散區都已經產生,然後沉積最 好是多晶矽層4的導電層,並且在多晶矽層4上沉積絕緣層 5。接下來,藉由光微影替多晶矽層4以及絕緣層5製作圖樣 ,如此多晶石夕層4大體上只會在源極區域内開啟(圖2a)。多 晶石夕層4仍舊會覆蓋,其他所有區域,尤其是其中大體上會產 生CMOS電晶體的區域。 , 然後,將執行製造本體區域以及源極區域的摻雜物植入 。已經有_圖樣的多晶矽層4會遮蓋住本體8與源極9的植入。 在過程中,首先將植入本體區域的捧雜物,並且利用熱處 理導入半導體基板1内’然後’將植入源極區域的捧雜物, -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) " -- 546744
並且藉纟帛三熱處王里導入半導體基板w。此具有優於傳統 方法的地方,其在本體擴散之後不需要額外的支出就可執 行源極植入。如此減少晶體缺陷的密度,並有助於源極摻 雜的最佳化。較好是,氧化13會將在第一熱處理開始時產 生的開口多晶矽側邊密封起來(焚化步驟)(圖2b)。 然後,將藉由保護層丨4覆蓋源極區域以及剩餘的多晶矽 區域(圖2c)。在本範例内,保護層〗4包含三個獨立層,也就 是氧化矽層14a、氮化矽層14b以及另一個氧化矽層14c。 這三個層最好都借助於CVD處理來產生,而最好是,藉由 TE〇S處理來產生兩氧化石夕層14a、14c。 然後’運用第二光微影钱刻步驟完成dm〇s閘堆疊的製 作圖樣。在此處理中,也會去除所有其他組件區域内的 導電層4,尤其是在還要產生cM0S電晶體(未顯示)的區 域内。 保護層14可用來當成硬光罩,來進行導電層4的蝕刻。 接下來’將作用區域敍刻乾淨。在C Μ 0 S電晶體閘氧化之 前的碎表面蝕刻清潔期間,將去除上TEOS層。不過,氮化 矽層可避免DMOS閘電極的過度切割蝕刻(發生在先前技藝 處理順序-内的此點上)。因此,當程序進行時,也可有效避 免在閘電極邊緣上形成「鳥喙」。這是根據本發明的方法 進一步比先前技藝方法還要好的地方。 — 然後,-藉由濕式蝕刻去除氮層,結果情況顯示在圖2d内 。在行程CMOS電晶體的閘氧化物以及沉積另一個導電層, 尤其是另一個多晶石夕層之前,TEOS層14a仍舊會覆蓋著 • 9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 546744 A7
DMOS源極區域。如此導致進一步* —# 乂 —刀虱化的優點,因此可 貫貝上避免在源極區域的DMOS閘雷托♦ τ 圖2e)。 問電極之下形成「鳥嗓」( 在導電層的圖樣製作期間(為了形成CM〇s電晶體的間電 極剩餘㈣電層通”留在DM0S閘電極旁邊的源極區 域上。這些位於源極區域内的多晶矽殘留物12會利用剩餘 的保護層14(TE〇S層14a)與源極區域和DM〇s閘電極充分隔 離,並且上面所有物體都不再位於DM〇S閘電極的突出區域 下。 藉由額外的光微影步驟也可毫無困難的將這些多晶石夕殘 留物12去除。然後,將產生DMOS電晶體的連接。為此目的 ’就一般慣例而言,在源極9上會產生一區隔裝置(未顯示) ’並執行連接植入,在間隔裝置的產生期間,將去除源極 9上的氧化矽層14a丨如此可在進一步處理步驟内於導電層 (未顯示)與源極9之間製作接點。 -10 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
Claims (1)
- A8 B8 C8 D8 '案而0讲辦利申請案 中文制請秦希i| ^替換本(92年1月) 申请專利祀圍 . 種製造DM0S電晶體結構之方法,包含下列步驟: a) 提供具備閘氧化物(3)的半導體基板(1), b) 在該閘氧化物上覆蓋一導電層(4), c) 對孩導電層(4)製作圖樣,大體上只將位於源極區域 (9)上的導電層(4)部分去除, d) 產生本體區域(8)以及源極區域(9), e) 供應至少一保護層(14), f) 在該保護層(14)以及導電層(4)上製作圖樣,如此會產 生閘電極,以及 g) 去除至少該源極區域(9)上的保護層(14)。 2.如申請專利範圍第丨項之方法,其特徵在於使用一多晶矽 層來作為一導電層(4p 3 ·如申印專利範圍第丨項之方法,其特徵在於該保護層 (14)包含一氧化矽層(14a)、一氮化矽層(i4b)' 一氧化矽 層(14c) 〇 4.如申叫專利範圍第2項之方法,其特徵在於該保護層 (14)包含一氧化矽層〇4a)、一氮化矽層(i4b)、一氧化矽 層(14c)。 5·如申請專利範圍第2項之方法,其特徵在於使用的氧化矽 層(14a、14c)作為 TE0S 層。 6·如申請專利範圍第2至5項中任一項之方法,其特徵在 於DM0S電晶體會與CM〇s電晶體整合到一半導體組件 内0 7.如申請專利範圍第丨項之方法,其特徵在於1)河〇3電 A B c D 546744 六、ΐ請專利範圍 體會與CMOS電晶體整合到一半導體組件内。 8. 如申請專利範圍第7項之方法,其特徵在於在步驟f)與步 騾g)之間產生CMOS電晶體的閘極氧化物。 9 · 如申請專利範圍第7或8項之方法,其特徵在於在步驟f) 與步驟g)之間產生CMOS電晶體的閘電極。 10·如申請專利範圍第7或8項之方法,其特徵在於將執行蝕 刻,以便去除源極區域(9)上CMOS電晶體閘電極的殘留 物(12)。 11.如申請專利範圍第9項之方法,其特徵在於將執行蝕刻, 以便去除源極區域(9)上CMOS電晶體閘電極的殘留物 (12) 〇 -2- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X297公釐)
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DE10053428A DE10053428A1 (de) | 2000-10-27 | 2000-10-27 | Verfahren zur Herstellung eines DMOS-Transistors |
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EP (1) | EP1328970B1 (zh) |
JP (1) | JP2004512694A (zh) |
KR (1) | KR20030038808A (zh) |
CN (1) | CN1227723C (zh) |
AT (1) | ATE349074T1 (zh) |
DE (2) | DE10053428A1 (zh) |
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JPH03175678A (ja) * | 1989-12-04 | 1991-07-30 | Sharp Corp | 半導体装置の製造方法 |
IT1254799B (it) * | 1992-02-18 | 1995-10-11 | St Microelectronics Srl | Transistore vdmos con migliorate caratteristiche di tenuta di tensione. |
US5382536A (en) * | 1993-03-15 | 1995-01-17 | Texas Instruments Incorporated | Method of fabricating lateral DMOS structure |
US5739061A (en) * | 1993-10-26 | 1998-04-14 | Fuji Electric Co., Ltd. | Method of manufacturing a semiconductor device using gate side wall as mask for self-alignment |
US5874340A (en) * | 1996-07-17 | 1999-02-23 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls |
KR100223600B1 (ko) * | 1997-01-23 | 1999-10-15 | 김덕중 | 반도체 장치 및 그 제조 방법 |
KR20000051294A (ko) * | 1999-01-20 | 2000-08-16 | 김덕중 | 전기적 특성이 향상된 디모스 전계 효과 트랜지스터 및 그 제조 방법 |
US6492678B1 (en) * | 2000-05-03 | 2002-12-10 | Linear Technology Corporation | High voltage MOS transistor with gate extension |
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2000
- 2000-10-27 DE DE10053428A patent/DE10053428A1/de not_active Withdrawn
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2001
- 2001-10-17 CN CNB018181422A patent/CN1227723C/zh not_active Expired - Fee Related
- 2001-10-17 EP EP01988948A patent/EP1328970B1/de not_active Expired - Lifetime
- 2001-10-17 AT AT01988948T patent/ATE349074T1/de not_active IP Right Cessation
- 2001-10-17 WO PCT/EP2001/012035 patent/WO2002035600A2/de active IP Right Grant
- 2001-10-17 JP JP2002538479A patent/JP2004512694A/ja not_active Withdrawn
- 2001-10-17 KR KR10-2003-7005050A patent/KR20030038808A/ko not_active Application Discontinuation
- 2001-10-17 DE DE50111707T patent/DE50111707D1/de not_active Expired - Lifetime
- 2001-10-25 TW TW090126394A patent/TW546744B/zh active
-
2003
- 2003-04-25 US US10/424,019 patent/US6852598B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1328970A2 (de) | 2003-07-23 |
ATE349074T1 (de) | 2007-01-15 |
KR20030038808A (ko) | 2003-05-16 |
EP1328970B1 (de) | 2006-12-20 |
CN1471729A (zh) | 2004-01-28 |
WO2002035600A3 (de) | 2002-11-07 |
DE50111707D1 (de) | 2007-02-01 |
DE10053428A1 (de) | 2002-05-16 |
JP2004512694A (ja) | 2004-04-22 |
WO2002035600A2 (de) | 2002-05-02 |
US20030190778A1 (en) | 2003-10-09 |
US6852598B2 (en) | 2005-02-08 |
CN1227723C (zh) | 2005-11-16 |
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