TW541507B - Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (blt) in parallel - Google Patents

Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (blt) in parallel Download PDF

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Publication number
TW541507B
TW541507B TW090124151A TW90124151A TW541507B TW 541507 B TW541507 B TW 541507B TW 090124151 A TW090124151 A TW 090124151A TW 90124151 A TW90124151 A TW 90124151A TW 541507 B TW541507 B TW 541507B
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TW
Taiwan
Prior art keywords
graphics
source
blt
pixel data
controller
Prior art date
Application number
TW090124151A
Other languages
English (en)
Chinese (zh)
Inventor
Brian K Langendorf
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW541507B publication Critical patent/TW541507B/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
TW090124151A 2000-09-28 2001-09-28 Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (blt) in parallel TW541507B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/671,237 US6630936B1 (en) 2000-09-28 2000-09-28 Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel

Publications (1)

Publication Number Publication Date
TW541507B true TW541507B (en) 2003-07-11

Family

ID=24693676

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090124151A TW541507B (en) 2000-09-28 2001-09-28 Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (blt) in parallel

Country Status (10)

Country Link
US (1) US6630936B1 (https=)
EP (1) EP1325470A2 (https=)
JP (1) JP3996054B2 (https=)
KR (1) KR100528955B1 (https=)
CN (1) CN100395734C (https=)
AU (1) AU2001296282A1 (https=)
DE (1) DE10196696T1 (https=)
GB (1) GB2384151B (https=)
TW (1) TW541507B (https=)
WO (1) WO2002027658A2 (https=)

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US7474312B1 (en) * 2002-11-25 2009-01-06 Nvidia Corporation Memory redirect primitive for a secure graphics processing unit
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US7292235B2 (en) * 2003-06-03 2007-11-06 Nec Electronics Corporation Controller driver and display apparatus using the same
US6952217B1 (en) * 2003-07-24 2005-10-04 Nvidia Corporation Graphics processing unit self-programming
US8446417B2 (en) * 2004-06-25 2013-05-21 Nvidia Corporation Discrete graphics system unit for housing a GPU
US8411093B2 (en) * 2004-06-25 2013-04-02 Nvidia Corporation Method and system for stand alone graphics independent of computer system form factor
US8941668B2 (en) * 2004-06-25 2015-01-27 Nvidia Corporation Method and system for a scalable discrete graphics system
US9087161B1 (en) 2004-06-28 2015-07-21 Nvidia Corporation Asymmetrical scaling multiple GPU graphics system for implementing cooperative graphics instruction execution
US20060012602A1 (en) * 2004-07-15 2006-01-19 George Lyons System and method for efficiently performing automatic partial transfers of image data
JP4049136B2 (ja) * 2004-08-10 2008-02-20 ブラザー工業株式会社 画像処理装置及びプログラム
US7633505B1 (en) 2004-11-17 2009-12-15 Nvidia Corporation Apparatus, system, and method for joint processing in graphics processing units
US7598958B1 (en) * 2004-11-17 2009-10-06 Nvidia Corporation Multi-chip graphics processing unit apparatus, system, and method
US7502947B2 (en) * 2004-12-03 2009-03-10 Hewlett-Packard Development Company, L.P. System and method of controlling a graphics controller
KR101110624B1 (ko) * 2004-12-15 2012-02-16 삼성전자주식회사 그래픽 처리 기능을 갖는 메모리 컨트롤러
US20060198175A1 (en) * 2005-03-03 2006-09-07 Badawi Ashraf H Method, system, and apparatus high speed interconnect to improve data rates of memory subsystems
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US10026140B2 (en) 2005-06-10 2018-07-17 Nvidia Corporation Using a scalable graphics system to enable a general-purpose multi-user computer system
US8893016B2 (en) * 2005-06-10 2014-11-18 Nvidia Corporation Using a graphics system to enable a multi-user computer system
US20070067517A1 (en) * 2005-09-22 2007-03-22 Tzu-Jen Kuo Integrated physics engine and related graphics processing system
US7525548B2 (en) 2005-11-04 2009-04-28 Nvidia Corporation Video processing with multiple graphical processing units
US8462164B2 (en) * 2005-11-10 2013-06-11 Intel Corporation Apparatus and method for an interface architecture for flexible and extensible media processing
US7948497B2 (en) * 2005-11-29 2011-05-24 Via Technologies, Inc. Chipset and related method of processing graphic signals
US8212832B2 (en) * 2005-12-08 2012-07-03 Ati Technologies Ulc Method and apparatus with dynamic graphics surface memory allocation
US7477257B2 (en) * 2005-12-15 2009-01-13 Nvidia Corporation Apparatus, system, and method for graphics memory hub
JP5111797B2 (ja) * 2006-06-29 2013-01-09 株式会社東芝 情報処理装置及び情報処理方法
US20080030510A1 (en) * 2006-08-02 2008-02-07 Xgi Technology Inc. Multi-GPU rendering system
US20080259023A1 (en) * 2007-04-19 2008-10-23 Aten International Co., Ltd. Method and System of Making a Computer as a Console for Managing Another Computer
US20080259556A1 (en) * 2007-04-20 2008-10-23 Tracy Mark S Modular graphics expansion system
US8564598B2 (en) * 2007-08-15 2013-10-22 Nvidia Corporation Parallelogram unified primitive description for rasterization
US8634695B2 (en) * 2010-10-27 2014-01-21 Microsoft Corporation Shared surface hardware-sensitive composited video
US10217270B2 (en) 2011-11-18 2019-02-26 Intel Corporation Scalable geometry processing within a checkerboard multi-GPU configuration
US9619855B2 (en) 2011-11-18 2017-04-11 Intel Corporation Scalable geometry processing within a checkerboard multi-GPU configuration
CN103984669A (zh) 2013-02-07 2014-08-13 辉达公司 一种用于图像处理的系统和方法
CN104424661B (zh) * 2013-08-23 2018-01-23 联想(北京)有限公司 三维对象显示方法和装置
US9734546B2 (en) 2013-10-03 2017-08-15 Nvidia Corporation Split driver to control multiple graphics processors in a computer system
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US8266232B2 (en) 2005-10-15 2012-09-11 International Business Machines Corporation Hardware processing of commands within virtual client computing environment
TWI403956B (zh) * 2005-10-15 2013-08-01 Ibm 虛擬客戶計算環境中指令處理伺服器計算裝置、方法與電腦可讀取資料儲存媒體

Also Published As

Publication number Publication date
CN100395734C (zh) 2008-06-18
GB2384151A (en) 2003-07-16
KR100528955B1 (ko) 2005-11-15
GB0306045D0 (en) 2003-04-23
AU2001296282A1 (en) 2002-04-08
EP1325470A2 (en) 2003-07-09
KR20030036822A (ko) 2003-05-09
US6630936B1 (en) 2003-10-07
CN1571991A (zh) 2005-01-26
DE10196696T1 (de) 2003-08-28
WO2002027658A2 (en) 2002-04-04
JP3996054B2 (ja) 2007-10-24
GB2384151B (en) 2004-04-28
WO2002027658A3 (en) 2002-07-18
HK1053895A1 (en) 2003-11-07
JP2004510269A (ja) 2004-04-02

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