KR100528955B1 - 싱글 블록변환의 일부를 두개의 그래픽 컨트롤러 각각이병렬로 실행하게 하는 메커니즘 및 방법 - Google Patents

싱글 블록변환의 일부를 두개의 그래픽 컨트롤러 각각이병렬로 실행하게 하는 메커니즘 및 방법 Download PDF

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Publication number
KR100528955B1
KR100528955B1 KR10-2003-7004217A KR20037004217A KR100528955B1 KR 100528955 B1 KR100528955 B1 KR 100528955B1 KR 20037004217 A KR20037004217 A KR 20037004217A KR 100528955 B1 KR100528955 B1 KR 100528955B1
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South Korea
Prior art keywords
graphics
controller
source
blt
pixel data
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Expired - Fee Related
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KR10-2003-7004217A
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English (en)
Korean (ko)
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KR20030036822A (ko
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란젠도르프브라이언
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인텔 코포레이션
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Publication of KR100528955B1 publication Critical patent/KR100528955B1/ko
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
KR10-2003-7004217A 2000-09-28 2001-09-20 싱글 블록변환의 일부를 두개의 그래픽 컨트롤러 각각이병렬로 실행하게 하는 메커니즘 및 방법 Expired - Fee Related KR100528955B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/671,237 US6630936B1 (en) 2000-09-28 2000-09-28 Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel
US09/671,237 2000-09-28
PCT/US2001/029605 WO2002027658A2 (en) 2000-09-28 2001-09-20 Shared single block transform in parallel

Publications (2)

Publication Number Publication Date
KR20030036822A KR20030036822A (ko) 2003-05-09
KR100528955B1 true KR100528955B1 (ko) 2005-11-15

Family

ID=24693676

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-7004217A Expired - Fee Related KR100528955B1 (ko) 2000-09-28 2001-09-20 싱글 블록변환의 일부를 두개의 그래픽 컨트롤러 각각이병렬로 실행하게 하는 메커니즘 및 방법

Country Status (10)

Country Link
US (1) US6630936B1 (https=)
EP (1) EP1325470A2 (https=)
JP (1) JP3996054B2 (https=)
KR (1) KR100528955B1 (https=)
CN (1) CN100395734C (https=)
AU (1) AU2001296282A1 (https=)
DE (1) DE10196696T1 (https=)
GB (1) GB2384151B (https=)
TW (1) TW541507B (https=)
WO (1) WO2002027658A2 (https=)

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US8446417B2 (en) * 2004-06-25 2013-05-21 Nvidia Corporation Discrete graphics system unit for housing a GPU
US8411093B2 (en) * 2004-06-25 2013-04-02 Nvidia Corporation Method and system for stand alone graphics independent of computer system form factor
US8941668B2 (en) * 2004-06-25 2015-01-27 Nvidia Corporation Method and system for a scalable discrete graphics system
US9087161B1 (en) 2004-06-28 2015-07-21 Nvidia Corporation Asymmetrical scaling multiple GPU graphics system for implementing cooperative graphics instruction execution
US20060012602A1 (en) * 2004-07-15 2006-01-19 George Lyons System and method for efficiently performing automatic partial transfers of image data
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US7633505B1 (en) 2004-11-17 2009-12-15 Nvidia Corporation Apparatus, system, and method for joint processing in graphics processing units
US7598958B1 (en) * 2004-11-17 2009-10-06 Nvidia Corporation Multi-chip graphics processing unit apparatus, system, and method
US7502947B2 (en) * 2004-12-03 2009-03-10 Hewlett-Packard Development Company, L.P. System and method of controlling a graphics controller
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US20060198175A1 (en) * 2005-03-03 2006-09-07 Badawi Ashraf H Method, system, and apparatus high speed interconnect to improve data rates of memory subsystems
US20060282604A1 (en) * 2005-05-27 2006-12-14 Ati Technologies, Inc. Methods and apparatus for processing graphics data using multiple processing circuits
US10026140B2 (en) 2005-06-10 2018-07-17 Nvidia Corporation Using a scalable graphics system to enable a general-purpose multi-user computer system
US8893016B2 (en) * 2005-06-10 2014-11-18 Nvidia Corporation Using a graphics system to enable a multi-user computer system
US20070067517A1 (en) * 2005-09-22 2007-03-22 Tzu-Jen Kuo Integrated physics engine and related graphics processing system
US8266232B2 (en) 2005-10-15 2012-09-11 International Business Machines Corporation Hardware processing of commands within virtual client computing environment
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US7948497B2 (en) * 2005-11-29 2011-05-24 Via Technologies, Inc. Chipset and related method of processing graphic signals
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US7477257B2 (en) * 2005-12-15 2009-01-13 Nvidia Corporation Apparatus, system, and method for graphics memory hub
JP5111797B2 (ja) * 2006-06-29 2013-01-09 株式会社東芝 情報処理装置及び情報処理方法
US20080030510A1 (en) * 2006-08-02 2008-02-07 Xgi Technology Inc. Multi-GPU rendering system
US20080259023A1 (en) * 2007-04-19 2008-10-23 Aten International Co., Ltd. Method and System of Making a Computer as a Console for Managing Another Computer
US20080259556A1 (en) * 2007-04-20 2008-10-23 Tracy Mark S Modular graphics expansion system
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Also Published As

Publication number Publication date
CN100395734C (zh) 2008-06-18
GB2384151A (en) 2003-07-16
TW541507B (en) 2003-07-11
GB0306045D0 (en) 2003-04-23
AU2001296282A1 (en) 2002-04-08
EP1325470A2 (en) 2003-07-09
KR20030036822A (ko) 2003-05-09
US6630936B1 (en) 2003-10-07
CN1571991A (zh) 2005-01-26
DE10196696T1 (de) 2003-08-28
WO2002027658A2 (en) 2002-04-04
JP3996054B2 (ja) 2007-10-24
GB2384151B (en) 2004-04-28
WO2002027658A3 (en) 2002-07-18
HK1053895A1 (en) 2003-11-07
JP2004510269A (ja) 2004-04-02

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