JP3996054B2 - 2つのグラフィック制御器が各々単一のブロック変換(blt)の一部を並列に実行することを可能にするためのメカニズムおよび方法 - Google Patents
2つのグラフィック制御器が各々単一のブロック変換(blt)の一部を並列に実行することを可能にするためのメカニズムおよび方法 Download PDFInfo
- Publication number
- JP3996054B2 JP3996054B2 JP2002531362A JP2002531362A JP3996054B2 JP 3996054 B2 JP3996054 B2 JP 3996054B2 JP 2002531362 A JP2002531362 A JP 2002531362A JP 2002531362 A JP2002531362 A JP 2002531362A JP 3996054 B2 JP3996054 B2 JP 3996054B2
- Authority
- JP
- Japan
- Prior art keywords
- graphic
- graphics
- controller
- source
- blt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2352/00—Parallel handling of streams of display data
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Graphics (AREA)
- Image Generation (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Processing (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/671,237 US6630936B1 (en) | 2000-09-28 | 2000-09-28 | Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel |
| PCT/US2001/029605 WO2002027658A2 (en) | 2000-09-28 | 2001-09-20 | Shared single block transform in parallel |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004510269A JP2004510269A (ja) | 2004-04-02 |
| JP2004510269A5 JP2004510269A5 (https=) | 2005-03-03 |
| JP3996054B2 true JP3996054B2 (ja) | 2007-10-24 |
Family
ID=24693676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002531362A Expired - Fee Related JP3996054B2 (ja) | 2000-09-28 | 2001-09-20 | 2つのグラフィック制御器が各々単一のブロック変換(blt)の一部を並列に実行することを可能にするためのメカニズムおよび方法 |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US6630936B1 (https=) |
| EP (1) | EP1325470A2 (https=) |
| JP (1) | JP3996054B2 (https=) |
| KR (1) | KR100528955B1 (https=) |
| CN (1) | CN100395734C (https=) |
| AU (1) | AU2001296282A1 (https=) |
| DE (1) | DE10196696T1 (https=) |
| GB (1) | GB2384151B (https=) |
| TW (1) | TW541507B (https=) |
| WO (1) | WO2002027658A2 (https=) |
Families Citing this family (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6819440B1 (en) * | 2000-05-15 | 2004-11-16 | International Business Machines Corporation | System, method, and program for automatically switching operational modes of a printer between direct and print-on-demand (POD) modes |
| US6724389B1 (en) * | 2001-03-30 | 2004-04-20 | Intel Corporation | Multiplexing digital video out on an accelerated graphics port interface |
| TW512277B (en) * | 2001-06-22 | 2002-12-01 | Silicon Integrated Sys Corp | Core logic of a computer system and control method of the same |
| US6731292B2 (en) * | 2002-03-06 | 2004-05-04 | Sun Microsystems, Inc. | System and method for controlling a number of outstanding data transactions within an integrated circuit |
| US7076669B2 (en) | 2002-04-15 | 2006-07-11 | Intel Corporation | Method and apparatus for communicating securely with a token |
| US20040083311A1 (en) * | 2002-06-05 | 2004-04-29 | James Zhuge | Signal processing system and method |
| TW577229B (en) * | 2002-09-18 | 2004-02-21 | Via Tech Inc | Module and method for graphics display |
| US7474312B1 (en) * | 2002-11-25 | 2009-01-06 | Nvidia Corporation | Memory redirect primitive for a secure graphics processing unit |
| US20040205254A1 (en) * | 2003-04-11 | 2004-10-14 | Orr Stephen J. | System for media capture and processing and method thereof |
| US7292235B2 (en) * | 2003-06-03 | 2007-11-06 | Nec Electronics Corporation | Controller driver and display apparatus using the same |
| US6952217B1 (en) * | 2003-07-24 | 2005-10-04 | Nvidia Corporation | Graphics processing unit self-programming |
| US8446417B2 (en) * | 2004-06-25 | 2013-05-21 | Nvidia Corporation | Discrete graphics system unit for housing a GPU |
| US8411093B2 (en) * | 2004-06-25 | 2013-04-02 | Nvidia Corporation | Method and system for stand alone graphics independent of computer system form factor |
| US8941668B2 (en) * | 2004-06-25 | 2015-01-27 | Nvidia Corporation | Method and system for a scalable discrete graphics system |
| US9087161B1 (en) | 2004-06-28 | 2015-07-21 | Nvidia Corporation | Asymmetrical scaling multiple GPU graphics system for implementing cooperative graphics instruction execution |
| US20060012602A1 (en) * | 2004-07-15 | 2006-01-19 | George Lyons | System and method for efficiently performing automatic partial transfers of image data |
| JP4049136B2 (ja) * | 2004-08-10 | 2008-02-20 | ブラザー工業株式会社 | 画像処理装置及びプログラム |
| US7633505B1 (en) | 2004-11-17 | 2009-12-15 | Nvidia Corporation | Apparatus, system, and method for joint processing in graphics processing units |
| US7598958B1 (en) * | 2004-11-17 | 2009-10-06 | Nvidia Corporation | Multi-chip graphics processing unit apparatus, system, and method |
| US7502947B2 (en) * | 2004-12-03 | 2009-03-10 | Hewlett-Packard Development Company, L.P. | System and method of controlling a graphics controller |
| KR101110624B1 (ko) * | 2004-12-15 | 2012-02-16 | 삼성전자주식회사 | 그래픽 처리 기능을 갖는 메모리 컨트롤러 |
| US20060198175A1 (en) * | 2005-03-03 | 2006-09-07 | Badawi Ashraf H | Method, system, and apparatus high speed interconnect to improve data rates of memory subsystems |
| US20060282604A1 (en) * | 2005-05-27 | 2006-12-14 | Ati Technologies, Inc. | Methods and apparatus for processing graphics data using multiple processing circuits |
| US10026140B2 (en) | 2005-06-10 | 2018-07-17 | Nvidia Corporation | Using a scalable graphics system to enable a general-purpose multi-user computer system |
| US8893016B2 (en) * | 2005-06-10 | 2014-11-18 | Nvidia Corporation | Using a graphics system to enable a multi-user computer system |
| US20070067517A1 (en) * | 2005-09-22 | 2007-03-22 | Tzu-Jen Kuo | Integrated physics engine and related graphics processing system |
| US8266232B2 (en) | 2005-10-15 | 2012-09-11 | International Business Machines Corporation | Hardware processing of commands within virtual client computing environment |
| US7525548B2 (en) | 2005-11-04 | 2009-04-28 | Nvidia Corporation | Video processing with multiple graphical processing units |
| US8462164B2 (en) * | 2005-11-10 | 2013-06-11 | Intel Corporation | Apparatus and method for an interface architecture for flexible and extensible media processing |
| US7948497B2 (en) * | 2005-11-29 | 2011-05-24 | Via Technologies, Inc. | Chipset and related method of processing graphic signals |
| US8212832B2 (en) * | 2005-12-08 | 2012-07-03 | Ati Technologies Ulc | Method and apparatus with dynamic graphics surface memory allocation |
| US7477257B2 (en) * | 2005-12-15 | 2009-01-13 | Nvidia Corporation | Apparatus, system, and method for graphics memory hub |
| JP5111797B2 (ja) * | 2006-06-29 | 2013-01-09 | 株式会社東芝 | 情報処理装置及び情報処理方法 |
| US20080030510A1 (en) * | 2006-08-02 | 2008-02-07 | Xgi Technology Inc. | Multi-GPU rendering system |
| US20080259023A1 (en) * | 2007-04-19 | 2008-10-23 | Aten International Co., Ltd. | Method and System of Making a Computer as a Console for Managing Another Computer |
| US20080259556A1 (en) * | 2007-04-20 | 2008-10-23 | Tracy Mark S | Modular graphics expansion system |
| US8564598B2 (en) * | 2007-08-15 | 2013-10-22 | Nvidia Corporation | Parallelogram unified primitive description for rasterization |
| US8634695B2 (en) * | 2010-10-27 | 2014-01-21 | Microsoft Corporation | Shared surface hardware-sensitive composited video |
| US10217270B2 (en) | 2011-11-18 | 2019-02-26 | Intel Corporation | Scalable geometry processing within a checkerboard multi-GPU configuration |
| US9619855B2 (en) | 2011-11-18 | 2017-04-11 | Intel Corporation | Scalable geometry processing within a checkerboard multi-GPU configuration |
| CN103984669A (zh) | 2013-02-07 | 2014-08-13 | 辉达公司 | 一种用于图像处理的系统和方法 |
| CN104424661B (zh) * | 2013-08-23 | 2018-01-23 | 联想(北京)有限公司 | 三维对象显示方法和装置 |
| US9734546B2 (en) | 2013-10-03 | 2017-08-15 | Nvidia Corporation | Split driver to control multiple graphics processors in a computer system |
| US11069022B1 (en) * | 2019-12-27 | 2021-07-20 | Intel Corporation | Apparatus and method for multi-adapter encoding |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3350043B2 (ja) | 1990-07-27 | 2002-11-25 | 株式会社日立製作所 | 図形処理装置及び図形処理方法 |
| US5640578A (en) * | 1993-11-30 | 1997-06-17 | Texas Instruments Incorporated | Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section |
| DE69635066T2 (de) * | 1995-06-06 | 2006-07-20 | Hewlett-Packard Development Co., L.P., Houston | Unterbrechungsschema zum Aktualisieren eines Lokalspeichers |
| US6008823A (en) | 1995-08-01 | 1999-12-28 | Rhoden; Desi | Method and apparatus for enhancing access to a shared memory |
| US5919256A (en) * | 1996-03-26 | 1999-07-06 | Advanced Micro Devices, Inc. | Operand cache addressed by the instruction address for reducing latency of read instruction |
| TW335472B (en) * | 1996-06-20 | 1998-07-01 | Cirus Logic Inc | Method and apparatus for transferring pixel data stored in a memory circuit |
| JPH1074073A (ja) * | 1996-08-30 | 1998-03-17 | Nec Corp | 表示制御装置 |
| US5929872A (en) * | 1997-03-21 | 1999-07-27 | Alliance Semiconductor Corporation | Method and apparatus for multiple compositing of source data in a graphics display processor |
| US5995121A (en) | 1997-10-16 | 1999-11-30 | Hewlett-Packard Company | Multiple graphics pipeline integration with a windowing system through the use of a high speed interconnect to the frame buffer |
| US5943064A (en) * | 1997-11-15 | 1999-08-24 | Trident Microsystems, Inc. | Apparatus for processing multiple types of graphics data for display |
| US6091432A (en) * | 1998-03-31 | 2000-07-18 | Hewlett-Packard Company | Method and apparatus for improved block transfers in computer graphics frame buffers |
-
2000
- 2000-09-28 US US09/671,237 patent/US6630936B1/en not_active Expired - Fee Related
-
2001
- 2001-09-20 EP EP01977141A patent/EP1325470A2/en not_active Withdrawn
- 2001-09-20 GB GB0306045A patent/GB2384151B/en not_active Expired - Fee Related
- 2001-09-20 AU AU2001296282A patent/AU2001296282A1/en not_active Abandoned
- 2001-09-20 WO PCT/US2001/029605 patent/WO2002027658A2/en not_active Ceased
- 2001-09-20 DE DE10196696T patent/DE10196696T1/de not_active Withdrawn
- 2001-09-20 KR KR10-2003-7004217A patent/KR100528955B1/ko not_active Expired - Fee Related
- 2001-09-20 JP JP2002531362A patent/JP3996054B2/ja not_active Expired - Fee Related
- 2001-09-20 CN CNB018164730A patent/CN100395734C/zh not_active Expired - Fee Related
- 2001-09-28 TW TW090124151A patent/TW541507B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| CN100395734C (zh) | 2008-06-18 |
| GB2384151A (en) | 2003-07-16 |
| TW541507B (en) | 2003-07-11 |
| KR100528955B1 (ko) | 2005-11-15 |
| GB0306045D0 (en) | 2003-04-23 |
| AU2001296282A1 (en) | 2002-04-08 |
| EP1325470A2 (en) | 2003-07-09 |
| KR20030036822A (ko) | 2003-05-09 |
| US6630936B1 (en) | 2003-10-07 |
| CN1571991A (zh) | 2005-01-26 |
| DE10196696T1 (de) | 2003-08-28 |
| WO2002027658A2 (en) | 2002-04-04 |
| GB2384151B (en) | 2004-04-28 |
| WO2002027658A3 (en) | 2002-07-18 |
| HK1053895A1 (en) | 2003-11-07 |
| JP2004510269A (ja) | 2004-04-02 |
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