TW533519B - Semiconductor device and method for producing the same - Google Patents

Semiconductor device and method for producing the same Download PDF

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Publication number
TW533519B
TW533519B TW089103776A TW89103776A TW533519B TW 533519 B TW533519 B TW 533519B TW 089103776 A TW089103776 A TW 089103776A TW 89103776 A TW89103776 A TW 89103776A TW 533519 B TW533519 B TW 533519B
Authority
TW
Taiwan
Prior art keywords
conductive metal
layer
metal layer
electrode
coating layer
Prior art date
Application number
TW089103776A
Other languages
English (en)
Chinese (zh)
Inventor
Eiji Watanabe
Kouichi Murata
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW533519B publication Critical patent/TW533519B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
TW089103776A 1999-04-13 2000-03-03 Semiconductor device and method for producing the same TW533519B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11105586A JP2000299337A (ja) 1999-04-13 1999-04-13 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW533519B true TW533519B (en) 2003-05-21

Family

ID=14411614

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089103776A TW533519B (en) 1999-04-13 2000-03-03 Semiconductor device and method for producing the same

Country Status (4)

Country Link
US (1) US6614113B2 (cg-RX-API-DMAC7.html)
JP (1) JP2000299337A (cg-RX-API-DMAC7.html)
KR (1) KR100536036B1 (cg-RX-API-DMAC7.html)
TW (1) TW533519B (cg-RX-API-DMAC7.html)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3387083B2 (ja) 1999-08-27 2003-03-17 日本電気株式会社 半導体装置及びその製造方法
JP2003045875A (ja) * 2001-07-30 2003-02-14 Nec Kagobutsu Device Kk 半導体装置およびその製造方法
US6768210B2 (en) * 2001-11-01 2004-07-27 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
JP2003140347A (ja) * 2001-11-02 2003-05-14 Tokyo Ohka Kogyo Co Ltd 厚膜ホトレジスト層積層体、厚膜レジストパターンの製造方法、および接続端子の製造方法
DE10156054C2 (de) * 2001-11-15 2003-11-13 Infineon Technologies Ag Herstellungsverfahren für eine Leiterbahn auf einem Substrat
JP2003188313A (ja) * 2001-12-20 2003-07-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
US6995475B2 (en) * 2003-09-18 2006-02-07 International Business Machines Corporation I/C chip suitable for wire bonding
US20050167837A1 (en) * 2004-01-21 2005-08-04 International Business Machines Corporation Device with area array pads for test probing
US7910471B2 (en) * 2004-02-02 2011-03-22 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
JP3981089B2 (ja) 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
TWI278946B (en) * 2004-07-23 2007-04-11 Advanced Semiconductor Eng Structure and formation method for conductive bump
US20060087039A1 (en) * 2004-10-22 2006-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Ubm structure for improving reliability and performance
US7416980B2 (en) * 2005-03-11 2008-08-26 Intel Corporation Forming a barrier layer in interconnect joints and structures formed thereby
KR100762354B1 (ko) * 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
JP5101169B2 (ja) * 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
US8350385B2 (en) * 2007-07-30 2013-01-08 Nxp B.V. Reduced bottom roughness of stress buffering element of a semiconductor component
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
JP5350022B2 (ja) * 2009-03-04 2013-11-27 パナソニック株式会社 半導体装置、及び該半導体装置を備えた実装体
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
KR101187977B1 (ko) * 2009-12-08 2012-10-05 삼성전기주식회사 패키지 기판 및 그의 제조방법
US9159652B2 (en) * 2013-02-25 2015-10-13 Stmicroelectronics S.R.L. Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process
US9666550B2 (en) * 2014-12-16 2017-05-30 Tongfu Microelectronics Co., Ltd. Method and structure for wafer-level packaging

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63161649A (ja) * 1986-12-25 1988-07-05 Casio Comput Co Ltd 半導体装置の製造方法
DE3885834T2 (de) * 1987-09-24 1994-04-28 Toshiba Kawasaki Kk Lötstelle und Verfahren zu ihrer Bewerkstelligung.
JP3361881B2 (ja) 1994-04-28 2003-01-07 株式会社東芝 半導体装置とその製造方法
JP3238011B2 (ja) * 1994-07-27 2001-12-10 株式会社東芝 半導体装置
JPH10150249A (ja) * 1996-11-20 1998-06-02 Ibiden Co Ltd プリント配線板
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making

Also Published As

Publication number Publication date
JP2000299337A (ja) 2000-10-24
KR100536036B1 (ko) 2005-12-12
US6614113B2 (en) 2003-09-02
KR20000076789A (ko) 2000-12-26
US20020003302A1 (en) 2002-01-10

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees