TW526581B - Metal-insulator-metal capacitor formed on the damascene interconnect structure and forming method - Google Patents

Abstract

A kind of metal-insulator-metal (MIM) capacitor formed on the damascene interconnect structure and the forming method are disclosed in the present invention. At first, a trench is defined and etched on the dielectric layer of the substrate; and a barrier layer and a metal layer are sequentially formed in the trench to form a damascene-type interconnect structure. Then, on the damascene-type interconnect structure, the patterned first conduction layer, the insulation layer and the second conduction layer are sequentially formed to form an MIM capacitor, in which the capacitor length is not smaller than the trench width. Finally, the second conduction layer of the MIM capacitor is defined and etched again such that there is a predetermined distance between both sides of the second conduction layer of the MIM capacitor and the corresponding trench inner wall to prevent the decrease of electric characteristic due to the generation of leakage current when the MIM capacitor is used.

Description

526581 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor process, and in particular, to a metal-insulator-metal (M 丨 M) capacitor and method of forming the same on a mosaic interconnect structure. In order to prevent MI capacitors from generating leakage current and damage. Relevant technical description: In today's copper damascene process, copper atoms have the disadvantage of being easy to expand. Therefore, a metal barrier layer is usually formed between the copper interconnect and the electrical layer. (Barrier iayer) to prevent the diffusion of copper atoms. For example, titanium nitride (TiN), tantalum nitride (TaN), and titanium tungsten nitride (TiWN) are used. However, after a copper-chemical mechanical polishing (CMp) process to form interconnects, it is easy to generate a recess at the interface between the barrier layer and the copper interconnects. On the other hand, with the development of increasingly integrated semiconductor integrated circuit components, capacitors therein must be implemented using a three-dimensional space structure, such as metal-insulator-metal (M 丨 M) capacitors. When the M IM capacitor is manufactured on the interconnections in the mosaic interconnection structure, the capacitor will cause similar depressions in the compliance of the upper and lower electrodes and the insulation layer due to the above-mentioned notches, resulting in degradation of electrical characteristics. In order to further understand the above problems, please refer to FIGS. 1 a to 1 c to describe a method for forming a M capacitor on a mosaic interconnect structure in the following. First, as shown in FIG. 1a, a substrate is provided, for example, a silicon wafer with a transistor element formed thereon. Here, in order to simplify the drawing, only a flat substrate 10 is shown. Next, a substrate with a trench 丨 is formed on the substrate 10

0503-7186TWf; TSMC2001-0963; spin.ptd page 4 526581 V. Description of the invention (2) Electrical layer 12. Subsequently, a metal barrier layer 1 4 ′ such as tantalum nitride (τ a N) is sequentially formed on the inner wall of the trench 12 a sequentially, and a trench of the metal barrier layer 14 is formed on the dielectric layer 12. A copper metal layer 16 is formed in the groove 12a. Next, referring to FIG. 1b, the copper metal layer 16 is removed by a chemical mechanical polishing (CMp) method until the surface of the dielectric layer 12 is exposed to complete the fabrication of the mosaic interconnection 17. However, due to the grinding process,

A notch 1 6 a is formed on the surface of the interconnection 17 at the interface between the metal barrier layer 14 and the copper metal layer 16. V Next, referring to FIG. 1c, a patterned first conductive layer 18, an insulating layer 19, and a second conductive layer 20 are sequentially formed on the interconnects 7 to form a MIM capacitor 22 and the first A conductive layer 18 and a second conductive layer 20 are used as the lower electrode and the upper electrode of the MIM capacitor 22, respectively. However, due to the aforementioned notch 16a, the interface between the lower electrode 18, the insulating layer 19, and the upper electrode 20 of the MIM capacitor 22 is correspondingly depressed, as shown in the figure. In this way, in the actual application of the device, it is easy to generate a tip discharge in the recess and cause serious leakage current, which causes the device to damage or reduce the electrical characteristics. In view of this, the present invention provides a metal-insulator-metal (MIM) capacitor formed on a mosaic interconnect structure and a method for forming the same. Shorten the length of the upper electrode to avoid the problem of sag, and then prevent leakage current or damage from occurring. Summary of the Invention: The object of the present invention is to provide a method for forming a metal-insulator-metal lightning finish on a mosaic interconnect structure.

526581 V. Description of the invention (3) The length of the electrode to avoid leakage current or damage to the interface between the upper electrode and the insulation layer. According to the above object, the present invention provides a method for forming a metal ~ insulator-metal capacitor on a structure: defining a substrate on which a -dielectric layer is formed by etching, in order to: trench; sequentially and compliantly formed in a trench : Barrier layer, which is formed in order to form a mosaic inner-distance-conducting structure, with a fierce layer, an insulating layer and a second conductive insulating layer and a second conductive layer on the silver insert: a capacitor is formed above The length of the capacitor and the second conductive layer that defines the capacitor at the remaining time. There are one between the two conductive layers opposite the inner wall of the trench, and it also includes the step of defining the insulating layer of the Xu Zhaolei heart to etch the magic valley. Layer length disk Lei Ke 5 | $ Μ Anorexia, the second conductive layer of the rabbit combination is roughly 0.5 microns apart. Brief description of the drawings: In order to make the above-mentioned objectives of the present invention, features and advantages, preferred embodiments are described below, and in accordance with the attached drawings, the following:, 1 & to the diagram show the traditional mosaic This is a schematic cross-sectional view of an MIM capacitor. Figures 2a to 2e are schematic cross-sectional diagrams showing the formation of MIM capacitors on a wiring structure according to the present invention. [Symbol] Generate a recess to cause a meta-mosaic internal method, including the dielectric layer and the filled internal wiring. Layer; the fixed mosaic is not smaller than the trench so that the capacitor has a predetermined distance, so that the electricity is the same. The connection junction is formed in the following steps to form a metal structure. Furthermore, for the container, the above can be more obvious and easy to understand. For detailed descriptions, such as the inner wiring structure, the example is in the embedded type.

526581 Fifth invention description (4) 10, 30 ~ substrate; 12, 32 ~ dielectric layer 12a, 32a ~ trench 1 4, 3 4 ~ barrier layer 16, 36 ~ copper metal layer; 16a, 36a ~ notch 1 7, 3 7 ~ Interconnect 18, 38 ~ Lower electrode 1 9, 3 9 ~ Insulating layer 20, 40 ~ Upper electrode 22, 42 ~ MIM capacitor § |. Detailed description of the preferred embodiment: The following configuration. Figures 2d and 2e illustrate a metal-insulator-metal capacitor (mim) formed on a damascene type interconnector according to an embodiment of the present invention. First, referring to FIG. 2d, the reference numeral 30 indicates a substrate, such as a silicon circle. A dielectric layer 32 is provided on the substrate 30 and the dielectric layer 32 has at least one trench 32a. Reference numerals 37 and 7 indicate copper metal interconnects and are disposed in the trenches 32a. Among them, the copper metal interconnects 37 are compliant barrier layers 34, such as nitride buttons, and copper metal layers 36, which are disposed on the inner walls of the trenches 32a. Constructed as a mosaic interconnect structure. Reference numeral 38 indicates a lower electrode, which is provided on the mosaic interconnect structure 37 and is made of, for example, tantalum nitride. The length of the lower electrode 38 is not less than the width of the trench 32a. Reference numeral 39 denotes an insulating layer, which is disposed on the lower electrode 38, for example, made of one of silicon nitride, tantalum pentoxide (τ & 05) and stone oxide, and the length of the insulating layer 39 is substantially the same as that of the lower electrode 38. Length

〇503-7186TWf; TSMC2001-0963; spin.ptd page 7 526581

The same 4 indicates that the upper electrode 'is provided on the insulating layer 39, for example, made of a chemical button. In this way, the lower electrode 38 and the insulating layer 39 constitute a MIM capacitor 42. Among them, the width of the upper electrode 40 of ± Ray θ and the two sides of the upper electrode 40 are at a distance of two grooves 32a from the door of the inner wall of the groove 32a. In this embodiment, 'this predetermined distance is 0.05 micrometers; I: -yet Next, please refer to FIG. 2e, the structure of which is the same as that of FIG. 2d, and the same reference numerals are given, and the description is omitted here. In addition, the difference between the second and the second figure is that the former has the same insulation. The upper electrode 40 has the same length. τ and the cavity and the following figure 2a to 2e illustrate the above-mentioned formation of metal-insulator-metal (MIM) capacitor 5 | First, please refer to FIG. 2a, and provide a substrate 30, for example, a circle, on which a transistor element is formed. Here, in order to simplify the diagram, only the flat substrate 30 is formed on the substrate 30. There is a dielectric layer 32. Next, the dielectric layer 32 is etched to form a trench 32 & on the dielectric layer 32. Subsequently, a barrier layer 34 made of a nitride button is sequentially formed in compliance with the inner wall of the trench 32a, and a copper metal layer is formed on the dielectric layer 32 and in the trench 32 & where the barrier layer 34 is formed. 36. Next, referring to FIG. 2b, chemical mechanical polishing (CMp) = removing the excess copper metal layer 36 until the surface of the dielectric layer 32 is exposed to complete the fabrication of the post-mount interconnect structure 37. However, this grinding process will form a notch 36 on the surface of the interconnector 37 at the interface between the barrier layer 34 and the copper metal layer 36. Next, referring to FIG. 2c, the mosaic interconnector 37 structure is sequentially formed. First conductive layer 38, such as nitride button, insulating layer 39, such as nitride

526581 V. Description of the invention (6) ^ ---- Shi Xi: one of the two pentoxides and the oxidation second, and the second conductive layer 40, such as chaos =, the thickness of the three is about 300 angstroms ( a). Subsequently, the engraved first, electrical layer 38, insulating layer 39, and second conductive layer 40 are defined to form a capacitor 42 above the damascene interconnect structure 37, and the first-conducting layer 38 and the second conductive layer 40 are respectively As the upper electrode of the MIM capacitor 42. In this embodiment, the length of the electrode 38 below the capacitor 42 is not less than the width of the trench 32a, which is to prevent the subsequent etching process from damaging the interconnections 37. However, due to the aforementioned notch 36a, the interface between the lower electrode 38, the insulating layer 3/9, and the upper electrode 40 of the MIM capacitor 42 is correspondingly depressed, as shown in the figure. Finally, please refer to FIG. 2d, and define the etching of the electrode 40 above the IM capacitor 42 again, so that there is a predetermined distance between both sides of the electrode 40 above the IM capacitor 42 with respect to the inner wall of the trench 32a. The predetermined distance here is 0.5 micrometers, the purpose of which is to shorten the length of the upper electrode 40 to avoid the above-mentioned depression. In this way, there will be no depression at the interface between the upper electrode 40 and the insulating layer 39, that is, preventing the M? M capacitor 42 from damaging or generating a leakage current to reduce the electrical characteristics.

Lei-'ming refers to FIG. 2e '. Similarly, the etching MIM ^' edge layer 39 'can be defined again so that the length of the insulating layer 39 is substantially the same as that of the upper electrode. The interface between the lower electrode 38 and the insulating layer 39 also does not cause a concave situation to further solve the problem of leakage current. Although the present invention has been disclosed in the preferred embodiment as above, the bran directly restricts the present invention. Anyone skilled in the art can change and retouch within the scope of the god and range = away from the present invention. The appended application patent shall prevail. Mingzhibao Zunweiwei

Claims (1)

526581 VI. Scope of patent application1. A metal-insulator-metal capacitor formed on a mosaic interconnect structure, comprising: a substrate, a dielectric layer disposed on the substrate, and the dielectric layer being less than a trench &Quot; A metal interconnect is disposed in the trench to form a mosaic interconnect structure; "the lower electrode is disposed on the mosaic interconnect structure, wherein the length of the lower electrode is not less than The width of the trench; an insulating layer disposed on the lower electrode; and an upper electrode disposed on the insulating layer to form a capacitor, wherein the length of the upper electrode is less than the width of the trench and the upper electrode is two There is a predetermined distance between the side and the inner wall of the trench. 2 · The metal-insulator-metal capacitor formed on the inlaid interconnect structure as described in item 1 of the scope of the patent application, further included in the trench A barrier layer is provided on the inner wall for compliance. 3 · The metal-insulator-metal capacitor formed on the mosaic interconnect structure as described in item 1 of the patent application scope, wherein the metal The wire is a copper metal interconnect. 4 · The metal-insulator-metal capacitor formed on the mosaic interconnect structure as described in item 1 of the scope of patent application, wherein the upper electrode and the lower electrode are made of nitride Made of tantalum. 5 · The metal-insulator-metal capacitor formed on the mosaic interconnect structure described in item 1 of the scope of the patent application, where the insulating layer is selected from one of the following groups: nitrogen Silicon, pentoxide and silicon oxide. 0503-7186TWf; TSMC2001-0963; spin.ptd Page 10 526581 VI. Application for patent scope 6 · The metal-insulator-metal capacitor formed on the mosaic interconnect structure described in item 1 of the scope of patent application, The length of the insulating layer is substantially the same as the length of the lower electrode. 7. The metal-insulator-metal capacitor formed on the mosaic interconnect structure as described in item 1 of the scope of the patent application, wherein the length of the insulating layer is substantially the same as the length of the upper electrode. 8. The metal-insulator-metal capacitor formed on the mosaic interconnect structure as described in item 1 of the scope of the patent application, wherein the predetermined distance is 0.5 micrometers. 9. The metal-insulator-metal capacitor formed on the mosaic interconnect structure described in item 2 of the scope of the patent application, wherein the barrier layer is made of a nitride button. 1 0 · —A method of forming a metal-insulator on a mosaic interconnect structure—a metal capacitor, including the following steps: defining a substrate with a dielectric layer formed by etching to form a trench in the dielectric reed; 9 Form a barrier layer and fill one layer in compliance in the trench in order to form a mosaic interconnect structure; 'a first edge layer and a first layer are sequentially formed on the mosaic interconnect structure. Two conductive layers; a conductive layer and an isolated conductive layer, wherein the length of the capacitor is defined to etch the first conductive layer, the insulating layer, and the length of the capacitor to form a capacitor above the edge-inlay type interconnect structure The width of the trench; and Bijie's definition of etching the second conductive layer of the capacitor such that 526581 6. Scope of patent application There is a predetermined distance between two sides of the second conductive layer with respect to the inner ridge of the trench. 1 1 · The method for forming a metal-insulator-metal capacitor on a mosaic interconnect structure as described in item 10 of the scope of the patent application, further including the step of defining the insulating layer of the capacitor at a later time so that the capacitor The length of the insulating layer is substantially the same as that of the second conductive layer of the capacitor. 1 2 · The method for forming a metal-insulator-metal capacitor on a mosaic interconnect structure as described in item 10 of the scope of the patent application, wherein the barrier layer is made of nitrided nitride. 1 3. The method for forming a metal-insulator-metal capacitor on a mosaic interconnect structure as described in item No. 0 of the patent application scope, wherein the metal layer is a copper metal layer. 14 · The method for forming a metal-insulator-metal capacitor on a mosaic interconnect structure as described in item 10 of the scope of patent application, wherein the first and second conductive layers are made of tantalum nitride . 15 · As described in Item 10 of the scope of the patent application, a method for forming a metal-insulator-metal capacitor on a mosaic-type interconnection structure is described, wherein the insulation layer is selected from one of the following groups: gasification Silicon, two pentoxides and oxidized stones 〇16 6 · As described in item 10 of the scope of the patent application, a method of forming a metal-insulator-metal capacitor on a mosaic interconnect structure is described. 0 · 5 microns. 0503-7186TWf; TSMC2001-0963; spin.ptd page 12