JP4501208B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a memory element of an LSI memory and a manufacturing method thereof.
[0002]
[Prior art]
In the LSI memory, a memory cell includes a transfer transistor (hereinafter referred to as a transistor) and an information storage capacity (hereinafter referred to as a storage capacity).
[0003]
In recent years, international competition has intensified in this field, and it has become essential to supply large-capacity LSI memories to the market at a low price. For this reason, there is a need for a technique capable of manufacturing a highly integrated LSI memory at a lower price.
[0004]
In order to realize higher integration, the structure of the memory cell is complicated, the step between the memory cell region and the peripheral circuit region is enlarged, and the difficulty of the processing process is increased. In particular, the difficulty of the process of forming a contact between the memory cell and the peripheral circuit region is increased, which is an obstacle to manufacturing an LSI memory at a lower price.
[0005]
Therefore, the present inventor has proposed in Japanese Patent Application Laid-Open No. 10-189912 as a conventional semiconductor device excellent in consistency between the memory cell formation process and the contact formation process in the peripheral circuit region and a manufacturing method thereof.
[0006]
A conventional semiconductor device and its manufacturing method will be described below with reference to the drawings.
[0007]
FIG. 14 is a plan view and a cross-sectional view showing the structure of a conventional semiconductor device. In the figure, the left side is a memory cell region m, and the right side is a peripheral circuit region p. FIG. 14A is a plan view, and FIG. 14B is an xx ′ cross-sectional view in FIG.
[0008]
In the figure, 101 is a semiconductor substrate, 102 is an element isolation region, 103 is a gate insulating film, 104 is a gate electrode, 105 is a protective film, 106 is a gate sidewall insulating film, 107 is a source / drain diffusion layer, and 114a is a first conductive layer. A storage electrode made of a body film, 114b is a dummy pattern made of a first conductor film, 114c is a contact plug in a peripheral circuit region made of a first conductor film, 118 is a capacitor dielectric film, and 119 is a second conductor film. The formed counter electrode 127 is a wiring layer.
[0009]
In the figure, the dummy pattern 114b and the contact plug 114c in the peripheral circuit region are formed simultaneously with the storage electrode 114a made of the first conductor of the storage capacitor of the memory cell. Therefore, it is possible to reduce the number of processes and the difficulty of the process due to the step between the memory cell area and the peripheral circuit area.
[0010]
[Problems to be solved by the invention]
However, even in the above-described conventional technique, an electrode extraction opening process is required to form the wiring layer 127. This opening process requires processes such as the formation of a resist mask by a photo process for forming the opening, etching of the insulating film that forms the opening, and removal of the resist mask. Difficult to do.
[0011]
Therefore, there is a demand for a technique that is excellent in consistency when forming the memory cell region and the peripheral circuit region and can manufacture an LSI memory at a lower cost.
[0012]
An object of the present invention is to provide a contact formation process between a memory cell and a peripheral circuit region of an LSI memory as a semiconductor device having a simple configuration and process and a method for manufacturing the same.
[0013]
[Means for solving the problems]
The object is to provide, on a semiconductor substrate, a capacitance formed by a first electrode made of a first conductor, a dielectric film, and a second electrode made of a second conductor, and from the first conductor. And the second electrode extends from the capacitor to the third electrode, and the second electrode and the third electrode are on the third electrode. This is achieved by an electrically connected semiconductor device.
[0014]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, and forming a first electrode made of a first conductor in the memory cell region; Forming a third electrode made of the first conductor at a boundary position between the memory cell region and the peripheral circuit region; and a portion belonging to the memory cell region from the boundary to the third electrode. A step portion lower than a portion belonging to the peripheral circuit region is formed, and a dielectric film and a second electrode made of a second conductor are formed on the first electrode, and the dielectric film And the second electrode extending to the side wall of the step portion of the third electrode, the second electrode formed on the side wall portion, and a part of the dielectric film Forming a groove from which the second electrode is removed, filling a part of the groove with a third conductor, and To be achieved by the method of manufacturing a semiconductor device including the step of electrically connecting the third electrodes.
[0015]
That is, according to the present invention, the extraction of the counter electrode is completed without steps such as formation of a resist mask by a photo process, etching of an insulating film, and removal of the resist mask, and the counter electrode is formed by a relatively easy process. A semiconductor device and a method for manufacturing the semiconductor device can be provided by a simpler configuration and process of forming a memory cell of an LSI memory and a contact forming process of a peripheral circuit region.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
[0017]
1A and 1B are a plan view and a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. The left side is a memory cell region M and the right side is a peripheral circuit region P. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. 2 to 4 are process cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment.
[0018]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.
[0019]
The semiconductor substrate 1 is defined by an element isolation region 2, and a transistor including a gate insulating film 3, a gate electrode 4, a protective film 5, a gate sidewall insulating film 6, and a source / drain diffusion layer 7 exists at a predetermined position. In the memory cell region M, a storage electrode (hereinafter referred to as storage electrode) 14a, which is the first electrode of the storage capacitor, is located at a position across the boundary between the memory cell region M and the peripheral circuit region P by the same conductor. A contact electrode (hereinafter referred to as a contact electrode) 14b, which is a third electrode, and a contact plug 14c are present in the peripheral circuit region P.
[0020]
A capacitor dielectric film 18 and a counter electrode (hereinafter referred to as a counter electrode) 19 as a second electrode are constituent parts of the storage capacitor of the memory cell region M, and the side walls of the stepped part of the contact electrode part 14b across the boundary Also extends to the department.
[0021]
In the side wall portion, there is a first groove 21 formed by etching the capacitor dielectric film 18 and the counter electrode 19 from the surface. At the bottom of the first groove, the capacitor dielectric film 18 is etched deeper than the counter electrode 19 to form a second groove 22. The second groove 22 is filled by volume expansion when oxide or nitride is generated by oxidizing or nitriding either or both of the side wall portion of the contact electrode 14b and the counter electrode 19.
[0022]
For the contact electrode 14b and the counter electrode 19, a material having conductivity, such as W (tungsten) nitride, is selected. In the case of W, the second groove 22 is filled with a conductive WNx (tungsten nitride) film 23 and both are electrically connected. An insulating film 26 exists in the first trench 21, and the contact electrode 14 b and the contact plug 14 c in the peripheral circuit region are exposed by planarizing the surface.
[0023]
These are opened by etch back or CMP (Chemical Mechanical Polishing) without connecting to the wiring layer 27 without requiring a photo process.
[0024]
In the plan view of FIG. 1A, an example in which the storage electrode 14a in the memory cell region M is arranged as a memory cell is shown. The boundary between the memory cell region M and the peripheral circuit region P is indicated by the pattern of the insulating film 26. The intersection of the pattern of the contact electrode 14b and the insulating film 26 indicates the positional characteristics of the electrode 14b.
[0025]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0026]
2A, after forming an element isolation region 2 on a semiconductor substrate 1 by, for example, STI (Shallow Trench Isolation), a gate insulating film 3, a gate electrode 4, a protective film 5, a gate sidewall insulating film 6, and a source A transistor is formed by the drain diffusion layer 7. Note that the gate electrode 4 also serves as a word line. On the source / drain diffusion layer 7 in the memory cell region M, a plug 7a made of doped polysilicon is formed.
[0027]
On one source / drain diffusion layer 7, a bit line 8 intersecting with a word line is formed via a plug 7 a, and on the peripheral circuit region P, an extraction electrode 8 c is formed.
[0028]
Next, an insulating film 9 is formed on the entire surface, and the surface of the insulating film 9 is planarized by a CMP method. Thereafter, an opening connected to the plug 7a and the extraction electrode 8c in the peripheral circuit region P is formed in the insulating film 9, and the opening is filled with a conductor film 10 such as W / TiN / Ti.
[0029]
Next, for example, a silicon nitride film 11 with a film thickness of 50 nm, a silicon oxide film 12 with a film thickness of 0.3 to 0.6 μm, and an amorphous silicon film with a film thickness of 50 nm as an etching mask are sequentially formed by CVD. Film. Thereafter, the amorphous silicon film is patterned by a photo process, and openings to be storage electrodes, contact electrodes, and peripheral circuit contact plugs are formed in the future using the amorphous silicon film 13 as an etching mask.
[0030]
Referring to FIG. 2B, a W film 14 of, eg, a 100 nm-thickness that becomes the first conductor is formed by CVD. The W film 14 is formed so as to fill the opening formed by the silicon oxide film 12 and the amorphous silicon film 13, and its surface becomes relatively flat.
[0031]
Referring to FIG. 2C, the W film 14 is etched back by dry etching with SF6 (sulfur hexafluoride) gas plasma until the amorphous silicon film 13 is exposed.
[0032]
Next, the amorphous silicon film 13 is etched, so that the W film 14 is formed as an isolated pattern of the portion to be the storage electrode and the contact electrode and the peripheral circuit region contact plug 14c. Instead of etching the W film 14 and the amorphous silicon film 13, a CMP method may be used.
[0033]
Referring to FIG. 3A, a silicon nitride film 16 of, eg, a 20 nm-thickness that serves as an etching protective film is formed by CVD. Next, the peripheral circuit region is covered with a resist mask 17 formed by a photo process, the silicon nitride film 16 is etched, and the W film is etched to about 100 to 300 nm by dry etching of SF6 plasma to obtain a desired accumulation. Make the height necessary to obtain the capacity. Here, the storage electrode 14a and the contact electrode 14b are formed.
[0034]
In the contact electrode 14b at a position intersecting the boundary, a step is generated because only a portion existing on the memory cell region M side is etched. By this step, a side wall is formed along the boundary crossing the contact electrode 14b.
[0035]
Next, using the silicon nitride film 16, the storage electrode 14a, and the contact electrode 14b as a mask, the silicon oxide film 12 in the memory cell region is dry-etched with fluorine plasma and optionally wet-etched with HF (hydrofluoric acid) solution. Etching up to the silicon nitride film 11.
[0036]
Although the conductor film 10 exists below the contact electrode 14b, the conductor film 10 does not need to function as a conductor and is not necessarily essential. However, when the conductor film 10 does not exist below the contact electrode 14b, the base of the contact electrode 14b becomes an insulating film, and the adhesion strength with the base is lower than when the base is a conductor film. There is a risk that the contact electrode 14b will peel off, and this peeling can be prevented.
[0037]
Referring to FIG. 3B, a Ta2 O5 film 18 having a film thickness of 10 nm, for example, which becomes a capacitor dielectric film, a W film 19 having a film thickness of 50 to 200 nm, for example, which serves as a counter electrode, and a film thickness by CVD. A silicon oxide film 20 having a thickness of 500 nm is sequentially formed.
[0038]
Next, the silicon oxide film 20 on the peripheral circuit region P is removed by, for example, the CMP method, and the W film 19 and the Ta2 O5 film 18 are removed by the etch back or the CMP method, and flattened to the surface of the silicon nitride film 16. . It should be noted that the etch back can be performed simultaneously with the removal of the W film 19 and the Ta2 O5 film 18 in the following steps shown in FIGS. 3C and 4A.
[0039]
In the contact electrode 14b under the boundary, the capacitor dielectric film 18 and the counter electrode 19 are formed and terminated on the surface so that the side wall portion of the step rises from the memory cell region M to the peripheral circuit region P.
[0040]
At this stage, the dielectric film 18 is interposed between the contact electrode 14b and the counter electrode 19, so that they are not electrically connected.
[0041]
Referring to FIG. 3C, the counter electrode 19 formed on the side wall portion of the boundary and the inner side wall portion of the contact electrode portion is removed by dry etching, and the first groove 21 is being formed. Become. The contact electrode 14b is made of W as in the counter electrode 19, but is not etched because it is covered with the silicon nitride film 16.
[0042]
Referring to FIG. 4A, the Ta2 O5 film 18 formed on the side wall of the contact electrode 14b is etched to the same depth as the counter electrode 19 to form the first groove 21. The Ta2 O5 film 18 has a thickness of 10 nm, for example, and the etching is performed by isotropic etching by dry etching of fluorine plasma similar to the etching conditions of the silicon oxide film. At this time, the silicon oxide film 20 is also etched, but the thickness of the etched film is less than the thickness of 100 to 300 nm and has no effect.
[0043]
Further, the Ta2 O5 film 18 is etched to further form a second groove 22 in a part of the bottom of the first groove 21. This groove is formed between the contact electrode 14b and the counter electrode 19, and its width corresponds to the film thickness of the Ta2 O5 film 18 and is, for example, 10 nm. Etching of the Ta2 O5 film 18 in this step is 10 to 20 nm, and there is no influence on the silicon oxide film 20 as described above.
[0044]
Referring to FIG. 4B, for example, thermal nitridation is performed in an NH3 atmosphere at 400 DEG C. for 5 to 10 minutes. The contact electrode 14b and the counter electrode 18 are both W, and the nitride WNx has conductivity. In the second groove 22, a WNx film 23 is formed and filled by volume expansion at that time. At the same time, the contact electrode 14b and the counter electrode 18 can be electrically connected. Since the width of the second groove is, for example, 10 nm, this step is completed by the thermal nitridation for the above time.
[0045]
Next, a silicon oxide film 26 is formed on the entire surface by CVD to fill the first groove 21. Thereafter, the silicon oxide film 26 and the silicon nitride film 16 other than filling the first trench 21 are removed by an etch back method or a CMP method.
[0046]
As a result, the process of opening the wiring for the counter electrode and opening to the peripheral circuit region includes the steps of forming a resist mask by a photo process for forming the opening, etching the insulating film forming the opening, and removing the resist. Complete without passing.
[0047]
With reference to FIG. 4C, necessary wiring layers 27 such as lead lines, main word lines, and peripheral circuits of the counter electrode are formed.
[0048]
In this embodiment, W is used as the material for the storage electrode 14a and the counter electrode 19, but other materials can be selected.
[0049]
For example, Ru (ruthenium) is selected as the storage electrode 14a and the contact electrode 14b, the second groove is filled by volume expansion due to oxidation, and the Ru oxide RuOx (ruthenium oxide) is a conductor. Can be connected. In this case, instead of the thermal nitridation step of FIG. 4B, thermal oxidation is performed at 450 ° C. in an O 2 atmosphere, for example, and the second groove 22 is filled by volume expansion due to oxidation. Etching is dry etching using O2 plasma.
[0050]
Further, Ru, WN, TiN, TiON or the like can be selected as the material of the counter electrode 19.
[0051]
Further, although Ta2 O5 is used as the dielectric film 18, other materials such as BST (BaStTaO3) and ST (StTaO3) can be selected.
[0052]
[Second Embodiment]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0053]
5A and 5B are a plan view and a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention, in which the left side is the memory cell region M and the right side is the peripheral circuit region P. FIG. 5A is a plan view, and FIG. 5B is a YY ′ cross-sectional view in FIG. 6 to 9 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.
[0054]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. The present embodiment is applied to a cylindrical capacitor structure that obtains a higher storage capacity by utilizing both side walls on the inside and outside of the storage electrode as electrodes in order to make the memory cell smaller.
[0055]
In the plan view of FIG. 5A, an example in which the storage electrode 34a in the memory cell region M is arranged as a memory cell is shown. The boundary between the memory cell region M and the peripheral circuit region P is indicated by the pattern of the silicon oxide film 26. The intersection of the pattern of the contact electrode 34b and the silicon oxide film 26 indicates the positional characteristics of the electrode 34b. In the plan view, the contact electrode 34b has a structure having both side walls on the inside and outside, similar to the storage electrode 34a. At the intersection between the contact electrode 34b and the silicon oxide film 26, the silicon oxide film 26 exists along the inner side wall of the contact electrode 34b.
[0056]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0057]
In FIG. 6A, an opening portion of the insulating film 12 to be a storage electrode, a contact electrode, and a contact plug of a peripheral circuit is formed in the same process as in FIG. 2A for explaining the first embodiment. Therefore, the description is omitted.
[0058]
With reference to FIG. 6B, a Ru film 34 of, eg, a 30 nm-thickness serving as the first conductor is formed by CVD. Unlike the process shown in FIG. 2B of the first embodiment, the opening of the insulating film 12 is not filled with the Ru film 34 in this embodiment.
[0059]
Next, a silicon oxide film 15 of, eg, a 200 nm-thickness serving as an inner surface protection film is formed by application by an SOG (coated glass) method, and the Ru film 34 is embedded. Next, the silicon oxide film 15 is etched so that the uppermost surface of the Ru film 34 is exposed to the surface and the bottom of the concave region of the Ru film 34 is protected.
[0060]
Referring to FIG. 6C, the protruding portion of the Ru film 34 and the amorphous silicon film 13 protruding by the depression of the silicon oxide film 15 are etched back by dry etching with O2 gas and CF4 gas to contact the storage electrode. A portion to be an electrode and a peripheral circuit contact plug 34c are each formed as an isolated pattern.
[0061]
Referring to FIG. 7A, a silicon nitride film 16 of, eg, a 50 nm-thickness is formed as an etching protection film by CVD. Next, the peripheral circuit region P is protected by a resist mask 17 formed by a photo process, and the Ru film 34 is etched by about 100 nm to 300 nm by plasma dry etching with O2 gas to a height determined by a desired storage capacity. Here, the storage electrode 34a and the contact electrode 34b are formed.
[0062]
In the contact electrode 34b at the position intersecting the boundary, only a portion existing on the memory cell region side is etched, so that a step is generated.
[0063]
Referring to FIG. 7B, the silicon oxide films 12 and 15 are removed by fluorine plasma dry etching and HF solution wet etching. In this step, the silicon oxide film 15 under the resist mask 17 is removed until the inner side wall of the contact electrode 34b is exposed. The insulating film 9 is protected by the silicon nitride film 11. Therefore, after the etching is completed, the resist mask 17 and the silicon nitride film 16 have a bowl shape.
[0064]
Next, the resist mask 17 is peeled off.
[0065]
The conductive film 10 is present below the contact electrode 34c. The reason for the existence is the same as that described with reference to FIG. 3A in the first embodiment.
[0066]
Referring to FIG. 7C, by CVD, for example, a Ta2 O5 film 18 with a film thickness of 10 nm, which becomes a capacitor dielectric film, and a Ru film 19 with a film thickness of 50 nm, for example, which becomes a counter electrode, for example, a film thickness of 500 nm The silicon oxide films 20 are sequentially formed.
[0067]
Next, the silicon oxide film 20 on the peripheral circuit region is removed by, for example, the CMP method, and then the Ru film 19 and the Ta2 O5 film 18 on the same region are removed by the etch back or the CMP method. Flatten to the surface. In the case of the etch back, it can be performed simultaneously with the removal of the Ru film 19 and the Ta2 O5 film 18 in the following steps of FIGS. 8A and 8B.
[0068]
In the contact electrode 34b below the boundary, a Ta2 O5 film 18 and a Ru film 19 as a counter electrode are formed on the inner side wall portion of the electrode so as to rise from the memory cell region M to the peripheral circuit region P. On the surface, the silicon nitride film 16 is formed in a bowl shape and terminates. At this stage, since the Ta2 O5 film 18 is interposed between the contact electrode 34a and the Ru film 19 of the counter electrode, the two are not electrically connected.
[0069]
Referring to FIG. 8A, the counter electrode 19 formed on the side wall portion of the inner surface of the contact electrode portion is removed by dry etching of O2 gas plasma, so that the first groove 21 is in the process of being formed. . Contact electrode 34 b is protected by silicon nitride film 16.
[0070]
Referring to FIG. 8B, the Ta2 O5 film 18 formed on the side wall of the inner surface of the contact electrode 34b is etched to the same depth as the counter electrode 19 to form the first groove 21. The Ta2 O5 film 18 has a film thickness of 10 nm, for example, and the etching conditions are the same as the etching conditions for the silicon oxide film by dry etching of fluorine plasma. At this time, the silicon oxide film 20 is also etched, but the etched film thickness is small as compared with the film thickness of 100 to 300 nm, and there is no influence.
[0071]
Further, the Ta2 O5 film 18 is etched to further form a second groove 22 in a part of the bottom of the first groove 21. This groove is formed between the contact electrode 34b and the counter electrode 19, and its width corresponds to the film thickness of the Ta2 O5 film 18 and is 10 nm. Etching of the Ta2 O5 film in this step is 10 to 20 nm, and there is no influence on the silicon oxide film 20 as described above.
[0072]
Referring to FIG. 8C, for example, thermal oxidation is performed at 450 ° C. for several minutes in an oxygen atmosphere. Both the contact electrode 34b and the counter electrode 19 are Ru, and the oxide thereof has conductivity. In the second groove 22, a RuOx film 24 is formed and filled by volume expansion at that time. At the same time, the contact electrode 34b and the counter electrode 19 can be electrically connected. Since the width of the second groove is, for example, 10 nm, this step is completed by the thermal nitridation for the above time.
[0073]
Referring to FIG. 9A, a silicon oxide film 26 is formed on the entire surface to fill the first groove 21. Next, the silicon oxide film 26 other than filling the first trench 21 and the silicon nitride film 16 are removed by an etching method or a CMP method.
[0074]
As a result, the opening process for taking out the wiring of the peripheral circuit and the counter electrode is completed without passing through processes such as formation of a resist mask by a photo process for forming the opening, etching of the insulating film forming the opening, and resist removal. .
[0075]
With reference to FIG. 9B, necessary wiring layers 27 such as lead lines, main word lines, and peripheral circuits of the counter electrode are formed.
[0076]
In the present embodiment, both the storage electrode 34a and the counter electrode 19 are made of Ru, but other materials can be selected. For example, as in the first embodiment, W can be selected as the storage electrode, and the second groove can be filled by volume expansion due to nitriding to be electrically connected. In this case, the thermal nitriding and etching steps are the same as in the first embodiment.
[0077]
The selection of the material for the dielectric film 18 is the same as in the first embodiment.
[0078]
In addition to Ru, W, WN, TiN, TiON, etc. can be selected as the material for the counter electrode.
[0079]
In FIG. 10, further expansion of a part of this embodiment will be described.
[0080]
10A and 10B are cross-sectional views focusing on the yy ′ cross-section in FIG. 5A, and FIG. 10A shows the resist mask 17 in the step of FIG. The cross section which paid attention only to the part which a pattern and the contact electrode 34b cross | intersect is shown. The structure of this part is the same as the structure of the contact electrode 14b in the first embodiment shown in FIG.
[0081]
That is, the electrical connection between the contact electrode 34 b and the counter electrode 19 is performed on the side wall of the step portion of the contact electrode 34 b on the end face of the resist mask 17.
[0082]
FIG. 10B shows a connection portion of the cross section of the contact electrode 34b in the step of forming the wiring layer 27 shown in FIG. 9B.
[0083]
Accordingly, the contact electrode 34b and the counter electrode 19 are electrically connected only by the connection portion. In this case, in the process of FIG. 7B, when etching the silicon oxide film 15, only the inner surface portion of the storage electrode 34a not covered with the resist mask 17 may be removed. It is not necessary to expose the inner wall of the contact electrode 34b.
[0084]
In the step of FIG. 6B, a conductor can be selected in place of the silicon oxide film 15 serving as the inner surface protective film. For example, a 200 nm-thick W film can be formed on the entire surface by CVD. This case is shown in FIGS. 10C and 10D.
[0085]
In FIG. 10C, not the etching of the silicon oxide film 15 in the step of FIG. 7B but plasma etching of W using SF6 gas is performed. A portion covered with the resist mask 17 remains in W15a inside the contact electrode 34b, and a step is formed in the electrode. The contact electrode 34b and the counter electrode 19 are electrically connected on the side wall of the same step.
[0086]
FIG. 10D shows a process in which the wiring layer 27 is formed. When the inner surface protective film is the conductor 15a such as W, the inner surface of the contact plug 34c in the peripheral circuit region is filled with the conductor, so that contact characteristics with lower resistance can be realized.
[0087]
As described above, in the present embodiment, as the portion where the contact electrode 34b and the counter electrode 19 are electrically connected, the side wall of the inner surface of the contact electrode 34b, the side wall of the stepped portion of the contact electrode 34b, and the inner surface protective film 15 of the contact electrode 34b. In the case of a conductor, there is a stepped side wall of the inner surface protective film in the electrode. Any of these electrical connections can be used alone or in combination of two or more.
[0088]
[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS.
[0089]
The present embodiment is an example of the same memory cell shape as that of the second embodiment, and FIG. 11 is a diagram showing a process unique to the present embodiment. The process of this embodiment is the same as that of FIG. 6 described in the second embodiment, but the silicon nitride film 16 is omitted as compared with the process shown in FIG. 7A of the second embodiment. .
[0090]
FIG. 11A shows a process of protecting the peripheral region with only the resist mask 17 by omitting the silicon nitride film.
[0091]
Referring to FIG. 11B, a Ta2 O5 film 18, a counter electrode 19, and a silicon oxide film 20 are formed and planarized as in the second embodiment. The wrinkle shape seen in FIG. 7A of the second embodiment is not seen in this embodiment.
[0092]
In the present embodiment, after the step shown in FIG. 11B, the counter electrode 19 is etched to form a groove (not shown) as in the second embodiment (not shown). However, the material for the storage electrode 34a, the counter electrode 19 and the like Depending on the combination of selection, the silicon nitride film as the etching protective film can be omitted.
[0093]
For example, W is selected as the storage electrode 34a and TiN is selected as the counter electrode 19, only the counter electrode 19 is etched by wet etching of hydrogen peroxide + sulfuric acid, and the Ta2 O5 film 18 is further etched to form the groove 21. To do.
[0094]
In the present embodiment, the step of filling the groove with a conductor determines conditions suitable for the selected material. In the case of the above material example, thermal nitriding is performed.
[0095]
[Fourth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fourth embodiment of the present invention will be described with reference to FIGS.
[0096]
The present embodiment is an example of the same memory cell shape as that of the second embodiment, and FIG. 12 is a diagram showing processes peculiar to the present embodiment. In the process of this embodiment, the first groove 21 and the second groove 22 are formed through the same processes as those shown in FIGS. 6 to 8B in the second embodiment. The following steps unique to this embodiment are shown in FIG.
[0097]
Referring to FIG. 12A, a TiN film 25 of, eg, a 10 nm-thickness is formed on the entire surface by CVD. Since this TiN film 25 is formed by the CVD method, it has good step coverage, and is formed on the inner sidewalls of the first groove 21 and the second groove 22. The conductor film 25 is formed so as to fill the second groove 22.
[0098]
Referring to FIG. 12B, the TiN film 25 is removed leaving the second groove 22 by dry etching using plasma of chlorine-based gas, and the contact electrode 34b and the counter electrode 19 are electrically connected. The
[0099]
Referring to FIG. 12C, a silicon oxide film 26 filling the first groove 21 is formed. Next, planarization for removing the silicon oxide film 26 is performed, whereby the peripheral circuit region and the opening process for extracting the wiring of the counter electrode are completed.
[0100]
Referring to FIG. 13, in the present embodiment, a process in which the second groove 22 shown in FIG. 12 is not formed can be selected. In the same figure, the process peculiar to the process is shown. That is, the TiN film 25 is grown after the first groove 21 is formed, and the excess portion is etched leaving the TiN film 25 filled at the bottom of the first groove 21. The contact electrode 34b and the counter electrode 19 are electrically connected by the TiN film 25. Next, a silicon oxide film 26 filling the upper part of the first groove 21 is formed.
[0101]
According to the present embodiment, regarding the selection of materials for the storage electrode 34a and the counter electrode 19, the degree of freedom of selecting a material that cannot use the volume expansion effect due to oxidation of the conductor film or the like when establishing electrical connection with each other is increased. Can do.
[0102]
Moreover, this embodiment can be applied also to the process in previous 3rd Embodiment. That is, the process of this embodiment can be performed after the process similar to that shown in FIGS. The electrode structure of the present embodiment is a cylindrical type similar to that of the second embodiment, but can also be implemented in the case of a column type.
[0103]
According to the first to fourth embodiments described above, the opening for extracting each wiring of the peripheral circuit and the counter electrode is formed by forming a resist mask by a photo process for forming the opening and etching the insulating film for forming the opening. It can be completed without going through steps such as resist removal.
[0104]
【The invention's effect】
As described above, according to the present invention, since the counter electrode and the peripheral circuit region are formed by a relatively easy process, the contact formation process between the memory cell and the peripheral circuit region of the LSI memory is simplified. It can be provided as a semiconductor device having a configuration and process and a manufacturing method thereof, and can contribute to a reduction in manufacturing cost of an LSI memory.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the invention.
FIG. 2 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 5A and 5B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the invention. FIGS.
FIG. 6 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 7 is a process cross-sectional view (No. 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 8 is a process cross-sectional view (No. 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 9 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 10 is a process sectional view (No. 5) showing the method for producing the semiconductor device according to the second embodiment of the invention;
FIG. 11 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention.
FIG. 12 is a sectional view (No. 1) showing the structure of the semiconductor device according to the fourth embodiment of the present invention;
FIG. 13 is a sectional view (No. 2) showing the structure of the semiconductor device according to the fourth embodiment of the present invention;
14A and 14B are a plan view and a cross-sectional view showing a structure of a conventional semiconductor device.
[Explanation of symbols]
1 Semiconductor substrate
2 Device isolation region
3 Gate insulation film
4 Gate electrode
5 Gate protection film
6 Gate sidewall insulating film
7 Source / drain diffusion layers
7a Plug with doped polysilicon
8-bit line
8c Drawer electrode for peripheral circuit
9 Insulating film
10 Conductor film
11 Silicon nitride film
12 Silicon oxide film
13 Amorphous silicon film
14, 34 first conductor
14a, 34a Storage electrode
14b, 34b Contact electrode
14c, 34c Contact plug in peripheral circuit area
15 Insulating film for inner surface protection film
15a Conductor serving as an inner surface protection film
16 Silicon nitride film
17 resist mask
18 Capacitor dielectric film
19 Counter electrode
20 Silicon oxide film
21 First groove
22 Second groove
23 WNx membrane
24 RuOx membrane
25 TiN film
26 Silicon oxide film
27 Wiring layer

Claims (3)

In a method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
Forming a first electrode made of a first conductor in the memory cell region;
Forming a third electrode made of the first conductor at a boundary position between the memory cell region and the peripheral circuit region;
The third electrode is formed with a step portion where a portion belonging to the memory cell region is lower than a portion belonging to the peripheral circuit region from the boundary, and the dielectric film and the second electrode are formed on the first electrode. Forming a second electrode made of a conductor, and forming the dielectric film and the second electrode so as to extend on a side wall of the step portion of the third electrode;
Forming a groove formed by removing a part of the second electrode and the dielectric film formed on the side wall;
A method of manufacturing a semiconductor device, comprising: filling a part of the groove with a third conductor and electrically connecting the second electrode and the third electrode. When forming the first electrode and the third electrode, a fourth electrode formed of the first conductor, to claim 1, characterized in that it comprises a step of forming the peripheral circuit region The manufacturing method of the semiconductor device of description. The step of filling a part of the groove with the third conductor includes:
And oxidizing or nitriding the first electrode or the second electrode, and filling a part of the groove with the second conductor with a conductive oxide or nitride. A method of manufacturing a semiconductor device according to claim 1 or 2 .

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