KR20070013572A - Method of forming semiconductor device with capacitor and metal interconnection in damascene process - Google Patents

Method of forming semiconductor device with capacitor and metal interconnection in damascene process Download PDF

Info

Publication number
KR20070013572A
KR20070013572A KR1020050067979A KR20050067979A KR20070013572A KR 20070013572 A KR20070013572 A KR 20070013572A KR 1020050067979 A KR1020050067979 A KR 1020050067979A KR 20050067979 A KR20050067979 A KR 20050067979A KR 20070013572 A KR20070013572 A KR 20070013572A
Authority
KR
South Korea
Prior art keywords
semiconductor device
dual damascene
pattern
capacitor
film
Prior art date
Application number
KR1020050067979A
Other languages
Korean (ko)
Other versions
KR101153224B1 (en
Inventor
조일현
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020050067979A priority Critical patent/KR101153224B1/en
Publication of KR20070013572A publication Critical patent/KR20070013572A/en
Application granted granted Critical
Publication of KR101153224B1 publication Critical patent/KR101153224B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A semiconductor device having a capacitor and a metal line is provided to reduce a loss of a lower electrode during etching an upper electrode by applying a damascene process. A semiconductor device includes an insulation film pattern(21), a dual damascene pattern, a capacitor(100), and a second metal line(31). A first metal line is formed on the insulation film pattern. The dual damascene pattern is formed on the insulation film pattern. The capacitor is arranged on an inner surface of the dual damascene pattern. The second metal line buries an inner portion of the dual damascene pattern. The first and second metal lines are selected from the group consisting of aluminum, gold, silver, tungsten, a doped polysilicon film, and copper. The capacitor includes upper and lower electrodes, whose thicknesses lie between 100 and 500 Š.

Description

다마신 공정에 의해 형성된 캐패시터와 금속 배선을 갖는 반도체 소자{METHOD OF FORMING SEMICONDUCTOR DEVICE WITH CAPACITOR AND METAL INTERCONNECTION IN DAMASCENE PROCESS}A semiconductor device having a capacitor and a metal wiring formed by a damascene process {METHOD OF FORMING SEMICONDUCTOR DEVICE WITH CAPACITOR AND METAL INTERCONNECTION IN DAMASCENE PROCESS}

도 1은 종래 기술의 문제점을 보여주는 TEM 사진,1 is a TEM photograph showing the problem of the prior art,

도 2a 내지 도 2c는 본 발명의 일실시예에 다마신 공정에 의해 형성된 캐패시터와 금속 배선을 갖는 반도체 소자 제조 방법을 나타낸 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a capacitor and a metal wiring formed by a damascene process according to one embodiment of the present invention;

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 제 1 절연막 패턴 22 : 베리어 메탈21: first insulating film pattern 22: barrier metal

23 : 제 1 금속 배선 24 : 제 2 절연막23: first metal wiring 24: second insulating film

25 : 비아콘택홀 26 : 제 3 절연막25: via contact hole 26: third insulating film

27 : 배선영역 28 : 하부전극27: wiring area 28: lower electrode

29 : 유전막 30 : 상부전극29 dielectric layer 30 upper electrode

31 : 제 2 금속 배선 100 : MIM 캐패시터31: second metal wiring 100: MIM capacitor

본 발명은 반도체 제조 기술에 관한 것으로, 특히 다마신(damascene) 공정에 의해 형성된 금속 배선 및 MIM(Metal-Insulator-Metal) 캐패시터를 갖는 반도체 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having metal wiring and MIM (Metal-Insulator-Metal) capacitors formed by a damascene process.

로직 소자의 고속화, 고집적화는 급속도로 진행되고 있다. 이는 트랜지스터의 미세화에 따라 이루어져 왔는데, 트랜지스터의 집적도 향상에 대응하여 배선이 미세화되고, 배선 급속히 진행되어 왔다. 따라서 고속, 고집적 소자에 있어서는 미세화에 따른 배선 지연의 문제가 심각해지고 있으며,소자의 고속화를 방해하는 원인으로 대두되고 있다.High speed and high integration of logic devices is rapidly progressing. This has been done according to the miniaturization of transistors, and the wiring has been miniaturized and the wiring has been rapidly progressed in response to the increase in the degree of integration of the transistor. Therefore, in the high speed and high integration devices, the problem of wiring delay due to miniaturization is becoming serious, and it is emerging as a cause that hinders the high speed of the devices.

이러한 상황에서 종래부터 LSI(Large Scale Integration)의 배선 재료로 일반적으로 이용해왔던 알루미늄 합금 대신에 보다 비저항이 작고, 높은 EM(Electro migration) 내성을 갖는 재료인 구리(Cu)를 이용한 배선이 활발히 개발되고 있다.In this situation, wiring using copper (Cu), which is a material having a lower specific resistance and high electromigration (EM) resistance, is actively developed instead of an aluminum alloy that has been generally used as a wiring material for large scale integration (LSI). have.

그런데 구리는 종래의 알루미늄 배선 공정에서 사용되어 온 건식 식각 방법이 용이하지 않고, 공정 중에 산화되는 문제점으로 인하여 구리 배선 형성을 위해서는 다마신 공정을 사용한다.However, copper is not easy to use the dry etching method used in the conventional aluminum wiring process, and the damascene process is used to form copper wiring due to the problem of oxidation during the process.

다마신 공정은 종래의 알루미늄을 이용한 배선 공정인 알루미늄 증착, 반응성 이온 식각법에 의한 식각, 절연물 증착과 평탄화라는 일련의 순서와는 상이하다. 즉, 다마신 공정은 절연막 상에 배선홈과 비아홀(via hole)을 형성하고, 구리를 채운 후에 화학적 기계적 연마(Chemical Mechanical Polishing; 이하 'CMP')로 평탄화하는 채움 공정이다.The damascene process is different from the sequence of aluminum deposition, which is a wiring process using conventional aluminum, etching by reactive ion etching, insulator deposition and planarization. That is, the damascene process is a filling process in which wiring grooves and via holes are formed on an insulating film, and copper is filled and then planarized by chemical mechanical polishing (hereinafter, referred to as 'CMP').

다마신 공정에는 비아 플러그(via plug)와 배선 홈을 별도로 형성하는 싱글 다마신 공정과 비아 플러그와 배선홈을 동시에 만드는 듀얼 다마신 공정이 있다. 듀얼 다마신은 비아 플러그와 배선홈을 한 번에 만들기 때문에 싱글 다마신에 비해 종횡비(aspect ratio)가 높지만, 공정 비용 관점에서 듀얼 다마신을 많이 채용하고 있다.The damascene process includes a single damascene process for forming a via plug and a wiring groove separately, and a dual damascene process for simultaneously forming a via plug and a wiring groove. Dual damascene has higher aspect ratio than single damascene because it makes via plug and wiring groove at once, but adopts dual damascene from the viewpoint of process cost.

듀얼 다마신 공정 순서는 비아홀과 배선홈 형성, 금속장벽층(barrier metal) 형성, 비아홀과 배선홈에 구리 채우기, CMP에 의하여 구리 및 금속장벽층 연마의 일련의 순서로 이루어진다.The dual damascene process consists of a sequence of via holes and interconnection grooves, barrier metal formation, copper fill in via holes and interconnection grooves, and copper and metal barrier layer polishing by CMP.

한편 다양한 로직(logic) 소자는 구성을 위하여 수동 소자인 캐패시터가 소자 제조 공정 중에 제조된다. 캐패시터의 구현을 위하여 지금까지는 실리콘 접합(junction)을 이용한 접합 캐패시터 또는 통상적인 알루미늄 배선 기술에서는 플라즈마 강화 화학 기상 증착(Plasma Enhanced Chemical Vapor Deposition; 이하 'PECVD')으로증착한 실리콘 질화막(SiN)을 유전체막으로 하여 알루미늄/실리콘 질화막/알루미늄(Al/SiN/Al)의 MIM(Metal/Insulator/Metal) 캐패시터가 사용되어 왔다.On the other hand, for the various logic devices, capacitors, which are passive devices, are manufactured during the device manufacturing process. For the implementation of the capacitor, a silicon nitride film (SiN) deposited by plasma enhanced chemical vapor deposition (hereinafter referred to as 'PECVD') in a conventional capacitor or a conventional aluminum wiring technology has been used. As the film, a MIM (Metal / Insulator / Metal) capacitor of aluminum / silicon nitride film / aluminum (Al / SiN / Al) has been used.

도 1은 종래 기술의 문제점을 나타내는 TEM 사진으로, 다마신 공정을 적용하지 않고 금속 배선이 형성된 절연막(1) 상에 하부전극(2), 유전막(3), 상부전극(4)을 적층 형성한 후, 캐패시터를 만들기 위해 상부전극(4)을 식각할 때, 정상적으로 식각한 경우(a)에서 보는 바와 같이 유전막(3)에서 식각 정지되어야 하지만, 과도 하게 식각될 경우(b)에서 보는 바와 같이 하부전극(2)이 식각되며, 더 심한 경우 하부전극(2)을 뚫고 하부 절연막(1)이 드러나게 된다. 1 is a TEM photograph showing a problem of the prior art, in which a lower electrode 2, a dielectric film 3, and an upper electrode 4 are stacked on an insulating film 1 on which metal wirings are formed without applying a damascene process. Then, when the upper electrode 4 is etched to make the capacitor, the etching stops at the dielectric layer 3 as shown in the case of normal etching (a), but as shown in the case of excessive etching (b) The electrode 2 is etched, and in more severe cases, the lower insulating film 1 is exposed through the lower electrode 2.

상술한 바와 같이, 금속 배선 및 MIM 캐패시터는 금속 배선을 제조한 후에 다시 그 위에 MIM 캐패시터를 형성하거나 또는 반대로 금속 배선을 제조하기 전에 MIM 캐패시터를 제조하였다. 그러나, 이러한 경우 공정 스텝 증가에 의해 공정 비용이 많이 소요되며 복잡한 공정을 실시해야하는 문제가 있다.As described above, the metal wiring and the MIM capacitor manufactured the MIM capacitor after forming the metal wiring and again forming a MIM capacitor thereon or vice versa before manufacturing the metal wiring. However, in this case, the process cost is increased by increasing the process step, and there is a problem that a complex process must be performed.

또한, 하부전극이 과도하게 식각될 경우 유전막 부분에 메탈이 재증착 되어 누설 소스로 작용하여 MIM 캐패시터의 기능을 할 수 없게 한다.In addition, when the lower electrode is excessively etched, the metal is redeposited on the dielectric layer to act as a leakage source, thereby preventing the MIM capacitor from functioning.

또한, 위와 같은 구조로 금속 배선을 형성하는 경우 유전막의 표면적이 작은 문제가 있다.In addition, when the metal wiring is formed with the above structure, there is a problem that the surface area of the dielectric film is small.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 다마신 공정으로 금속 배선 및 캐패시터를 제조하는데 하부전극의 식각 손실을 방지하여 소자의 특성을 개선하는데 적합한 반도체 소자 및 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device and a manufacturing method suitable for improving the characteristics of the device by preventing the etching loss of the lower electrode in the manufacturing of metal wiring and capacitor by the damascene process Its purpose is to.

상기 목적을 달성하기 위한 특징적인 본 발명의 반도체 소자 및 제조 방법은 제 1 금속 배선이 형성된 절연막 패턴, 상기 절연막 패턴 상부에 형성된 듀얼 다마 신 패턴, 상기 듀얼 다마신 패턴 내부 표면을 따라 형성된 캐패시터; 및 상기 듀얼 다마신 패턴 내부를 매립하는 제 2 금속 배선을 포함한다.A semiconductor device and a manufacturing method of the present invention for achieving the above object comprises: an insulating film pattern formed with a first metal wiring, a dual damascene pattern formed on the insulating film pattern, a capacitor formed along an inner surface of the dual damascene pattern; And a second metal wire filling the inside of the dual damascene pattern.

또한, 본 발명은 반도체 기판 상부에 제 1 금속 배선이 형성된 절연막 패턴을 형성하는 단계, 상기 절연막 패턴 상부에 상기 제 1 금속 배선 상부를 오픈하는 듀얼 다마신 패턴을 형성하는 단계, 상기 듀얼 다마신 패턴의 내부 표면을 따라 캐패시터를 형성하는 단계, 및 상기 듀얼 다마신 패턴을 매립하는 제 2 금속 배선을 형성하는 단계를 제공한다.The present invention also provides a method of forming an insulating film pattern on which a first metal wiring is formed on a semiconductor substrate, forming a dual damascene pattern to open an upper portion of the first metal wiring on the insulating film pattern, and the dual damascene pattern. Forming a capacitor along an inner surface of the substrate, and forming a second metal wiring to fill the dual damascene pattern.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(도시하지 않음) 상에 제 1 금속 배선(23)이 형성된 제 1 절연막 패턴(21)을 형성한다. 이 때, 제 1 금속 배선(23) 내부에 도전 물질을 채우기 전에 또 다른 도전 물질층인 베리어 메탈(22)을 형성할 수 있다. 베리어 메탈(22)은 바람직하게는 Ti/TiN의 이중막으로 형성하는 것이 바람직하나, Ti/TiN의 이중막으로만 한정되는 것은 아니며, 티타늄(Ti), 지르코늄(Zr), 하프늄(Hf), 바나디윰(V), 몰리브데늄(Mo), 탄탈륨(Ta), 크롬(Cr)의 단일막 또는 이들간의 이중막 이상의 층상 구조일 수 있다. 또한, 경우에 따라서 Ti, Zr, Hf, V, Mo, Ta 및 Cr의 질화물(Nitride), 탄화물(Carbide) 또는 실리사이드(Silicide)를 사용할 수 있다.As shown in FIG. 2A, a first insulating film pattern 21 on which a first metal wire 23 is formed is formed on a semiconductor substrate (not shown). In this case, the barrier metal 22, which is another conductive material layer, may be formed before the conductive material is filled in the first metal wire 23. Barrier metal 22 is preferably formed of a double film of Ti / TiN, but is not limited to a double film of Ti / TiN, titanium (Ti), zirconium (Zr), hafnium (Hf), It may have a layered structure of vanadium (V), molybdenum (Mo), tantalum (Ta), chromium (Cr) single layer or a double layer or the like. In some cases, nitrides, carbides, or silicides of Ti, Zr, Hf, V, Mo, Ta, and Cr may be used.

또한, 제 1 금속 배선(23)은 알루미늄(Al), 금(Au), 은(Ag), 텅스텐(W), 도핑된 폴리실리콘막(Doped PolySi) 및 구리(Cu)와 같은 물질 중에서 비저항이 작은 금속류를 선택적으로 사용하여 전기도금법으로 형성한다.In addition, the first metal wiring 23 has a specific resistance among materials such as aluminum (Al), gold (Au), silver (Ag), tungsten (W), doped polysilicon (Doped PolySi), and copper (Cu). Small metals are selectively used to form the electroplating method.

이어서, 제 1 금속 배선(23)이 형성된 결과물의 전면에 제 2 및 제 3 절연막 패턴(24, 26)을 형성한다.Subsequently, second and third insulating film patterns 24 and 26 are formed on the entire surface of the resultant product in which the first metal wirings 23 are formed.

더 자세히는, 제 1 금속 배선(23)이 형성된 결과물의 전면에 제 2 절연막(24)을 형성한다. 그런다음, 제 2 절연막(24) 상에 포토레지스트를 도포하고 노광 및 현상을 진행하여 배선 영역을 형성하기 위한 포토레지스트 패턴(도시하지 않음)을 형성한다.More specifically, the second insulating film 24 is formed on the entire surface of the resultant product in which the first metal wirings 23 are formed. Then, a photoresist is applied on the second insulating film 24, and exposure and development are performed to form a photoresist pattern (not shown) for forming the wiring region.

한편, 제 2 절연막(24)은 다층 배선 구조에서 발생하는 기생 캐패시턴스를 고려하여 적절한 유전율을 갖는 절연 물질을 선택하여 형성하되 실리콘산화막(SixOy), 실리콘질화막(SixNy), 및 실리콘산화질화막(SixOyNz)과 같은 물질 중에서 선택하여 사용한다. 다층 배선 구조를 구비하는 반도체 집적회로 소자의 경우에는 제 2 절연막(24)의 두께는 다층 배선 구조에서 유발되는 배선층간의 기생 캐패시턴스를 고려하고 반도체 집적회로 소자의 3차원적 토폴로지를 고려하여 결정되어야 하는데 바람직하게는 500Å∼3000Å이 두께로 형성한다. On the other hand, the second insulating film 24 is formed by selecting an insulating material having an appropriate dielectric constant in consideration of the parasitic capacitance generated in the multilayer wiring structure, but the silicon oxide film (Si x O y ), silicon nitride film (Si x N y ), and It is used by selecting from materials such as silicon oxynitride film (Si x O y N z ). In the case of a semiconductor integrated circuit device having a multilayer interconnection structure, the thickness of the second insulating film 24 should be determined in consideration of the parasitic capacitance between interconnection layers caused in the multilayer interconnection structure and the three-dimensional topology of the semiconductor integrated circuit device. Preferably, 500 micrometers-3000 micrometers are formed in thickness.

계속해서, 포토레지스트 패턴을 이용하여 제 1 금속 배선이 드러나는 타겟으로 제 2 절연막(24)을 선택적으로 식각하여 비아콘택홀(25)을 형성하고, 포토레지스트 패턴은 스트립한다.Subsequently, the via contact hole 25 is formed by selectively etching the second insulating layer 24 using the photoresist pattern to expose the first metal wires, and the photoresist pattern is stripped.

이어서, 비아콘택홀(25)에 제 2 절연막(24)과 선택비가 좋은 무기계열의 절연막으로 무기 SOG막(도시하지 않음)을 매립한다.Subsequently, an inorganic SOG film (not shown) is filled in the via contact hole 25 with the second insulating film 24 and the inorganic series insulating film having a good selectivity.

다음으로, 무기 SOG막이 매립된 제 2 절연막(24) 상에 제 3 절연막(26)을 증착한다. 제 3 절연막(26) 상에 배선 영역(27)을 형성하기 위한 마스크로 포토레지스트 패턴(도시하지 않음)을 형성하고, 포토레지스트 패턴을 식각마스크로 무기 SOG막이 드러나는 타겟으로 제 3 절연막(26)을 선택적으로 식각하여 배선 영역(27)을 형성하고, 포토레지스트 패턴은 스트립한다.Next, the third insulating film 26 is deposited on the second insulating film 24 in which the inorganic SOG film is embedded. A photoresist pattern (not shown) is formed as a mask for forming the wiring region 27 on the third insulating layer 26, and the third insulating layer 26 is used as a target in which the inorganic SOG film is exposed using the photoresist pattern as an etching mask. Is selectively etched to form the wiring region 27, and the photoresist pattern is stripped.

계속해서, BOE 용액 또는 불산 용액을 이용하여 무기 SOG막을 제거하여 듀얼 다마신 패턴(25,27)을 형성한다.Subsequently, the inorganic SOG film is removed using a BOE solution or a hydrofluoric acid solution to form dual damascene patterns 25 and 27.

도 2b에 도시된 바와 같이, 듀얼 다마신 패턴이 형성된 결과물의 표면을 따라, 캐패시터 형성을 위한 하부전극(28) 및 유전막(29)을 증착한다. As shown in FIG. 2B, a lower electrode 28 and a dielectric film 29 for capacitor formation are deposited along the surface of the resultant product having the dual damascene pattern.

한편, 배선영역과 캐패시터영역은 그 구조를 다르게 형성하는데 배선영역과 캐패시터영역에 하부전극(28)과 유전막(29)을 증착한 후, 캐패시터영역에 캐패시터영역을 모두 덮는 포토레지스트 패턴(도시하지 않음)을 형성하고, 배선영역의 유전막(29)을 식각하여 제거한다. 식각 후, 포토레지스트 패턴을 스트립하고, 결과물을 따라 상부전극(30)을 증착한다.On the other hand, the wiring region and the capacitor region have different structures, and after depositing the lower electrode 28 and the dielectric film 29 on the wiring region and the capacitor region, the photoresist pattern covering all of the capacitor region in the capacitor region (not shown) ), And the dielectric film 29 in the wiring region is etched and removed. After etching, the photoresist pattern is stripped and the upper electrode 30 is deposited along the resultant.

그리고나서, 화학적 기계적 연마(Chemical Mechanical Polishing; CMP) 또는 전면 식각(Etch Back)을 실시하여 제 3 절연막(26)이 드러나는 타겟으로 평탄화 식각하여 배선영역과 캐패시터영역을 분리한다.Then, chemical mechanical polishing (CMP) or etching back is performed to planarly etch the target to expose the third insulating layer 26 to separate the wiring region and the capacitor region.

한편, 하부전극(28) 및 상부전극(30)은 Ta, W, TaN, WN, Ti 및 TiN에서 선택된 물질을 사용하고 100Å∼500Å의 두께로 스퍼터링 또는 기상저합화학기상증착법(ALCVD)으로 증착하며, 유전막(29)은 SiN, Ta2O5, Al2O3, 및 HfO2에서 선택된 물질을 사용하며, 100Å∼1000Å의 두께로 플라즈마강화화학기상증착법(PECVD)으로 증착한다.On the other hand, the lower electrode 28 and the upper electrode 30 is made of a material selected from Ta, W, TaN, WN, Ti and TiN, and deposited by sputtering or vapor phase chemical vapor deposition (ALCVD) to a thickness of 100 ~ 500Å The dielectric film 29 uses materials selected from SiN, Ta 2 O 5 , Al 2 O 3 , and HfO 2 , and is deposited by plasma enhanced chemical vapor deposition (PECVD) at a thickness of 100 kPa to 1000 kPa.

도 2c에 도시된 바와 같이, 결과물의 전면에 배선용 물질을 증착하여 듀얼 다마신 패턴을 매립한 후, CMP 또는 전면 식각으로 제 3 절연막(26)이 드러나는 타겟으로 평탄화 식각하여 제 2 금속 배선(31)을 형성한다. 이 때, 제 2 금속 배선(31)은 알루미늄(Al), 금(Au), 은(Ag), 텅스텐(W), 도핑된 폴리실리콘막(Doped PolySi) 및 구리(Cu)와 같은 물질 중에서 비저항이 작은 금속류를 선택적으로 사용하여 전기도금법으로 형성한다.As shown in FIG. 2C, the wiring material is deposited on the entire surface of the resultant to fill the dual damascene pattern, and then the surface of the second metal wiring 31 is planarized by etching the target to expose the third insulating layer 26 by CMP or front surface etching. ). At this time, the second metal wiring 31 has a resistivity among materials such as aluminum (Al), gold (Au), silver (Ag), tungsten (W), doped polysilicon (Doped PolySi), and copper (Cu). The small metals are selectively used to form the electroplating method.

상술한 바와 같이, 본 발명은 듀얼 다마신 공정을 적용하여 공정 스텝을 줄일 수 있고, 캐패시터 식각을 직접하지 않고 다마신 공정으로 제조하기 때문에 캐패시터 식각시 발생하는 하부전극 데미지를 방지할 수 있다.As described above, the present invention can reduce the process step by applying a dual damascene process, and can be produced by the damascene process instead of the capacitor etching directly, it is possible to prevent the lower electrode damage caused during the capacitor etching.

또한, 상기와 같은 캐패시터(100) 구조를 적용하여 유전막 표면적을 증가시킬 수 있다.In addition, the surface of the dielectric film may be increased by applying the capacitor 100 structure as described above.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으 나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 공정 스텝을 줄여 비용을 절감하는 효과가 있으며, 다마신 공정을 적용하기 때문에, 상부전극 식각시 발생하는 하부전극의 손실 또는 펀치 스루를 방지하는 효과를 얻을 수 있다.The present invention described above has the effect of reducing the cost by reducing the process step, and since the damascene process is applied, it is possible to obtain the effect of preventing the loss or punch-through of the lower electrode generated during the upper electrode etching.

또한, 본 발명은 MIM 캐패시터 중 절연물의 단면적을 크게 증가시킬 수 있는 효과가 있다.In addition, the present invention has an effect that can greatly increase the cross-sectional area of the insulation in the MIM capacitor.

또한, 본 발명은 금속 배선과 MIM 캐패시터를 동시에 제조 가능하기 때문에, 기존 제품보다 공정 능력 향상에 기여하는 효과가 있다.In addition, since the present invention can manufacture the metal wiring and the MIM capacitor at the same time, there is an effect that contributes to the improvement of the process capability than the existing products.

Claims (13)

제 1 금속 배선이 형성된 절연막 패턴;An insulating film pattern on which the first metal wiring is formed; 상기 절연막 패턴 상부에 형성된 듀얼 다마신 패턴;A dual damascene pattern formed on the insulating layer pattern; 상기 듀얼 다마신 패턴 내부 표면을 따라 형성된 캐패시터; 및A capacitor formed along an inner surface of the dual damascene pattern; And 상기 듀얼 다마신 패턴 내부를 매립하는 제 2 금속 배선A second metal wire to fill the dual damascene pattern 을 포함하는 반도체 소자.Semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제 1 및 제 2 금속 배선은 알루미늄, 금, 은, 텅스텐, 도핑된 폴리실리콘막 및 구리로 이루어진 그룹에서 선택된 물질로 형성된 반도체 소자.The first and second metal wires are formed of a material selected from the group consisting of aluminum, gold, silver, tungsten, a doped polysilicon film, and copper. 제 1 항에 있어서,The method of claim 1, 상기 캐패시터는, 하부전극 및 상부전극으로 탄탈륨, 텅스텐, 탄탈륨질화막, 텅스텐질화막, 티타늄막 및 티타늄질화막으로 이루어진 그룹에서 선택된 물질로 형성된 반도체 소자.The capacitor is a semiconductor device formed of a material selected from the group consisting of tantalum, tungsten, tantalum nitride film, tungsten nitride film, titanium film and titanium nitride film as the lower electrode and the upper electrode. 제 3 항에 있어서,The method of claim 3, wherein 상기 하부전극 및 상부전극은 100Å∼500Å의 두께로 형성된 반도체 소자.The lower electrode and the upper electrode is a semiconductor device formed to a thickness of 100 ~ 500Å. 반도체 기판 상부에 제 1 금속 배선이 형성된 절연막 패턴을 형성하는 단계;Forming an insulating film pattern having a first metal wiring formed on the semiconductor substrate; 상기 절연막 패턴 상부에 상기 제 1 금속 배선 상부를 오픈하는 듀얼 다마신 패턴을 형성하는 단계;Forming a dual damascene pattern on the insulating layer pattern to open the upper portion of the first metal wire; 상기 듀얼 다마신 패턴의 내부 표면을 따라 캐패시터를 형성하는 단계; 및Forming a capacitor along an inner surface of the dual damascene pattern; And 상기 듀얼 다마신 패턴을 매립하는 제 2 금속 배선을 형성하는 단계Forming a second metal wire to fill the dual damascene pattern 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 5 항에 있어서,The method of claim 5, 상기 듀얼 다마신 패턴의 내부 표면을 따라 캐패시터를 형성하는 단계는,Forming a capacitor along the inner surface of the dual damascene pattern, 상기 듀얼 다마신 패턴 표면을 따라 하부전극, 유전막, 상부전극을 차례로 형성하는 단계; 및Sequentially forming a lower electrode, a dielectric layer, and an upper electrode along a surface of the dual damascene pattern; And 상기 듀얼 다마신 패턴이 표면이 드러날 때까지 상기 하부전극, 유전막, 상부전극을 평탄화 식각하는 단계를 포함하는 반도체 소자 제조 방법.And planarizing etching the lower electrode, the dielectric layer, and the upper electrode until the surface of the dual damascene pattern is exposed. 제 6 항에 있어서,The method of claim 6, 상기 하부전극 및 상부전극은 탄탈륨, 텅스텐, 탄탈륨질화막, 텅스텐질화막, 티타늄막 및 티타늄질화막으로 이루어진 그룹에서 선택된 물질로 형성하는 반도체 소자 제조 방법. The lower electrode and the upper electrode are formed of a material selected from the group consisting of tantalum, tungsten, tantalum nitride film, tungsten nitride film, titanium film and titanium nitride film. 제 6 항에 있어서,The method of claim 6, 상기 하부전극 및 상부전극은 100Å∼500Å의 두께로 형성하는 반도체 소자 제조 방법.The lower electrode and the upper electrode is a semiconductor device manufacturing method to form a thickness of 100 ~ 500Å. 제 6 항에 있어서,The method of claim 6, 상기 하부전극 및 상부전극은 스퍼터링 또는 ALCVD로 형성하는 반도체 소자 제조 방법.And forming the lower electrode and the upper electrode by sputtering or ALCVD. 제 6 항에 있어서,The method of claim 6, 상기 유전막은 SiN, Ta2O5, Al2O3, 및 HfO2로 이루어진 그룹에서 선택된 물질을 사용하는 반도체 소자 제조 방법.The dielectric film is a semiconductor device manufacturing method using a material selected from the group consisting of SiN, Ta 2 O 5 , Al 2 O 3 , and HfO 2 . 제 10 항에 있어서,The method of claim 10, 상기 유전막은 100Å∼1000Å의 두께로 PECVD로 증착하는 반도체 소자 제조 방법.The dielectric film is a semiconductor device manufacturing method which is deposited by PECVD in a thickness of 100 ~ 1000Å. 제 5 항에 있어서,The method of claim 5, 상기 제 1 및 제 2 금속 배선은 알루미늄(Al), 금(Au), 은(Ag), 텅스텐(W), 도핑된 폴리실리콘막(Doped PolySi) 및 구리(Cu)로 이루어진 그룹에서 선택된 물질을 사용하는 반도체 소자 제조 방법.The first and second metal wires may be formed of a material selected from the group consisting of aluminum (Al), gold (Au), silver (Ag), tungsten (W), doped polysilicon (Doped PolySi), and copper (Cu). A semiconductor device manufacturing method to be used. 제 5 항에 있어서,The method of claim 5, 상기 제 1 금속 배선은 내부에 베리어 메탈을 포함하는 반도체 소자 제조 방법.The first metal wire is a semiconductor device manufacturing method comprising a barrier metal therein.
KR1020050067979A 2005-07-26 2005-07-26 Method of forming semiconductor device with capacitor and metal interconnection in damascene process KR101153224B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050067979A KR101153224B1 (en) 2005-07-26 2005-07-26 Method of forming semiconductor device with capacitor and metal interconnection in damascene process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050067979A KR101153224B1 (en) 2005-07-26 2005-07-26 Method of forming semiconductor device with capacitor and metal interconnection in damascene process

Publications (2)

Publication Number Publication Date
KR20070013572A true KR20070013572A (en) 2007-01-31
KR101153224B1 KR101153224B1 (en) 2012-06-07

Family

ID=38013248

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050067979A KR101153224B1 (en) 2005-07-26 2005-07-26 Method of forming semiconductor device with capacitor and metal interconnection in damascene process

Country Status (1)

Country Link
KR (1) KR101153224B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100787707B1 (en) * 2006-08-30 2007-12-21 동부일렉트로닉스 주식회사 Method of fabricating semiconductor device having multi layer cu line and mim capacitor
WO2008157338A1 (en) * 2007-06-14 2008-12-24 Svtc Technologies, Llc Copper-free semiconductor device interface and methods of fabrication and use thereof
US10553363B2 (en) 2016-03-22 2020-02-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor having via electrode and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100787707B1 (en) * 2006-08-30 2007-12-21 동부일렉트로닉스 주식회사 Method of fabricating semiconductor device having multi layer cu line and mim capacitor
WO2008157338A1 (en) * 2007-06-14 2008-12-24 Svtc Technologies, Llc Copper-free semiconductor device interface and methods of fabrication and use thereof
US10553363B2 (en) 2016-03-22 2020-02-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor having via electrode and method of manufacturing the same

Also Published As

Publication number Publication date
KR101153224B1 (en) 2012-06-07

Similar Documents

Publication Publication Date Title
US7332764B2 (en) Metal-insulator-metal (MIM) capacitor and method of fabricating the same
KR100532455B1 (en) Method for manufacturing semiconductor device including MIM capacitor and interconnect structure
JP3895126B2 (en) Manufacturing method of semiconductor device
KR100468069B1 (en) Self-aligned metal caps for interlevel metal connections
US20050263848A1 (en) Metal-insulator-metal capacitor having a large capacitance and method of manufacturing the same
US6468898B1 (en) Method of manufacturing semiconductor device
JP3540895B2 (en) Semiconductor device wiring forming method
KR100806034B1 (en) Semiconductor device having metal-insulator-metal capacitor and fabrication method for the same
JP2007221161A (en) Capacitor used in semiconductor device, and production method thereof
KR100835409B1 (en) Method for manufacturing damascene mim type capacitor of semiconductor device
KR20060113825A (en) Metal interconnection having low resistance in semiconductor device and method of fabricating the same
US8338951B2 (en) Metal line of semiconductor device having a diffusion barrier with an amorphous TaBN layer and method for forming the same
KR101153224B1 (en) Method of forming semiconductor device with capacitor and metal interconnection in damascene process
CN109524348B (en) Fully aligned vias in a substantially regular region
KR100701426B1 (en) Multi layer metal in semiconductor device and method for manufacturing the same
KR100831981B1 (en) Method for forming contact plug in semiconductor device
KR101168507B1 (en) Semiconductor device and method for forming the same
KR20070119173A (en) Method of forming a metal line in a semiconductor device
JP2002319632A (en) Semiconductor device and manufacturing method therefor
KR20080061168A (en) Method of manufacturing a metal line in semiconductor device
JP2006310894A (en) Semiconductor device and its manufacturing method
KR100784105B1 (en) Method of manufacturing a semiconductor device
KR100899566B1 (en) Method for forming bitline in semiconductor device
KR20050003296A (en) Method for forming the semiconductor memory device having a self-aligned contact hole
KR100807513B1 (en) Metal-insulator-metal capacitor forming method for semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20150416

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee