TW525262B - Method for forming a gate insulating film for semiconductor devices - Google Patents

Method for forming a gate insulating film for semiconductor devices Download PDF

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TW525262B
TW525262B TW089127924A TW89127924A TW525262B TW 525262 B TW525262 B TW 525262B TW 089127924 A TW089127924 A TW 089127924A TW 89127924 A TW89127924 A TW 89127924A TW 525262 B TW525262 B TW 525262B
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insulating film
taon
amorphous
film
patent application
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TW089127924A
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Dong-Su Park
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Hyundai Electronics Ind
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Description

525262
五、發明說明（1) <發明之範圍> ：關於-種半導體元件之 ί:匕=於-種適合於高積體半導體元件ί:二 /、：；特性的半導體元件之閑絕緣膜形成方法。具有優 <發明之背景 > 戈 通常金氧半導體場效應電晶體（M0SFET)，苴 以一做為閘絕緣膜的薄氧化石夕 八]咆極係 私日日脰，其阻抗甚少低減，又因閘二i 即可形成，是以製造方法簡單，適合高積體化，擴畋過程 又為了提咼半導體記憶裝置之積集度， 匕，單房電晶體間絕緣膜的厚度及寬度實；=· 鈿小。例如下一世代的256M DRAM以上的記憶I置，盥一π 般閘絕緣膜製造方法一樣，實施8 0 0〜9 0 0 1的高γ、 乳化過程，以矽氧化膜的成長形成閘絕緣膜。此時：絕、ς 犋厚度形成5 0 0 Α以下，維持元件屈伏（breakd〇wn)強度特 性與對印加於閘電極電壓的耐性時間於所期望之值。 /又最近做為高積體記憶裝置的閘絕緣膜者，則有高介 電係數（ε二25)的TaA來化替Si〇2，此時由KTa2〇5本身具 有不安定的化學量論比（stoichiometry)，致有發生因Ta ，〇組成比之差的置換型Ta原子於薄膜内之場合。X為此， 蒸著TaJ2閘絕緣膜時，由於TaJ5的前驅體^(〇(^{}5 )5等有 機物與〇2(或〜0)氣體反應，致有生成不純物如子、碳 化合物（c、ch4、c2h4等）及水（M)的缺點。…
第5頁 這些的以不純物存在於Taj5閘絕緣膜内的碳原子、離 問電極與基板間的洩漏電流，絕緣特性劣 ......- 通常在蒸著TaJ5後，須進行一次以上白 理（例如電漿或uV-〇3)過程與高溫熱處理 明之總論> ° $ 渙熱處 之發明之總論> 氧p--------- 一 >丨〜，皿恐羝段迥桎吋丞扳表面發生f务 ==的寄ΐ氧化膜，使基板與^間絕緣膜 間的界面持性名化，同時增加了整個閘絕緣膜的昃 於是本發明的目的乃在提供具有優異電氣 件的閘絕緣膜形成方法。 的千导 然而這樣的熱處理過程實在太煩雜，因絕緣膜 牝抵抗性低，致在高溫熱處理過程時基板表面、 應，形成不均勻的寄生氧化膜，使基板盥τ x + 雜元件的閘絕緣膜形成方法 又本發明的另一目的在提供能翁 ^ … #攸1/、此约防止其他元侔雷裔4士 十生劣化的半導體元件之閘絕緣膜形成方法 八寸 又本發明的£ _日沾太坦w Λμ⑹_ y ^ 〇 製 又本發明的再一目的在提供能夠單純化半導 造過私的半導體几件之閘絕緣膜形成方法。 的 又本發明的又一目的在提件能％ 導體元件之閘絕緣膜形成方法。^ W ，、‘品壽命的半 為了達成上揭各目的，本發明提 絕緣膜形成方法，其包括的步驟有：才、主+ ^脰兀件之閘 界定（de f i ne )活性領域及元件分離 導版基板上形成 化膜形成過程；在形成有該場氧場氧化膜的場氧· 化物絕緣膜的含有氮化物絕緣膜形：、珥：板上形成含有氮· 物絕緣膜上形成非晶質Ta0N絕緣膜=程；在該含有氮化 成過程；及使該非晶質TaON絕緣膜姓1曰晶質Ta〇N絕緣膜形 〈較佳具體實施例之詳細描述>、、、、°晶的結晶化過程。
525262
广又中參 膜的y上 …4 +啜明的午導體元件之閘絕綾 ΪΓ二4法具體實施例。本發明方法的各過程則說明ί β至弟5圖之半導體元件剖面圖。 、 元子Ιί如第1圖所示，在半導體基板（1〇)上施行通常的 形二，過程（例如削地（L0C0S)或挖溝（Trench)過程）而 二Γ，j疋兀件的活線領域與分離領域的場氧化膜（12)。发 (^2; JHF、％ —1、Μ〇4等化學物品清洗形成有場氧化膘 細粒子:板（1 〇 )表面：藉以除去基板表面的自然氧化臈及 “者在半導體基板（10)的後續工程實施的非晶質Ta0N _ 筏ί 4，為了防止在基板（10)界面形成不均勻的低介電 ^氧化膜，如第2圖所示的，形成氮化薄膜（Si ， 化薄膜（SiON)(14)。 · 。此時該氮化薄膜U 4)可在2〇〇〜6〇〇 t：左右，最好在 35〇 C〜4 5 0 °C左右的溫度範圍的低壓化學氣基 〜又氮氧化薄膜（14)可在低壓化學氣相蒸著室中以2〇〇 恭〇〇 c左右，最好是在350〜45〇。〇左右溫度範圍，利用 :水、題3、及〇2或等，對該室内以流量調節器（mass w controller)為介，做iq〜i〇Q〇sccm左右的定量供應修 而幵/成。又在氮氧化薄膜（丨4)形成之際，為免在基板（1〇) 表面形成寄生氧化膜，在電漿環境中先注入腿3，而化或 瓦斯則在以後注入為宜。 這樣在後述的非晶質TaON蒸著前實施的基板（10)的氮
525262 五、發明說明（4) 化處理或氮氧化處理以2 0 0〜8〇(TC，最好是35〇〜45〇t左 广的較為低溫下進行，因而可防止已經形成的場氧化膜 (1 2)铃凹井等其他元件電氣特性的劣化。 其次如第3圖所示，在基板（10)的氮化薄膜或 1 =⑷的上面蒸著非晶fTaQN膜而形成閘絕緣膜(⑻。 $广化學蒸汽，係使用例如MOCA、、ΜΑ等h夺化 B物寻以流量調節器為介來定量供應，而以15〇〜2〇〇^ 右的溫度範圍使其蒸發而得。然後該“化學蒗汽盥 的〇2及龍3瓦斯以流量調節器為介，供⑽〜_ 2 =低壓化學氣相蒸著室内•，誘起表面化學反岸而· 瘵者非晶質TaON膜（16)。 子久應、肉 蒸著過程中生成的碳化合物的不純物與存在於 空孔，並誘導結晶化。 、、内的乳乳 此時’該退火過程可利用急速熱處理(rapl = 以6 50〜9 5 0 °C左右的溫度條件下進行0. 5〜 刀"里左右，以除去在非晶質Ta〇N膜蒸著過程 化合物的不純物並誘導結晶化。 生成的反 再者，該退火過程係利用電氣爐以65〇〜 溫度範圍與Μ、〇2«2環境下進行卜30分鐘來誘H右曰的 負TaON膜的結晶化為宜。此時由於退火過程， ： 晶質TaON間絕緣膜⑽的結晶化，一面除 產生的膜内揮發性碳化合物（C〇 、私中所 A 、Μ4)，補強界
525262
五、發明說明（5) :=j裂(micro crack)及針孔等構造上的缺陷，而 另一方面，在非晶質TaON膜（16)形成後，以in_situ 了ltl1，利用電漿在20 0〜6〇。°c左右，nh3(咬N /H ) if > m仃虱虱化過私。此時可省略須在約70 0 t：以上严产進 火，。其理由在Ta〇N蒸著後進行如此的氮:度二 i緣;=結Γ皮形求閘電極後進行的後續過程使議 其次，如第4圖所示，在間頌给描广彳β、l 用滲雜繁矽胺±在閘'巴緣膜（16)上形成閘電極 气/士 ^/夕胰（1δ)。此日守滲雜聚矽膜（18)上因其高電阻電 *寸盆：亦可追加積層做為金屬矽化物質的鎢矽化膜。 八-人，如第5圖所示，可刺用門 、
TaON ,1 ^ ^ /(H) /A f ^ ^ # 化薄膜^ ) 4膜（或氣氧
形成碜雜聚矽膜圖型（18a)，TaON f 扣⑹Μ化薄膜（或氮氧化薄膜）圖型 (14a)，完成閘電極製造過程。 联；ΰ孓 法有月，本發明的半導體元件之閘絕緣膜形成方 電係ί (V二方〜G:::;為閘絕緣臈材料的τ_ ’其介 c^〇2) ^ ^ t #1, Λ ^ # " ^ ^ ^ ^ 厚度為厚，但電氣厚声 W軏白知的閘氧化膜的物理 之間絕緣膜。可減低而可得高積體半導體元件 象版特f生絶緣屈伏強度提高而延長製品壽命。 第9頁 525262
i··"·11 1 ' 1 ---— ——I 五、發明說明（6) 再者’本發明的TaON閘絕緣膜較習知Ta2〇3閘絕緣膜在 構造上安定。與矽基板的氧化反應性亦小，因而對外加電 氣衝擊抵抗亦大，絕緣破壞電壓提高，洩漏電流減少。 又本發明的氮化處理，係在TaON閘絕緣膜蒸著之前， 氮化或氮氧化處理石夕基板表面，因此增加後續工程中的氧 化抵抗性而抑制不均勻氧化膜的生成，改善界面特性。 斤又，本發明的氮化或氮氧化處理與既有的急速熱處理 ，^化或氮氧化比較：如在2〇〇〜6 0G°C左右較為低溫下進 行’可防止其他元件電氣特性的劣化。 、，又，本發明的氮化或氮氧化處理，如以TaON膜蒸著裝_ 備亚以ln-situ進行，則不需另外的裝備，可簡化製造過 制本發明實本發明較佳之具體細，並非用來限 同等變更“’即凡依本發明中請專利範圍所做之 專利範圍所如未能超出本發明之内$ ’概為本發明 525262 第1圖至第5圖為說明本發明半導體元件之閘絕緣膜形 圖式簡單說明 成方法的過 程 剖 面 圖。 <圖式中元 件 名 稱 與符號之對照> 10 半 導 體 基 板 12 場 氧 化 膜 14 氮 化 薄 膜 (或氮氧化薄膜） 16 TaON 閘 絕 緣率 18 滲 雜 聚 矽 膜 _
第11頁

Claims (1)

  1. 525262 _案號 89127924_ 年 六、申請專利範圍 曰 修正 氣；以及， 將Ta化學蒸氣喷出至LPCVD室中。 6 ·如申請專利範圍第1項之方法，其中形成非晶質 TaON絕緣膜的步驟更包括： 供應定量之Ta化學蒸氣、03及/或02，以及NH3至一 LPCVD 室； 在300至600 t：的溫度下，於小於lOOtorr的壓力下， 且以一0· 15至2torr(在低壓製程）或50至30 0torr(在一高 壓製程）的施加電力，來誘導了&化學蒸氣、〇3與NH3之間的 表面化學反應。 7 ·如申請專利範圍第1項之方法，其中結晶化非晶質 Ta0N絕緣膜的步驟更包括將非晶質TaON絕緣膜退火之步 :如申請專利範圍第7項之方法，其中將非晶質丁&训 、、、邑緣膜退火之步驟更包括對Ta〇N非晶質絕緣膜加熱至65〇 〜950 C溫度範圍内；以及 維持非晶質Ta〇N絕緣膜於此溫度範圍内〇· 5〜3〇分鐘 緣膜項之方法’其中將非晶質· 下對TaON絕緣膜加熱至6 50至 於此溫度範圍内1〜3 0分鐘
    。在一Ν2〇、〇2或化的氣壓 9 5 0 C之間的溫度；以及 維持非晶質Ta0N絕緣膜 者0 、
    第13頁 525262
    12.—種半導體元件之ι絕緣膜形成方法 步驟有： ，、巴栝的 提供一包括有活性領域與元件分離領域的半 板，而半導體基板的一表面乃曝露於活性領域中._土 =導體基板之活性領域上形成一絕緣膜，i 馭包括氮化矽或氮氧化矽； ，、中絕緣 形成一TaON絕緣膜於氮化矽或氮氧化矽上·， 結晶化非晶質TaON絕緣膜。 ’ T U取一氮化矽膜之步驪，二 此LPCVD室係在20 0〜60 0。(：之間，於NH 盘口 驛而 操作。 力關3或〜與心之氣壓下 範圍第12項之方法’纟中 〜7驟更包括於一LPCVD室中形成—氮化矽膜之步驟''，= 此LPCVD室係在20 0〜60 0 t：之間，於Nh3或〇2與\〇之 操作。 笑卜 1 5·如申請專利範圍第1 2項之方法，其中形 質TaON絕緣膜之步驟更包括： ’ 非晶 1 3·如申請專利範圍第！ 2項之方豆 之步驟更包括於一 LPCVD室中形成一氮化:夕膜=緣骐 此LPCVD室係在20 0〜60 0 °C之間，於μη 々μ也了τ 乂鄉而 之 525262 案號 89127924 年 月 曰 修」 六、申請專利範圍 利用通過一流量調節器，供應一固定量之Ta系化合物 至一蒸發器而得一 T a化學蒸氣：以及 在1 5 0〜2 0 0 C溫度範圍將τ a化合物蒸發。 1 6 „如申請專利範圍第丨2項之方法，其中形成非晶質 TaON絕緣膜的步驟更包括： 、 供應定量之Ta化學蒸氣、〇、;及/或〇2，以及至一 LPCVD 室； 在300至600 °C的溫度下，於小於i〇〇torr的壓力下， 且以一〇· 15至2torr(在低壓製程）或50至3 00torr(在一高
    壓製程）的施加電力，來誘導Ta化學蒸氣、〇3與NH3之間的 表面化學反應。 ^ 1 f ·如申請專利範圍第1 2項之方法，其中結晶化非晶 質TaON絕緣膜的步驟更包括將非晶fTa〇N絕緣膜退火之 驟。 1 8 ·如申請專利範圍第1 2項之方法，其中將非晶質 絕緣膜退火之步驟更包括對Ta〇N非晶質絕緣膜加熱 650〜950 °C溫度範圍内；以及 維持非晶質TaON絕緣膜於此溫度範圍内〇 · 5〜3 〇分鐘 者。
    2 .如申請專利範圍第17項之方法，其中將非晶質 Ta〇N纟巴緣胰退火之步驟更包括·· 95〇 〇c 〜〇、〇2或1的氣壓下對TaON絕緣膜加熱至650至 之間的溫度；以及 、非晶質TaON絕緣膜於此溫度範圍内1〜3〇分鐘
    第15頁 525262 _案號 89127924_年月日_ί±^._ t、申請專利範圍 者。 2 0,如申請專利範圍第1 2項之方法，其更包括在2 0 0至 6 0 0 t的溫度範圍内，於NH3或N2與H2的氣壓下，以電漿處 理氮化非晶質TaON絕緣膜之一個表面者。 2 1. —種半導體元件之閘絕緣膜形成方法，其包括的 步驟有： 提供一半導體基板’此半導體基板包括被元件分離領 域分開之活性領域，而元件分離領域包含場氧化物； 在半導體基板的曝露表面上形成含有氮的絕緣膜； 在該含有氮的絕緣膜上形成非晶質TaON絕緣膜；及 使該非晶質TaON絕緣膜結晶的結晶化過程。 2 2.如申請專利範圍第2 1項之方法，其中結晶化非晶 質T a 0 N絕緣膜的步驟更包括：以快速熱處理在6 5 0至9 5 0 °C 的溫度範圍，對非晶質絕緣膜退火；而其快速熱處理的時 間在0 . 5至3 0分鐘之間。 2 3.如申請專利範圍第2 1項之方法，其中結晶化非晶 質TaON絕緣膜的步，驟更包括：於一電氣熱處理爐中，在 6 5 0至9 5 0 °C的溫度範圍中，於N\」0、02或化的氣壓下，對非 ，晶質TaON絕緣膜退火1〜30分鐘。 2 4.如申請專利範圍第2 1項之方法，其更包括在一 NH3 或1^2/112的氣壓中，於2 0 0至6 0 0 °(：的溫度間，氮化非晶質 TaON絕緣膜的一個表面的步驟。
    第16頁
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