TW521382B - A method for fabrication of a high capacitance interpoly dielectric - Google Patents
A method for fabrication of a high capacitance interpoly dielectric Download PDFInfo
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- TW521382B TW521382B TW091102007A TW91102007A TW521382B TW 521382 B TW521382 B TW 521382B TW 091102007 A TW091102007 A TW 091102007A TW 91102007 A TW91102007 A TW 91102007A TW 521382 B TW521382 B TW 521382B
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- silicon nitride
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 50
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 30
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012895 dilution Substances 0.000 claims abstract description 4
- 238000010790 dilution Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 230000007547 defect Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000010405 reoxidation reaction Methods 0.000 claims description 5
- 239000004575 stone Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000002309 gasification Methods 0.000 claims description 2
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims 1
- 239000007853 buffer solution Substances 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 235000006408 oxalic acid Nutrition 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052704 radon Inorganic materials 0.000 claims 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 claims 1
- 238000005475 siliconizing Methods 0.000 claims 1
- 239000002131 composite material Substances 0.000 abstract description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 238000007667 floating Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- -1 nitride nitride Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910052778 Plutonium Inorganic materials 0.000 description 1
- 150000001218 Thorium Chemical class 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
- H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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Description
521382 五、發明說明(i) 技術領域 本發明大致係關 定言之,係關於二;二種形成介電複合物之方法,及更特 物之氮化矽薄股^種形成使用作為極間介電體之ΟΝΟ複合 ^研之方法。 背景技藝 技藝中知曉包括 一广 0Ν0介電結構的核門、有二氧化矽/氮化矽/二氧化矽層之 揮發性記憶體譽/ )1電結構。0Ν0介電體被使用於製造非 〜紅灰置諸 衣k井 電容器裝置。 LEPR0M、及FLASH及其他的 如先前技蓺你· 4 列的記憶格:夂° J ’非揮發性記憶體裝置-般包括一李 域、設置於源及沒 ,材表面上之源及汲區 閑⑴。atlng gate)、^^置之广緣層、在絕緣層上之浮置 絕緣介電體上之控制ϋ之一層絕緣介電體及在 :吏浮置開絕緣,並幫助其維持】;ί電荷,及絕緣介電體 f70的二元數據。數據之值係電:何。在浮置閘中儲存-耗或增益會改變數據之值。4浮:t函數,因此,電荷損 汙置閘保持其電荷之能力置閘應可長期保持電荷。 _ 決I為防止電荷指;由:於使浮置間絕緣之 的電Μ ’以當在程式規劃:二介電體必需具有夠高 位此日守,阻止電子_ "矛王中對控制閘施★丄 入至洋置閘中之能量係在浮置卩閘。被消耗於將電荷 函數,且其與介電層之厚 τ人控制聞之間之
W312\2d-c〇de\91-04\91102007.ptd 及介電層之表面積成正比,心提t電容係與介電;: -- N表面積或減小介電層 五、發明說明(2) 之厚度將可使記憶輅之带六 使用記憶格之裝置的密=二=織口裝置所佔據之面積隨 的特徵在於較低的電‘又二小。所產生之較小裝置 減至最小,以使供電* 1 希望使絕緣介電層之厚度 小,及提高裳何進出浮置開用之所需能量減至最 ΟΝΟ介電複合物具有- ^ t ,1ΛΤΛ Λ^ ^ ^ ^ ^ 0Ν0複合物之氣化欲思復_盍虱化矽層之一層二氧化矽。 ^ , 火 層之氧化使氮化矽層變薄,因迚而站 =二f之厚度減至最小。發證給_丄 化應:使乳化物層做得較任—氧化物層薄。 平飞 之美國專利第5,5()4,021號說明一種製 堆弋介電體之方法。此方法包括將厚度大約二 二t單d?層沈積於矽基材之表面上。氮化物層係使 _ 土乾式軋化程序氧化,以形成〇N〇堆疊介電體。 及:ί:丄11電體之厚度的減小,洩漏通過針孔之電荷 及存在於;丨笔體中之其他瑕疵一般將會增加。 —^„rinivasan等人之美國專利第5,882 9 78號提供 一種使适谷器介電體之氮化矽層内之瑕疵減少的方法。此 =法包括在基材上方形成氮化石夕之第-層。氮化石夕具有其 形成有針孔之外表面。利用濕式酸姓刻溶液(例如填酸) 將針孔加寬較佳1包含碎之第二層形成於第—層上及經 加寬的針孔内。將第二層之矽氮化成為氮化矽,以於經加 寬的針孔内形成氮化矽,及形成包括第一及第二層兩者之 \\312\2d-code\91-04\91102007.ptd ^21382 五、發明說明(3) 氮化矽之包含氮化矽之層。 小利= 之〇:介“合物之氮化梦層的厚度並未減 ^ ;1電層愈薄,則電容愈大。 較:二ίί二:“◊為提供-種機械性質優良,諸如 本發明之;m匕;化石夕層之_複合物之製造方法。 石夕層之酬複合物之性f μ之具有薄化氮化 電目的為提供-種使由極間介電體所提供之 本巧:之再一目的為提供一種展現 之極間介電體之製造方法。 屯机及同可罪性 鳘^之概吨 特瑕疲密度之薄氮切層 製造方法。且右i 氧化矽(〇n〇)堆疊複合物的 笔各極間介電結構。減小介電層之厚度將使供南 降低瑕疵密度將可防止電流自被介 :τ n ’及 浮置閘洩漏。 、口構、、、巴、、承之記憶格的 在ΟΝΟ複合物之形成中,將底部或第一二 於基材諸如多晶矽上。冑氮化矽層形“> 成 並利用氧化作用將其㈣。氮化矽薄膜之;::矽層上’ 生暫時二氧化矽屉;5两之只戌 、軋化作用藉由產 氟酸稀釋將此暫;二;化“除耗;利用氫 化㈣再次變薄1第二二氧…= 氮 \\312\2d-code\91-04\91102007.ptd 五、發明說明(4) 將弟二層多晶矽沈積於氮化 人驚奇地,所產生之_介電/,,形成極間介電體。令 有較利用習知方法變薄之且之虱化矽層較薄,且其具 介電體為少的瑕疮,因此二=同f度之氮化石夕層的_ 可將由本發明所形成之介::電容的介電結構。 EPROM及FLASH晶格及其他之;=,=用於諸如EEPROM、 佳模式 包谷器t置的裝置中。 以下之說明提供本發明之0ΝΠ益入&
顯示第一—氧化石夕之0^禝合物的形成方法。圖1A 之各ί方;二陶層14可利用技藝中已知 於Ν 0浐产“ t /、,例如,於〇2環境中之熱成長、 化低溫化學蒸氣沈積(4〇〇。〇及高溫 I :1。’)。高溫化學蒸氣沈積由於其可 順從;化物薄膜而可能為較佳。其亦產生 Γ'^夕晶石夕層52(示於圖2)之表面的氧化物薄 肤。二氧化矽層之厚度範圍可自,例如,數埃至數百埃。 "於底部二氧化梦層14形成之後,將氮化矽層16形成於二 乳化矽層14上。氮化矽層16可利用技藝中已知之各種方法 形成於底部氧化物層14上’其包括,例如,化學蒸氣沈積 及快速熱方法(RTP)。氮化物層可利用,例如,化學蒸氣 沈積作用,使用SiHJL/NH3在6 5 0。-78(rc之間之溫度下 形成。 ,氮化矽層1 6形成後,將氮化矽層氧化。在氮化物層i 6 之氧化過程中熱成長出暫時二氧化石夕層。二氧化石夕層U 係利用技藝中已知的使用H2及〇2氣體在大於>8〇〇它之溫9度
521382 五、發明說明(5) 下熱成長於氮化物層1 6上之高溫蒸氣氧 子中1在02環境或N20環境中之乾式氧化=。在另—例 知曉)使用於二氧化石夕層 < 熱成長1用所 沈積方法將不會產生氮化矽層之薄化。子k孔α積之 氮化石夕層之氧化作用經由以下之反 或使氮化矽變薄及產生二氧化矽:…/耗一 i氮化矽 6H2〇(或302 ) + Si3N4-->3Si02 + 4NHg 可改變,例如,氧化方法之時間長度, 之氮化矽薄膜。 以產生不同厚度 之利=之ΐ化物移除溶液諸如氫氟酸稀釋,將所產生 之一虱化矽之層1 8移除。稀釋可為在,例如, 溶Ϊ以提供良好的程序控制。常用的稀釋:方二 =整定的㈣特性。氧化物移除係根據以
Si02 + 6HF — H2 + Si F6 + 2H20 於將二氧化矽之層18移除,及使氮化矽i6變薄 化矽層1 6再氧化。利用如前所述之高溫蒸氣氧化方法: 上方的氧化物層20成長於氮化物層16上。在另一例子 ,用如前所述之乾式氧化方法於再氧化。氮化矽層1 6之 氧化使氮化矽變薄,並產生上方之二氧化矽2〇之^。二 化矽層2 0之厚度可自,例如,數埃至數百埃。 描繪於圖1 E及圖2中之生成的0N0複合物4〇具有經薄化的 氮化矽層。氮化矽層16經薄化兩次,因此,氮化矽之起始 第9頁 C:\2D-CODE\91-04\91102007.ptd yzu^z 五、發明說明(6) 沈積厚度應夠厚 度。生成氮化矽 埃。 將利用本發明 所描繪之極間介 於上或技藝中已 4 〇之底部二氧化 2 )上。接下來, 層1 6之氧化、氧 用技藝中已知之 40之上方二氧化 層5 2可形成浮置 中之5己憶格之控 本發明之方法 薄氮化石夕層由於 之電荷維持性質 層提供較經以相 之技術薄化至相 明之優點亦包括 之技術薄化至相 見之瑕疵密度為 利用本發明之 的結構完整性, 極間介電體70被 以於再氧化完成之後產生期望的終厚 層16之厚度範圍可自,例如,數埃至數百 =方法形成之ΟΝΟ複合物40使用於製造圖2 :、、、°構。在本發明之方法中,可利用說明 〇之沈積技術或其他技術,將ΟΝΟ複合物 f ί14(圖丨)形成於下方的多晶矽層52(圖 二:二述進行氮化矽層1 6之沈積、氮化矽 ,移除及氮化矽層1 6之再氧化。利 法將第二多晶矽層54沈積於0Ν0複合物 矽層20上,而產生極間介電體70。多晶矽 =閘及多曰曰曰石夕層54可形成使用於各種裝置 ,生具有經薄化氮化矽層之〇Ν〇複合物。 氮化石夕層之厚度的最小化導致0Ν0複合物 =增進而有利。比方說,本發明之氮化矽 二之生成厚度沈積之石夕層或較經使用習知 同生成厚度之氮化矽層為大的電容。本發 較於以相同生成厚度沈積,或經使用習知 同生成厚度之0Ν0複合物之氮化矽層中所 低的氮化矽層瑕疵密度之驚人結果。 方法製得之極間介電體7〇 (圖2)具有高度 而可防止電荷洩漏,及提供高的電容值。 使用於EPROM、EEPR0M、及FLASH裝置及其 C:\2D-CODE\91-04\91102007.ptd 第10頁 521382 五、發明說明(7) 他裝置之製造,而產生可靠的記憶體裝置 元件編號之說明
14 第 一 二 氧 化 矽 層 16 氮 化 矽 層 18 暫 時 二 氧 化 矽 層 20 上 方 的 氧 化 物 層 40 ΟΝΟ複合物 52 多 晶 矽 層 54 第 二 多 晶 矽 層 70 極 間 介 電 體 第11頁 C:\2D-CQDE\91-04\91102007.ptd 521382 圖式簡單說明 圖1 (A)〜(E)概略顯示在利用本發明方法之薄ΟΝΟ介電複 合物之形成過程中之二氧化矽基材。 圖2係具有利用圖1 (Α)〜(Ε)所示之本發明方法形成之 0Ν0介電體之極間介電體的圖式。
C:\2D-CQDE\91-04\91102007.ptd 第12頁
Claims (1)
- 521382 六、申請專利範圍 1·:種形成〇NO介電體之方法,包括·· 將氮化矽層形成於第一二氧化矽層上· 化矽層; 將該暫時的二氧化矽層移除; :虱化矽層再氧化,而於該氮化矽層上形成第二 時的二氣 =氮化石夕層氧化,而於該氮化;層上產生暫 化 矽層 白勺^氣 酸稀釋 5亥酸稀釋包括 該緩衝劑係為 該氧化作用係 该氧化係在大 該氧化作用使 二方法,,該暫時 係3在:Π專利範圍第2項之方法,其中,該氯氣 緩4衝:申請專利範圍第2項之方法,其中 t申請專利範圍第4項之方法,其中 氣化錄。 制6/:申?專利範圍第1項之方法,其中 利用回溫瘵氣氧化方法進行。 7.如申請專利範圍 於800 °C之溫度下進行。 力无/、中 二:申請專利範圍第1項之方法,其中 邊氮化石夕層變薄。 9 ·如申請專利筋圖楚1 矽声且右P夂彻从圍弟項之方法,其中,該生成之氮化 y層具有降低的瑕疵密度。 1 〇 ·如申清專利範圍黛 〜乾㈤弟1項之方法,其中,該〇N〇介電體 第13頁 C:\2D-mDE\91.〇4\91102007.ptd 521382 六、申請專利範圍 係設於極間介電結構内。 11.如申請專利範圍第1 0項之方法,其中,該第一二氧 化石夕層係形成於多晶石夕基材上。 1 2.如申請專利範圍第1 1項之方法,其中,將一層多晶 矽沈積於該第二二氧化矽層上。 1 3.如申請專利範圍第11項之方法,其中,該第一二氧 化石夕層之形成係藉由該多晶石夕基材之氧化作用而進行。 1 4.如申請專利範圍第1項之方法,其中,氮化矽層之形 成係經由將氮化物薄膜沈積於第一二氧化矽層上而進行。 1 5.如申請專利範圍第1 4項之方法,其中,該沈積係利 用化學蒸氣沈積進行。 1 6.如申請專利範圍第1項之方法,其中,該再氧化作用 係利用高溫蒸氣氧化方法進行。 1 7.如申請專利範圍第1項之方法,其中,該氧化作用係 利用乾式氧化方法進行。 1 8.如申請專利範圍第1項之方法,其中,該再氧化作用 係利用乾式氧化方法進行。 1 9. 一種高電容極間介電結構之製造方法,包括: 將第一二氧化矽層形成於多晶矽基材上; 在二氧化矽上形成一層氮化矽; 使該氮化矽層氧化,而於該氮化矽層上形成暫時的二氧 化矽層; 將該暫時的二氧化矽層移除; 使該氮化矽層再氧化,而形成第二二氧化矽層;及\\312\2d-code\91-04\91102007.ptd 第14頁 521382 六、申請專利範圍 將多晶矽層沈積於該第二二氧化矽層上。 2 0.如申請專利範圍第1 9項之方法,其中,該氧化作用 係利用高溫蒸氣氧化方法進行。 2 1.如申請專利範圍第1 9項之方法,其中,該再氧化作 用係利用高溫蒸氣氧化方法進行。C:\2D-CODE\91-04\91102007.ptd 第15頁
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US7115469B1 (en) * | 2001-12-17 | 2006-10-03 | Spansion, Llc | Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process |
CN102097312B (zh) * | 2010-11-16 | 2012-08-29 | 无锡中微晶园电子有限公司 | 一种ono电容结构的生长工艺 |
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Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5244825A (en) | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
IT1191755B (it) | 1986-04-29 | 1988-03-23 | Sgs Microelettronica Spa | Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido |
US5013692A (en) * | 1988-12-08 | 1991-05-07 | Sharp Kabushiki Kaisha | Process for preparing a silicon nitride insulating film for semiconductor memory device |
JPH04144278A (ja) | 1990-10-05 | 1992-05-18 | Mitsubishi Electric Corp | 半導体記憶装置およびその製造方法 |
US5241198A (en) | 1990-11-26 | 1993-08-31 | Matsushita Electronics Corporation | Charge-coupled device and solid-state imaging device |
US5120670A (en) * | 1991-04-18 | 1992-06-09 | National Semiconductor Corporation | Thermal process for implementing the planarization inherent to stacked etch in virtual ground EPROM memories |
US5324675A (en) | 1992-03-31 | 1994-06-28 | Kawasaki Steel Corporation | Method of producing semiconductor devices of a MONOS type |
TW236710B (zh) | 1994-04-08 | 1994-12-21 | ||
US5478765A (en) | 1994-05-04 | 1995-12-26 | Regents Of The University Of Texas System | Method of making an ultra thin dielectric for electronic devices |
US5619052A (en) | 1994-09-29 | 1997-04-08 | Macronix International Co., Ltd. | Interpoly dielectric structure in EEPROM device |
EP0751560B1 (en) * | 1995-06-30 | 2002-11-27 | STMicroelectronics S.r.l. | Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC |
US5731235A (en) | 1996-10-30 | 1998-03-24 | Micron Technology, Inc. | Methods of forming a silicon nitrite film, a capacitor dielectric layer and a capacitor |
US5981404A (en) | 1996-11-22 | 1999-11-09 | United Microelectronics Corp. | Multilayer ONO structure |
US5969381A (en) * | 1997-02-26 | 1999-10-19 | Nec Corporation | Semiconductor device with unbreakable testing elements for evaluating components and process of fabrication thereof |
US5872376A (en) | 1997-03-06 | 1999-02-16 | Advanced Micro Devices, Inc. | Oxide formation technique using thin film silicon deposition |
US6297096B1 (en) * | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
US6207587B1 (en) * | 1997-06-24 | 2001-03-27 | Micron Technology, Inc. | Method for forming a dielectric |
US5998253A (en) | 1997-09-29 | 1999-12-07 | Siemens Aktiengesellschaft | Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell |
US6117763A (en) | 1997-09-29 | 2000-09-12 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water |
JP3609258B2 (ja) * | 1998-05-19 | 2005-01-12 | 日本電産株式会社 | モータ |
US6037235A (en) | 1998-09-14 | 2000-03-14 | Applied Materials, Inc. | Hydrogen anneal for curing defects of silicon/nitride interfaces of semiconductor devices |
US6096604A (en) * | 1999-08-04 | 2000-08-01 | Chartered Semiconductor Manufacturing Ltd | Production of reversed flash memory device |
US6255172B1 (en) * | 2000-05-10 | 2001-07-03 | United Microelectronics Corp. | Electrically erasable non-volatile memory |
US6395654B1 (en) * | 2000-08-25 | 2002-05-28 | Advanced Micro Devices, Inc. | Method of forming ONO flash memory devices using rapid thermal oxidation |
US6271090B1 (en) * | 2000-12-22 | 2001-08-07 | Macronix International Co., Ltd. | Method for manufacturing flash memory device with dual floating gates and two bits per cell |
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JP2004534385A (ja) | 2004-11-11 |
US20030045123A1 (en) | 2003-03-06 |
NO20034362D0 (no) | 2003-09-29 |
KR20030088471A (ko) | 2003-11-19 |
EP1374292A2 (en) | 2004-01-02 |
US6709990B2 (en) | 2004-03-23 |
WO2002080235A3 (en) | 2003-03-20 |
AU2002243516A1 (en) | 2002-10-15 |
CA2435680A1 (en) | 2002-10-10 |
CN1500289A (zh) | 2004-05-26 |
WO2002080235A2 (en) | 2002-10-10 |
US20020142570A1 (en) | 2002-10-03 |
CN1254850C (zh) | 2006-05-03 |
NO20034362L (no) | 2003-11-28 |
US6495475B2 (en) | 2002-12-17 |
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