TW520548B - Shallow trench isolation filled with thermal oxide - Google Patents
Shallow trench isolation filled with thermal oxide Download PDFInfo
- Publication number
- TW520548B TW520548B TW088107569A TW88107569A TW520548B TW 520548 B TW520548 B TW 520548B TW 088107569 A TW088107569 A TW 088107569A TW 88107569 A TW88107569 A TW 88107569A TW 520548 B TW520548 B TW 520548B
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- trench
- shaped
- isolation
- region
- silicon
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Description
520548
[技術領域] 本發明係關於積 ^ ^ (FOX) ^ ^ t ^ ^ % 〇 體電路基片上形成淺溝隔離(STI)區之製丄技術如於在積 L發明之背景] 製造半導體裝置之方法所包含之 j介電材料之隔離區,…材料提供確保形:電;y 包路5又什之適當功能的所須保護。此方法包括矽域 化作用(_。此方法一般開始是在二氧切層 ,層)上沉積氮化石夕層厚度達U5㈣至範圍。j 疋用低壓化學氣相沉積(LPCVD)技術來沉積氮化 ^ ,包括了任何適當之在卫業上已知之可買到的 材料後 光阻罩層沉積在氮切層上。然後在光阻罩層上繪^^ 形成隔離渠溝。用蝕刻方式’將隔離渠溝區 氧 化石夕層和氮切層和光阻層之m說來 成渠溝區,基片之上表面經小量地蝕刻,大約為…" 0.25 。由使用四乙基原矽酸脂(TE〇s)作為沉積二 矽之源材,而沉積二氧化矽之厚墊,形成在隔離區上 化層。氧化墊之厚度,亦稱之為場氧化層(F〇x)墊 广 圍是在1.2#m至1.5/zm之間。此方法更進一步包括磨 成之隔離墊至表面水準,而厚度大致同高於氮化矽 / 用濕蝕刻移除接續形成之氮化矽氧化墊和二氧化矽芦=: 以露出用來形成各種的積體.路組件之活動區。濕^ 般是先用熱磷酸蝕刻氮化矽層,然後將基片浸泡在氫氟酸
Claims (1)
- 520548ft 案號 88107569 六、1. 修正2. 3. 4· 申請專利範圍 一種半導體裝置,該裝置包括: 半導體基片構件; 至少一對形成在該半導體構件上之間隔開之第一 介電材料墊,在該間隔開之介電材料之間之區域劃出 半導體基片區用來形成隔離渠溝區; 傾斜之第二介電材料製成的間隔器構件,鄰接各 該間隔開之第一介電材料墊而形成;和 V形隔離渠溝區,製成該半導體基片構件内,該V 形隔離渠溝區製成在該等間隔開之第一介電墊和個別 之鄰接間隔器構件之間,該V形隔離渠溝區包括具有與 該等第一介電墊分離一段距離之上端部之V形渠溝構 造,該分離之一段距離依照該間隔器構件之材料厚度 而改變,和下端部延伸一預定之距離進入該半導體基 片中。 如申請專利範圍第1項所述之半導體裝置,其中: 該至少一對間隔開之第一介電材料墊包括由氮化 砍製成,和 該傾斜的第二介電材料之間隔器構件包括藉由熱 氧化物製造方法而製成之二氧化矽所製成。 如申請專利範圍第1項所述之半導體裝置,其中: 該上端部包括開口,測量為0. 2 // hi,和下端部測 量實質為小於〇. 2 // m。 如申請專利範圍第3項所述之半導體裝置,其中·· 該半導體基片包括碎材料,和91531.ptc 第1頁 2002.09.21.013 520548 案號 88107569 Λ 六 5· 6 · 7 、申請專利範圍 ^^^一 該裝置尚包括在該ν渠溝區之實質部份 由熱氧 化物方法而生長的第一二氧化矽材料。 如申請專利範圍第4項所述之半導體裝置,其中· 該裝置尚包括第二二氧化矽材料,沉 形渠 溝區之該上端部。 ^ i ^ 一種半導體裝置,該裝置包括·· 半導體基片構件; 至少一對形成在該半導體構件上之間隔開之氮化 石夕塾’在該間隔開之氮化石夕墊之間之區域劃出半導體 基片區用來形成隔離渠溝區; 傾斜之氧化矽間隔器構件,鄰接各該間隔氮 化矽墊而形成; v形隔離渠溝區,製成該半導體基片構件内,該ν 形隔離渠溝區製成在該等間隔開之氮化矽墊和個別鄰 接之氧化間隔器構件之間,該V形隔離渠溝區包括具 與該等氮化矽墊分離一段距離之上端部之V形渠溝^ 造,該分離之一段距離依照該間隔器構件之材料厚产 而改變,和下端部延伸一預定之距離進入該 二= 片中;和 子m暴 渠溝隔離材料,包括二氧化矽,生長在該V 區之實質部份内。 7未屢 如申請專利範圍第6項所述之半導體裝置,其中·· 該上端部包括開口,測量為0· 2从m,而下端· 量為實質小於0.2"m;和 h 91531.ptc 第2頁 20〇2.09.21.014 520548 六 1 號 88107569 — Μ >0 η —修正 8· 9· 、申請專利範圍 該渠溝隔離材料從相對側壁構造 形渠溝構造。 並填埋該V 如申請專利範圍第6項所述之半導體裝置, 該裝置尚包括第二二氧化矽材料,由其與中+ : 積方法而沉積在該V形渠溝區之該上端部 予翁氧沉 一種產製至少一個淺溝隔離之方法, 各步驟: ’包括下列 (a) 提供製有阻障氧化層之半導 (b) 在該阻障氧化層上形成 ^ f件·, 電介質墊; 夕對間隔開之第— (c) 在該第一電介質墊上和於該第_ 區域的該阻障氧化層上形成二氧化矽層 介質墊之間的該等區域包括形成該至& 之區域; (d) 在該二氧化矽層上形成多晶矽層, 於刻劃形成該至少一個淺溝隔離之該區域厂夕晶矽層 渠溝並提供第一緩衝區域,該第一緩衝區域$第 物和鄰接該至少一對間隔開之第一電介匕括氧化 材料; 势之多晶矽 (e) 在形成該至少一個淺溝隔離之該區 矽蝕刻處理而形成較寬的第二U形渠溝,該L由多晶 溝具有傾斜的侧壁,此侧壁形成第二緩衝材〜U形渠 第二緩衝材料區包括氧化物和多晶矽材料2區,誘 和 新尖量· 電介質墊之間 ’該各第一電 -個淺溝隔離520548 _案號88107569_4 (年 3月 曰 修正_ 六、申請專利範圍 (〇形成V形隔離渠溝區進入該半導體基片構件 内,該V形隔離渠溝區由蝕刻包括該第二U形渠溝之側 壁之多晶矽材料而製成,由蝕穿該阻障氧化層並進入 該半導體基片達一預令深度。 1 0 .如申請專利範圍第9項所述之產製淺溝隔離之方法,其 中·· 該步驟(f )包括形成具有該氮化矽墊之鄰接相對之 氧化材料之改變厚度的相對隔離件,該等隔離件包括 該V形隔離渠溝區之上端側壁部。 1 1.如申請專利範圍第9項所述之產製淺溝隔離之方法,該 方法尚包括下列步驟: 生長渠溝隔離材料在該V形渠溝區之實質部份内, 該渠溝隔離材料包括二氧化矽。 1 2.如申請專利範圍第1 1項所述之產製淺溝隔離之方法, 該方法尚包括下列步驟: 由化學蒸氣沉積方法,沉積二氧化矽材料於該V形 渠溝區之上端部。 1 3. —種產製至少一個淺溝隔離之方法,該方法包括下列 各步驟: (a) 提供製有阻障氧化層之半導體基片構件; (b) 在該阻障氧化層上形成至少一對間隔開之第一 電介質墊; (c) 在該第一電介質墊上和於該第一電介質墊之間 區域的該阻障氧化層上形成二氧化矽層,該各第一電91531.ptc 第4頁 2002.09.21.016 520548 _案號88107569_年9月,曰 修正_ 六、申請專利範圍 介質墊之該等區域包括形成該至少一個淺溝隔離之區 域; (d )在該二氧化矽層上形成多晶矽層,該多晶矽層 於刻劃形成該至少一個淺溝隔離之該區域形成第一 U形 渠溝並提供第一緩衝區域,該第一緩衝區域包括氧化 物和鄰接該至少一對間隔開之第一電介質墊之多晶矽 材料, (e)在形成該至少一個淺溝隔離之該區域,由多晶 矽蝕刻處理而形成較寬的第二U形渠溝,該第二U形渠 溝具有傾斜的側壁,此側壁形成第二緩衝材料區,該 第二緩衝材料區包括氧化物和多晶矽材料之漸尖量; (f )形成V形隔離渠溝區進入該半導體基片構件 内,該V形隔離渠溝區由蝕刻包括該第二U形渠溝之側 壁之多晶矽材料而製成,由蝕穿該阻障氧化層並進入 該半導體基片達一預令深度;和 (g)生長渠溝隔離材料,包括生長在該V形隔離渠 溝區之實質部分内之第一熱氧化物。 1 4.如申請專利範圍第11項所述之產製淺溝隔離之方法, 該方法尚包括下列步驟: 由化學蒸氣沉積方法,沉積二氧化矽材料於該V形 渠溝區之上端部。91531.ptc 2002. 09.21.017 第5頁
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/082,607 US6232646B1 (en) | 1998-05-20 | 1998-05-20 | Shallow trench isolation filled with thermal oxide |
Publications (1)
Publication Number | Publication Date |
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TW520548B true TW520548B (en) | 2003-02-11 |
Family
ID=22172223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW088107569A TW520548B (en) | 1998-05-20 | 1999-05-11 | Shallow trench isolation filled with thermal oxide |
Country Status (4)
Country | Link |
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US (1) | US6232646B1 (zh) |
JP (1) | JP3703069B2 (zh) |
KR (1) | KR100675962B1 (zh) |
TW (1) | TW520548B (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323104B1 (en) * | 2000-03-01 | 2001-11-27 | Micron Technology, Inc. | Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry |
KR100421046B1 (ko) * | 2001-07-13 | 2004-03-04 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
KR100458767B1 (ko) * | 2002-07-04 | 2004-12-03 | 주식회사 하이닉스반도체 | 반도체 소자의 소자 분리막 형성 방법 |
US6727150B2 (en) | 2002-07-26 | 2004-04-27 | Micron Technology, Inc. | Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers |
US7381615B2 (en) * | 2004-11-23 | 2008-06-03 | Sandisk Corporation | Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices |
US7416956B2 (en) * | 2004-11-23 | 2008-08-26 | Sandisk Corporation | Self-aligned trench filling for narrow gap isolation regions |
US20060240660A1 (en) * | 2005-04-20 | 2006-10-26 | Jin-Sheng Yang | Semiconductor stucture and method of manufacturing the same |
US20080157169A1 (en) * | 2006-12-28 | 2008-07-03 | Yuan Jack H | Shield plates for reduced field coupling in nonvolatile memory |
US20080160680A1 (en) * | 2006-12-28 | 2008-07-03 | Yuan Jack H | Methods of fabricating shield plates for reduced field coupling in nonvolatile memory |
CN102117762B (zh) * | 2010-01-05 | 2012-11-07 | 上海华虹Nec电子有限公司 | 浅沟隔离槽 |
CN110416089B (zh) * | 2019-07-31 | 2023-02-03 | 上海华虹宏力半导体制造有限公司 | 一种ldmos的制备方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
JPH07122627A (ja) * | 1993-10-22 | 1995-05-12 | Sony Corp | 半導体装置の製造方法 |
US5643822A (en) * | 1995-01-10 | 1997-07-01 | International Business Machines Corporation | Method for forming trench-isolated FET devices |
JPH08316224A (ja) * | 1995-05-18 | 1996-11-29 | Sony Corp | 素子分離法及び半導体装置の製造方法 |
US5679599A (en) * | 1995-06-22 | 1997-10-21 | Advanced Micro Devices, Inc. | Isolation using self-aligned trench formation and conventional LOCOS |
US5643823A (en) * | 1995-09-21 | 1997-07-01 | Siemens Aktiengesellschaft | Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures |
US6064104A (en) * | 1996-01-31 | 2000-05-16 | Advanced Micro Devices, Inc. | Trench isolation structures with oxidized silicon regions and method for making the same |
KR980012278A (ko) * | 1996-07-12 | 1998-04-30 | 원본미기재 | 반도체 소자분리공정 |
US5910018A (en) * | 1997-02-24 | 1999-06-08 | Winbond Electronics Corporation | Trench edge rounding method and structure for trench isolation |
US5895253A (en) * | 1997-08-22 | 1999-04-20 | Micron Technology, Inc. | Trench isolation for CMOS devices |
US5945724A (en) * | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
-
1998
- 1998-05-20 US US09/082,607 patent/US6232646B1/en not_active Expired - Lifetime
-
1999
- 1999-05-11 TW TW088107569A patent/TW520548B/zh not_active IP Right Cessation
- 1999-05-20 JP JP17881199A patent/JP3703069B2/ja not_active Expired - Fee Related
- 1999-05-20 KR KR1019990018256A patent/KR100675962B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR19990088449A (ko) | 1999-12-27 |
KR100675962B1 (ko) | 2007-02-01 |
US6232646B1 (en) | 2001-05-15 |
JP3703069B2 (ja) | 2005-10-05 |
JP2000031262A (ja) | 2000-01-28 |
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