TW516125B - Semiconductor device and apparatus for manufacturing semiconductor device - Google Patents
Semiconductor device and apparatus for manufacturing semiconductor device Download PDFInfo
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- TW516125B TW516125B TW090106101A TW90106101A TW516125B TW 516125 B TW516125 B TW 516125B TW 090106101 A TW090106101 A TW 090106101A TW 90106101 A TW90106101 A TW 90106101A TW 516125 B TW516125 B TW 516125B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 89
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 45
- 239000002994 raw material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims abstract description 15
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 105
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 20
- 239000001301 oxygen Substances 0.000 claims description 20
- 229910052760 oxygen Inorganic materials 0.000 claims description 20
- 239000007788 liquid Substances 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 16
- UUGMKRAJZZIRRC-UHFFFAOYSA-N 5,5-diethylcyclopenta-1,3-diene ruthenium Chemical compound C(C)C1(C=CC=C1)CC.[Ru] UUGMKRAJZZIRRC-UHFFFAOYSA-N 0.000 claims description 10
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 claims 1
- 230000002349 favourable effect Effects 0.000 claims 1
- QRSFFHRCBYCWBS-UHFFFAOYSA-N [O].[O] Chemical compound [O].[O] QRSFFHRCBYCWBS-UHFFFAOYSA-N 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000002079 cooperative effect Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- SOQXOILVAMUTKS-UHFFFAOYSA-N [Ru].C(C)C1=CC=CC1 Chemical compound [Ru].C(C)C1=CC=CC1 SOQXOILVAMUTKS-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
- C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
516125 Α7 ___ Β7 五、發明說明(5
於初期成膜工程之較佳成膜條件下,亦即,作爲不發 生堆積延遲之成膜條件,係例示有溫度3 0 〇〜3 5 0 °C ,最佳爲 315°C,壓力 1333Pa 〜3999Pa ( 1〇T 〇 r r〜3 Ο T 〇 r· r ),釕液體原料流量 〇· 01〜〇· lccm,含氧氣流量50〇〜3Ό00 s c c m,成膜時間3〇〜1 8 0秒,更佳爲3 0〜 1 2 0秒。又,將於初期成膜工程之上述成膜條件,因應 其目的做適當決定時,都可成膜釕膜或氧化釕膜之任一。
於正成膜工程之較佳成膜條件下,亦即,作爲被覆高 低差性良好之成膜條件,係例示有溫度2 9 0〜3 3 0 °C ,壓力67Pa〜1333Pa (〇.5Torr〜1〇 T 〇 r r ),釕液體原料流量0 · 0 1〜0 . 1 c c m, 含氧氣流量5〜20〇s c cm,成膜時間60〜380 秒。又,將於正成膜工程之上述成膜條件,因應其目的做 適當決定時,都可成膜釕膜或氧化釕膜之任一。 以上所說明之初期成膜工程及正成膜工程之時間圖表 與製程(溫度、壓力、氧氣流量、釕液體原料流量),表 示於第7圖。 按,設定爲上述初期成膜工程及正成膜工程之成膜條 件,係正成膜工程較初期成膜工程者被覆高低差性變成良 好,又,初期成膜工程較正成膜條件者之溫度變高’或壓 力能夠變高,或對於釕液體原料流量之含氧氣流量之比變 大,爲從防止於初期成膜工程之堆積延遲,於提升正成膜 工程之被覆高低差性上之觀點較佳。又,初期成膜工程與 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請 先 閱 讀 背 δ 之 注 意 再 填 · 寫裝 頁 訂 經濟部智慧財產局員工消費合作社印製 -8- 516125 經濟部智慧財產局員工消費合作社印製 A7 B7__五、發明說明(6 ) 正成膜工程,係於同一反應室內連續地進行,在成本上, 亦即生產量上,設備費等之點來說爲較佳。 在初期成膜工程所設之膜厚,係例如5〜1 5 n m, 在正成膜工程所設之膜厚,係例如1 0〜5 〇 n m較佳。 又,其他條件,係可將以往公知之熱V C D法之條件 可做適當設定。 > 於本發明在釕膜或氧化釕膜下視其需要所設之質地膜 ,雖然並非特別加以限制,但是例如可舉出S i〇2、 Si3N4、TiN、Ti〇2、WN、Ta2〇5、 TiAIN、BST、聚矽等。 本發明所使用之釕液體原料,係因應用途從種種種類 可做適當選擇,但是雙乙基環戊二烯釕爲代表性者。又, 在本發明所使用之含氧氣,係因應用途雖然可從種種種類 做適當選擇,但是例如氧氣(〇2 )、臭氧(〇3 )爲代表 性者。 【實施例】 第1圖〜第4圖係表示初期成膜工程之成膜條件與正 成膜工程後所得到之釕膜之膜電阻之關係。於此,膜電阻 與膜厚係具有反比例之關係,膜電阻愈小,膜厚將變厚, 並且不容易發生堆積延遲。 第1圖係用來說明初期成膜工程之溫度,與正成膜工 程後所得到之釕膜之膜電阻R s ( Ω / □)關係之圖。於 第1圖於初期成膜工程之溫度以外之成膜工程’係定爲壓 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱1 " (請先閱讀背面之注意leFW再填寫本頁) 丨裝 ·. ¾ 經濟部智慧財產局員工消費合作社印製 516125 A7 B7_____ 五、發明說明(7 ) 力Pa252Pa(19T〇rr),釕液體原料(雙乙 基環戊二烯釕)流量〇 · 〇6 6 c cm,含氧氣(氧)流 量1 500 s c cm,成膜時間1 80秒,又作爲成膜之 質地使用絕緣膜之S i 0 2。於初期成膜工程所得到之膜厚 係設定爲5〜1 5 n m。於正成膜工程之成膜工程·,係設 定爲溫度3〇0°C ,壓力67Pa.(〇· 5T〇r r), 釕液體原料(雙乙基環戊二烯釕)流量0 . 0 6 6 c c m ,含氧氣(氧)流量1 6 0 s c c m,成膜時間2 4 0秒 。於初期成膜工程所得到之膜厚係設定爲2 0〜3 0 n m (實驗係就複數之膜厚進行)。 從第1圖若設定初期成膜工程較正成膜工程條件者溫 度爲高之成膜條件時,曉得因膜電阻變小所以可改善堆積 延遲。 第2圖係用來說明初期成膜工程與壓力,與正成膜工 程後所得到之釕膜之膜電阻膜電阻R s ( Ω /□)關係之 圖。於第2圖於初期成膜工程之壓力以外之成膜工程,係 定爲溫度3 0 0 °C,釕液體原料(雙乙基環戊二烯釕)流 量0 · 066ccm,含氧氣(氧)流量 1 5 00 s c cm,成膜時間1 80秒,又作爲成膜之質 地使用絕緣膜之S i 0 2。於初期成膜工程所得到之膜厚係 設定爲5〜1 5 nm。於正成膜工程之成膜工程,係設定 爲溫度30〇°C,壓力67Pa(〇.5T〇rr),釕 液體原料(雙乙基環戊二烯釕)流量0 · 06 6 c cm, 含氧氣(氧)流量1 6 0 s c c m,成膜時間2 4 0秒。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ~\〇1 (請先閱讀背面之注意事項再填寫本頁) 丨裝 ¾. 516125 A7 B7 五、發明說明(8 ) (請先閱讀背面之注意S再填寫本頁) 於正成膜工程所得到之膜厚係設定爲2 0〜3 0 n m (實 驗係就複數之膜厚進行)。於第2圖於初期成膜工程之壓 力以外之成膜工程,係定爲溫度3 0 0 °C,釕液體原料( 雙乙基環戊二烯釕)流量0 · 0 6 6 c c m,含氧氣(氧 )流量1 5 0 0 s c c m,成膜時間1 8 〇秒,又‘作爲成 膜之質地使用絕緣膜S i〇2。於初.成膜工程所得到之膜 厚係設定爲5〜1 5 nm。於正成膜工程之成膜工程,係 設定爲溫度300 °C,壓力67Pa (〇 · 5T〇rr) ,釕液體原料(雙乙基環戊二烯釕)流量 〇·〇66ccm,含氧氣(氧)流量16〇sccm, 成膜時間2 4 0秒。於正成膜工程所得到之膜厚係設定爲 2 0〜3 0 nm (實驗係就複數之膜厚進行)。 第3圖係用來說明初期成膜工程之含氧氣(氧)流量 ,與正成膜工程後所得到釕膜之膜電阻膜電阻R s ( Ω / □)關係之圖。於第3圖係於初期成膜工程之氧氣流量以 外之成膜條件,係定爲溫度3 0 0 °C,壓力2 5 2 P a ( 1 9 T 〇 r r ),釕液體原料(雙乙基環戊二烯釕)流量 經濟部智慧財產局員工消費合作社印製 0 · 0 6 6 c cm,成膜時間1 8 0秒,又作爲成膜之質 地使用絕緣膜S i〇2。於正成膜工程之成膜條件,係所得 到之膜厚係設定爲5〜1 5 n m。於正成膜工程之成膜工 程,係設定爲溫度3 0 0 °C,壓力6 7 P a ( 〇· 5 T 〇 r r ),釕液體原料(雙乙基環戊二烯釕)流 量〇·〇66ccm,含有氧氣(氧)流量 1 6 0 s c c m,成膜時間爲2 4 0秒,在正成膜工程所 -11 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 516125 Α7 Β7 五、發明說明(ίο ) 又,從第3圖,第4圖,若將成膜條件設定爲初期成 膜工程較正成膜工程者,對於釕原料流量之含氧氣(氧) 流量之比爲大時,因膜電阻會變小,曉得可改善堆積延遲 〇 按,於第1圖〜第4圖之任一情形,於成膜工程所形 成之釕膜之被覆高低差性係於寬高比(aspect raUo ) 4得 到9 0 %以上,又表面波度(morphology )也變成良好。 第5圖係用來說明於本發明可利用之熱V C D裝置一 例之圖。於第5圖基板1係使用機器手臂(未圖示),通 過閘閥2設置於具有加熱器之基板架3上。加熱器係使用 升降裝置上升到既定位置,一定時間加熱基板1 ,將反應 室4內之壓力安定於所需値之後,在基板上將欲成膜之釕 膜或氧化釕膜所用之原料氣體從氣體供給口 5導入,而從 氣體排氣口 6排氣,使用熱C VD法進行初期成膜工程與 正成膜工程。按,於各工程之溫度、壓力、氧氣流量、釕 液體原料流量之控制,係分別使用溫度控制裝置8、壓力 控制裝置9、氧氣流量控制裝置1 0、釕液體原料流量控 制裝置1 1控制成上述所需之成膜條件。完成正成膜工程 之後,以機器手臂運出基板1外。 第6圖係表示包含使用本發明之製造方法所形成之釕 膜或氧化釕膜之D R A Μ —部之剖面圖。 如第6圖所示,在矽基板6 1表面形成有分離形成多 數電晶體形成領域之場氧化膜6 2 ,在矽基板6 1表面部 形成源極電極6 3、汲極電極6 4,在源極電極6 3與汲
• > V 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 -13- 516125 Α7 _______ Β7 五、發明說明(12 ) 膜,藉進行釕膜之圖案形成,以形成電容下部電極7 2。 接著’在電容下部電極7 2上形成由T a 2〇5所成之電容 絕緣膜7 3 ,在電容絕緣膜7 3上形成釕或由T i N等所 成之電容上部電極7 4。 【發明效果】 . 若依據本發明,就可提供可製造優於被覆高低差性, 並且以低成本量產性良好之半導體裝置之方法及裝置。 圖式之簡單說明 第1圖係用來說明初期成膜工程之溫度,·與在正成膜 工程後所得到之膜電阻R s ( Ω /□)關係之圖。 第2圖係用來說明初期成膜工程之壓力,與在正成膜 工程後所得到之膜電阻R s ( Ω /□)關係之圖。 第3圖係用來說明初期成膜工程之氧氣流量,與在正 成膜工程後所得到之膜電阻R s ( Ω /□)關係之圖。 第4圖係用來說明初期成膜工程之釕液體原料(雙乙 基環戊二烯釕)流量,與在正成膜工程後所得到之膜電阻 R s ( Ω /□)關係之圖。 第5圖係用來說明本發明可利用之熱C V D法裝置一 例之圖。 第6圖係表示使用本發明之製造方法所形成包含釕膜 或氧化釕膜之D R A Μ —部之剖面圖。 第7圖係表示於初期成膜工程與正成膜工程之製程條 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) (請先閱讀背面之注意再填寫本頁) i裝 · 經濟部智慧財產局員工消費合作社印製 -15- 516125 A7 B7 五、發明說明(13 ) 件之時間圖表。 【符號之說明】 1 基板,2 閘閥,3 基板架,4 反應室,5 氣體供給口,6 氣體排氣口。 ‘ (請先閱讀背面之注意再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) .^6 -
Claims (1)
- 5161辟 A8 B8 C8 D8 六、申請專利範圍 第90 1 06 1 0 1號專利申請案 中文申請專利範圍修正本 民國9 1年9百26日修正 1.一種半導體裝置之製造方法,其特徵爲:使用氣 化釕液體原料之氣體與含氧氣體,在基板上成膜釕膜或氧 化釕膜時, 上述成膜之工程,係具有: 初期成膜工程;及 正成膜工程;該正成膜工程係成膜成與上述初期成膜 工程不同成膜條件下形成比上述初期成膜工程之膜更厚。 2 ·如申請專利範圍第1項之半導體裝置之製造方法 ,其中上述初期成膜工程與正成膜工程,係使用熱c V D 法,在同一反應室內連續進行。 3 ·如申請專利範圍第1項之半導體裝置之製造方法· ,其中在正成膜工程比初期成膜工程的被覆高低差性還要 良好的條件下進行成膜。 4 ·如申請專利範圍第1項之半導體裝置之製造方法 ,其中以初期成膜工程比正成膜工程的成膜速度還要快之 方式來進行成膜。 5 ·如申請專利範圍第1項之半導體裝置之製造方$ ,其中以初期工程比正成膜工程的成膜溫度還要高,或$ 膜壓力還要高之方式來進行成膜。 6 ·如申請專利範圍第1項之半導體裝置之製冑$ & ,其中以初期成膜工程比正成膜工程之對釕原料流量的# 本紙張尺度適用中國國冢標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 、π 經濟部智慧財產局員工消費合作社印製A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 、申請專利範圍 氧氣體流量的比還要大之方式來進行成膜。 7 .如申請專利範圍第1項之半導體裝置之 ,其中在初期成膜工程,係以溫度3 0 0〜3 5力6 6 7〜3 9 9 9P a之範圍進行成膜。 8 ·如申請專利範圍第1項之半導體裝置之 ’其中上述釕液體原料係雙乙基環戊二烯釕( cuclo pentadine ginule ruthenium ) ) ° 9·一種半導體製造裝置,其特徵爲具有: 可收容基板的一個反應室;及 氣體供給口;該氣體供給口係對於上述基板 釕或氧化釕膜所用之原料氣體供給於上述反應室; 氣體排氣口;該氣體排氣口係將上述原料氣 反應室排氣; 將上述原料氣體從上述氣體供給口向基板供 熱C V D法在上述基板上成膜釕膜或氧化釕膜, 上述釕膜或氧化釕膜作爲下層,在與上述釕或氧 成膜條件不同的成膜條件下,利用熱C V D法來 述釕膜或氧化釕膜更厚的膜厚之釕膜或氧化釕膜。 製造方法 .〇 t及壓 製造方法 bis ethyl 上將成膜 及 體從上述 給,利用· 接著,以 化釕膜的 形成比上 (請先聞讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準(CNS ) Α4規格(21〇Χ297公釐) -2-
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JPH0794680A (ja) | 1993-09-22 | 1995-04-07 | Fujitsu Ltd | 半導体装置の製造方法 |
KR0172772B1 (ko) * | 1995-05-17 | 1999-03-30 | 김주용 | 반도체 장치의 확산장벽용 산화루테늄막 형성 방법 |
JP3676004B2 (ja) * | 1996-11-28 | 2005-07-27 | 富士通株式会社 | 酸化ルテニウム膜の形成方法および半導体装置の製造方法 |
JP3905977B2 (ja) * | 1998-05-22 | 2007-04-18 | 株式会社東芝 | 半導体装置の製造方法 |
JPH11354751A (ja) * | 1998-06-04 | 1999-12-24 | Toshiba Corp | 半導体装置,半導体装置の製造方法および半導体製造装置 |
US6180164B1 (en) * | 1998-10-26 | 2001-01-30 | Delco Electronics Corporation | Method of forming ruthenium-based thick-film resistors |
KR100389913B1 (ko) * | 1999-12-23 | 2003-07-04 | 삼성전자주식회사 | 공정조건을 변화시키면서 화학기상 증착법으로 루테늄막을형성하는 방법 및 그에 의해 형성된 루테늄막 |
JP3976462B2 (ja) * | 2000-01-26 | 2007-09-19 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US6380080B2 (en) * | 2000-03-08 | 2002-04-30 | Micron Technology, Inc. | Methods for preparing ruthenium metal films |
-
2001
- 2001-01-31 JP JP2001024360A patent/JP4034518B2/ja not_active Expired - Lifetime
- 2001-03-08 KR KR1020010011966A patent/KR100769513B1/ko active IP Right Grant
- 2001-03-15 TW TW090106101A patent/TW516125B/zh not_active IP Right Cessation
- 2001-03-29 US US09/819,653 patent/US6548404B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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JP2001345285A (ja) | 2001-12-14 |
KR20010094961A (ko) | 2001-11-03 |
US6548404B2 (en) | 2003-04-15 |
JP4034518B2 (ja) | 2008-01-16 |
KR100769513B1 (ko) | 2007-10-23 |
US20010026963A1 (en) | 2001-10-04 |
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