TW508784B - Method of manufacturing a semiconductor device and a semiconductor device - Google Patents

Method of manufacturing a semiconductor device and a semiconductor device Download PDF

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Publication number
TW508784B
TW508784B TW090108015A TW90108015A TW508784B TW 508784 B TW508784 B TW 508784B TW 090108015 A TW090108015 A TW 090108015A TW 90108015 A TW90108015 A TW 90108015A TW 508784 B TW508784 B TW 508784B
Authority
TW
Taiwan
Prior art keywords
dielectric layer
hard mask
layer
film
pattern
Prior art date
Application number
TW090108015A
Other languages
English (en)
Chinese (zh)
Inventor
Kazusato Hara
Keisuke Funatsu
Toshinori Imai
Junji Noguch
Naohumi Ohashi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW508784B publication Critical patent/TW508784B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
TW090108015A 2000-04-25 2001-04-03 Method of manufacturing a semiconductor device and a semiconductor device TW508784B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000123839A JP4057762B2 (ja) 2000-04-25 2000-04-25 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW508784B true TW508784B (en) 2002-11-01

Family

ID=18634066

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090108015A TW508784B (en) 2000-04-25 2001-04-03 Method of manufacturing a semiconductor device and a semiconductor device

Country Status (4)

Country Link
US (2) US6495466B2 (https=)
JP (1) JP4057762B2 (https=)
KR (1) KR100783868B1 (https=)
TW (1) TW508784B (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996653A (zh) * 2014-05-09 2014-08-20 上海大学 Tft深接触孔制造方法
CN103996618A (zh) * 2014-05-09 2014-08-20 上海大学 Tft电极引线制造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010030169A1 (en) * 2000-04-13 2001-10-18 Hideo Kitagawa Method of etching organic film and method of producing element
US6800918B2 (en) * 2001-04-18 2004-10-05 Intel Corporation EMI and noise shielding for multi-metal layer high frequency integrated circuit processes
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
US6949411B1 (en) * 2001-12-27 2005-09-27 Lam Research Corporation Method for post-etch and strip residue removal on coral films
US20030215570A1 (en) * 2002-05-16 2003-11-20 Applied Materials, Inc. Deposition of silicon nitride
US20050062164A1 (en) * 2003-09-23 2005-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving time dependent dielectric breakdown lifetimes
US7444867B2 (en) * 2005-01-04 2008-11-04 Bell Geospace, Inc. Accelerometer and rate sensor package for gravity gradiometer instruments
KR101674989B1 (ko) 2013-05-21 2016-11-22 제일모직 주식회사 레지스트 하층막용 조성물, 이를 사용한 패턴 형성 방법 및 상기 패턴을 포함하는 반도체 집적회로 디바이스
US12454752B2 (en) * 2022-01-14 2025-10-28 Asm Ip Holding B.V. Method and apparatus for forming a patterned structure on a substrate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09139423A (ja) 1995-11-13 1997-05-27 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3660799B2 (ja) 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3300643B2 (ja) 1997-09-09 2002-07-08 株式会社東芝 半導体装置の製造方法
US6066569A (en) * 1997-09-30 2000-05-23 Siemens Aktiengesellschaft Dual damascene process for metal layers and organic intermetal layers
TW337608B (en) * 1997-10-29 1998-08-01 United Microelectronics Corp Process for producing unlanded via
DE19756988C1 (de) * 1997-12-20 1999-09-02 Daimler Benz Ag Elektrisch beheizbare Glühkerze oder Glühstab für Verbrennungsmotoren
JP3107047B2 (ja) * 1998-05-28 2000-11-06 日本電気株式会社 半導体装置の製造方法
JP3186040B2 (ja) * 1998-06-01 2001-07-11 日本電気株式会社 半導体装置の製造方法
KR20000019171A (ko) * 1998-09-09 2000-04-06 윤종용 감광성 폴리머를 사용하는 금속배선 형성방법
US6184142B1 (en) * 1999-04-26 2001-02-06 United Microelectronics Corp. Process for low k organic dielectric film etch
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
US6261963B1 (en) * 2000-07-07 2001-07-17 Advanced Micro Devices, Inc. Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996653A (zh) * 2014-05-09 2014-08-20 上海大学 Tft深接触孔制造方法
CN103996618A (zh) * 2014-05-09 2014-08-20 上海大学 Tft电极引线制造方法
CN103996653B (zh) * 2014-05-09 2017-01-04 上海大学 Tft深接触孔制造方法
CN103996618B (zh) * 2014-05-09 2017-01-18 上海大学 Tft电极引线制造方法

Also Published As

Publication number Publication date
US6495466B2 (en) 2002-12-17
US6734104B2 (en) 2004-05-11
JP2001308178A (ja) 2001-11-02
KR100783868B1 (ko) 2007-12-10
KR20010098743A (ko) 2001-11-08
JP4057762B2 (ja) 2008-03-05
US20030073317A1 (en) 2003-04-17
US20010034132A1 (en) 2001-10-25

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