TW501010B - Memory attribute palette - Google Patents

Memory attribute palette Download PDF

Info

Publication number
TW501010B
TW501010B TW087112447A TW87112447A TW501010B TW 501010 B TW501010 B TW 501010B TW 087112447 A TW087112447 A TW 087112447A TW 87112447 A TW87112447 A TW 87112447A TW 501010 B TW501010 B TW 501010B
Authority
TW
Taiwan
Prior art keywords
memory
attribute
memory attribute
signal
register
Prior art date
Application number
TW087112447A
Other languages
English (en)
Chinese (zh)
Inventor
Lance E Hacking
Bryant E Bigbee
Shahrokh Shahidzadeh
Shreekant S Thakkar
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW501010B publication Critical patent/TW501010B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Generation (AREA)
TW087112447A 1997-08-18 1998-07-29 Memory attribute palette TW501010B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/914,578 US5946713A (en) 1997-08-18 1997-08-18 Memory attribute palette

Publications (1)

Publication Number Publication Date
TW501010B true TW501010B (en) 2002-09-01

Family

ID=25434537

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087112447A TW501010B (en) 1997-08-18 1998-07-29 Memory attribute palette

Country Status (10)

Country Link
US (1) US5946713A (enExample)
JP (1) JP4312952B2 (enExample)
KR (1) KR100358601B1 (enExample)
CN (1) CN1149484C (enExample)
AU (1) AU8577298A (enExample)
BR (1) BR9811952B1 (enExample)
DE (1) DE19882617B4 (enExample)
GB (1) GB2343275B (enExample)
TW (1) TW501010B (enExample)
WO (1) WO1999009510A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694418B2 (en) * 2001-03-30 2004-02-17 Intel Corporation Memory hole modification and mixed technique arrangements for maximizing cacheable memory space
US6681311B2 (en) * 2001-07-18 2004-01-20 Ip-First, Llc Translation lookaside buffer that caches memory type information
KR100633144B1 (ko) 2004-11-09 2006-10-11 삼성전자주식회사 색 관리방법 및 이를 적용한 색 관리장치
JP4783163B2 (ja) * 2006-01-19 2011-09-28 Ｏｋｉセミコンダクタ株式会社 マイクロコントローラ
US7949834B2 (en) * 2007-01-24 2011-05-24 Qualcomm Incorporated Method and apparatus for setting cache policies in a processor
US8103816B2 (en) * 2008-10-28 2012-01-24 Intel Corporation Technique for communicating interrupts in a computer system
US9331855B2 (en) 2011-07-01 2016-05-03 Intel Corporation Apparatus, system, and method for providing attribute identity control associated with a processor
US20130111181A1 (en) * 2011-10-31 2013-05-02 Lsi Corporation Methods and apparatus for increasing device access performance in data processing systems
US11513779B2 (en) 2020-03-19 2022-11-29 Oracle International Corporation Modeling foreign functions using executable references
US11875168B2 (en) 2020-03-19 2024-01-16 Oracle International Corporation Optimizing execution of foreign method handles on a virtual machine
US11543976B2 (en) * 2020-04-01 2023-01-03 Oracle International Corporation Methods for reducing unsafe memory access when interacting with native libraries

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668949A (en) * 1993-11-12 1997-09-16 Intel Corporation System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
US5590289A (en) * 1993-11-12 1996-12-31 Intel Corporation Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources
US5561814A (en) * 1993-12-22 1996-10-01 Intel Corporation Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
US5819079A (en) * 1995-09-11 1998-10-06 Intel Corporation Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch

Also Published As

Publication number Publication date
HK1027183A1 (en) 2001-01-05
KR100358601B1 (ko) 2002-10-25
DE19882617B4 (de) 2007-06-21
DE19882617T1 (de) 2000-09-21
CN1149484C (zh) 2004-05-12
WO1999009510A2 (en) 1999-02-25
AU8577298A (en) 1999-03-08
GB0003909D0 (en) 2000-04-05
BR9811952B1 (pt) 2011-08-23
BR9811952A (pt) 2000-08-22
KR20010022983A (ko) 2001-03-26
CN1276892A (zh) 2000-12-13
WO1999009510A3 (en) 1999-05-14
JP2001516089A (ja) 2001-09-25
JP4312952B2 (ja) 2009-08-12
GB2343275A (en) 2000-05-03
US5946713A (en) 1999-08-31
GB2343275B (en) 2002-05-29

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