BR9811952A - Paleta de atributo de memória - Google Patents

Paleta de atributo de memória

Info

Publication number
BR9811952A
BR9811952A BR9811952-4A BR9811952A BR9811952A BR 9811952 A BR9811952 A BR 9811952A BR 9811952 A BR9811952 A BR 9811952A BR 9811952 A BR9811952 A BR 9811952A
Authority
BR
Brazil
Prior art keywords
memory
attribute
attributes
memory attribute
signals
Prior art date
Application number
BR9811952-4A
Other languages
English (en)
Other versions
BR9811952B1 (pt
Inventor
Lance E Hacking
Bryant E Bigbee
Shahrokh Shahidzadeh
Shreekant S Thakkar
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9811952A publication Critical patent/BR9811952A/pt
Publication of BR9811952B1 publication Critical patent/BR9811952B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Generation (AREA)

Abstract

Patente de Invenção: <B>"PALETA DE ATRIBUTO DE MEMóRIA"<D>. A presente invenção refere-se com um sistema de computador no qual os atributos de memória linear são especificados. Os atributos de memória física também podem ser especificados nos registros de atributo físico. Uma paleta de atributo de memória (MAP) recebe os sinais índice e seleciona os atributos de memória linear em resposta aos sinais índice. Um seletor de atributo de memória efetiva recebe os sinais de atributo de memória linear selecionados e, se presente, os sinais de atributo de memória física e em resposta aos mesmos, seleciona os sinais de atributo de memória efetiva para apresentar atributo de memória efetiva. Em uma modalidade preferida, os atributos de memória linear podem ser gravados de forma programada em um ou mais registros, por meio disso permitindo a um programa ou a um OS a flexibilidade na escolha dos atributos de memória, incluindo os atributos de memória não atualmente utilizados. A invenção permite a um programa aplicar um atributo de memória da escolha para uma seção particular da memória, por meio disso permitindo ao sistema de computador proporcionar uma performance mais elevada.
BRPI9811952-4A 1997-08-18 1998-07-21 processador e método para especificar atributos de memória. BR9811952B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/914,578 US5946713A (en) 1997-08-18 1997-08-18 Memory attribute palette
US08/914,578 1997-08-18
PCT/US1998/015054 WO1999009510A2 (en) 1997-08-18 1998-07-21 Memory attribute palette

Publications (2)

Publication Number Publication Date
BR9811952A true BR9811952A (pt) 2000-08-22
BR9811952B1 BR9811952B1 (pt) 2011-08-23

Family

ID=25434537

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI9811952-4A BR9811952B1 (pt) 1997-08-18 1998-07-21 processador e método para especificar atributos de memória.

Country Status (11)

Country Link
US (1) US5946713A (pt)
JP (1) JP4312952B2 (pt)
KR (1) KR100358601B1 (pt)
CN (1) CN1149484C (pt)
AU (1) AU8577298A (pt)
BR (1) BR9811952B1 (pt)
DE (1) DE19882617B4 (pt)
GB (1) GB2343275B (pt)
HK (1) HK1027183A1 (pt)
TW (1) TW501010B (pt)
WO (1) WO1999009510A2 (pt)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694418B2 (en) * 2001-03-30 2004-02-17 Intel Corporation Memory hole modification and mixed technique arrangements for maximizing cacheable memory space
US6681311B2 (en) * 2001-07-18 2004-01-20 Ip-First, Llc Translation lookaside buffer that caches memory type information
KR100633144B1 (ko) 2004-11-09 2006-10-11 삼성전자주식회사 색 관리방법 및 이를 적용한 색 관리장치
JP4783163B2 (ja) * 2006-01-19 2011-09-28 Ｏｋｉセミコンダクタ株式会社 マイクロコントローラ
US7949834B2 (en) * 2007-01-24 2011-05-24 Qualcomm Incorporated Method and apparatus for setting cache policies in a processor
US8103816B2 (en) * 2008-10-28 2012-01-24 Intel Corporation Technique for communicating interrupts in a computer system
US9331855B2 (en) 2011-07-01 2016-05-03 Intel Corporation Apparatus, system, and method for providing attribute identity control associated with a processor
US20130111181A1 (en) * 2011-10-31 2013-05-02 Lsi Corporation Methods and apparatus for increasing device access performance in data processing systems
US11875168B2 (en) 2020-03-19 2024-01-16 Oracle International Corporation Optimizing execution of foreign method handles on a virtual machine
US11513779B2 (en) 2020-03-19 2022-11-29 Oracle International Corporation Modeling foreign functions using executable references
US11543976B2 (en) * 2020-04-01 2023-01-03 Oracle International Corporation Methods for reducing unsafe memory access when interacting with native libraries

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5590289A (en) * 1993-11-12 1996-12-31 Intel Corporation Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources
US5668949A (en) * 1993-11-12 1997-09-16 Intel Corporation System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
US5561814A (en) * 1993-12-22 1996-10-01 Intel Corporation Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
US5819079A (en) * 1995-09-11 1998-10-06 Intel Corporation Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch

Also Published As

Publication number Publication date
TW501010B (en) 2002-09-01
DE19882617T1 (de) 2000-09-21
CN1276892A (zh) 2000-12-13
US5946713A (en) 1999-08-31
JP4312952B2 (ja) 2009-08-12
WO1999009510A2 (en) 1999-02-25
BR9811952B1 (pt) 2011-08-23
AU8577298A (en) 1999-03-08
GB0003909D0 (en) 2000-04-05
HK1027183A1 (en) 2001-01-05
WO1999009510A3 (en) 1999-05-14
DE19882617B4 (de) 2007-06-21
GB2343275A (en) 2000-05-03
JP2001516089A (ja) 2001-09-25
GB2343275B (en) 2002-05-29
KR100358601B1 (ko) 2002-10-25
KR20010022983A (ko) 2001-03-26
CN1149484C (zh) 2004-05-12

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 23/08/2011, OBSERVADAS AS CONDICOES LEGAIS.

B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 23.08.2021