TW499823B - Printed circuit board and its manufacturing method - Google Patents

Abstract

By disposing chip capacitor 20 in the printed circuit board 10, the separation distance between IC chip 90 and the chip capacitor 20 is reduced such that it is capable of decreasing the circuit inductance. Thus, by laminating the first resin board 30a, the second resin board 20b and the third resin board 30c to form the printed circuit board, a core board 30 with adequate strength can be obtained.

Description

499823 [Technical Field] · The present invention relates to a printed circuit board on which electronic components such as IC chips are mounted and a method for manufacturing the same, and more particularly, to a printed wiring board with a built-in capacitor and a method for manufacturing the same. [Conventional Technology] At present, a printed circuit board for assembling a substrate has a chip capacitor mounted on its surface for the purpose of smoothly supplying IC chip power and the like. 03 Because the reactance of the wiring from the chip capacitor to the IC chip is frequency dependent, as 1 (: the driving frequency of the chip increases, even if a chip capacitor is mounted on the surface, a sufficient effect cannot be obtained. 9 Therefore, The present inventor proposed a technique for forming a recess in a core plate and receiving a chip capacitor in the recess in No. 2424 No. 1. In addition, the techniques for embedding capacitors in a substrate / board include No. 6_326472 and No. 7- 263 " 619, JP-A-1 0-256429, JP-A-1 1-45955, JP-A-1 1-1 26978, JP-A-1 ^ -3 ^ 868, etc. 幵 JP-A-6-326472 was exposed on the glass The resin substrate f made of epoxy is a technology for embedding capacitors. With this structure, power supply noise (n01Se) can be reduced, and there is no need to install a chip capacitor space (s ^ a), and the substrate can be used. Kaiping No. 7_26361 No. 9 reveals the technology of capacitors in ceramics, layers, and terminals. With this structure, the power supply is connected to shorten the wiring length and reduce the impedance of the wiring. Kaikai " 26472 No., No. 7,3619, No. 2 =;: C crystal Distance capacitor 1C of the wafer at high frequency ". R now low inductance particularly necessary in the manufacture of multi resin

Layer printed circuit board, ceramics, and interlayer resin insulation layer terminals and interlayer windows , Li's absolute reliability in the interlayer resin.

脂 组合 的 核 # Heart substrate Therefore, the chip capacitor has cracks in the chip capacitor and the edge layer, and the surface, the invention of No. 1-2424831 No. 1 is not available when the capacitor is turned on and placed vertically. Correctly connecting the capacitor's terminals and interposer will not supply power from the capacitor to the 1C chip. In order to solve the above problems, the present invention aims to provide a printed circuit board with built-in electronics and high connection reliability, and a method for manufacturing the printed circuit board. In order to achieve the above-mentioned purpose, the printed circuit board of the first scope of the application for a patent is an interlayer resin insulation layer and a conductor circuit which are laminated on a core substrate that houses a capacitor. The core substrate that houses the capacitor is A resin substrate, a second resin substrate having a capacitor receiving opening, and a third resin substrate are laminated. In addition, the method of manufacturing a printed circuit board according to item 16 of the patent application includes at least the following steps (a) to (d): (a) forming a conductor pad portion on a first resin substrate; (b) ) A capacitor is connected to the conductor pad portion of the first resin substrate via a conductive 1 adhesive; i (c) a third resin substrate and a second resin substrate having an opening for accommodating the capacitor and the first resin substrate , The capacitor of the first resin substrate is housed in the opening of the second resin substrate, and 1! _ 1 1 1 1 1 1 1 1 Ϊ 2160-3403-?!. Ptd page 6 499823 I Description of the invention (3) «The third resin substrate is laminated with the opening of the 苐 2 resin substrate, and is laminated through a bonding plate; and (d) the first resin substrate, the second resin substrate, and the third resin substrate are laminated. The resin substrate is heated and pressurized to form a core substrate. | The printed circuit board with the scope of patent application No. 1 and the printed circuit board with the scope of patent application No. 16 can manufacture capacitors in the core substrate. 'Because the distance between the IC chip and the capacitor can be shortened, the printed circuit can be reduced. The loop inductance of the board. In addition, since the resin substrate is laminated, sufficient strength can be obtained on the core substrate. In addition, the first resin substrate and the third resin substrate are arranged on both sides of the core substrate to form a core substrate smoothly. An interlayer resin insulation layer and a conductor circuit can be appropriately formed on the core substrate, and the printed circuit board can be reduced. Incidence of defective products. An interlayer resin insulating layer is provided on the core substrate, and an interlayer window or a through-hole is applied to the interlayer resin insulating layer to form a circuit formed by a buid method in which a conductive layer is a conductor circuit. You can use either the semi additive method or the fuU additive method! The gap is preferably filled with resin. Since there is no gap between the capacitor and the core substrate, the operation of the capacitor is reduced, and even if stress starting from the capacitor occurs, it can be alleviated by the filled resin. In addition, this tree moon also has the effect of reducing the adhesion and migration of the capacitor and the core substrate. I. The second item in the scope of patent application is because the aforementioned bonding sheet is impregnated with a core material in a thermosetting resin, so a core base with high strength can be obtained.

499823 V. Description of invention ⑷ β plate. The scope of the patent application is No. 3. The board is a board in which the heartwood is impregnated in the tree moon purpose. Term 4 of the scope of patent application Because the above-mentioned first, second, and third resin-based resins can be obtained with a high-strength core-based container, it is possible that electricity may be contained in the core substrate. • Please normalize the patent. ... It can be said that the number of layers of the insulating layer is formed on the second resin substrate due to the conductor circuit. Door soil board ’s wiring density ’and reduce the interlayer resin.

A capacitor is added to the capacitor.疋 The device contained in the printed circuit board is shortened, so the chip is shortened by 1C; the capacitor is stored in the printed circuit board to supply the lightning source instantaneously, and the distance between the other two devices is to reduce the inductance of the circuit. A capacitor can be equipped. Therefore, it can be installed because of the large chip power on the surface of the printed circuit board. And large-capacity capacitors, and it is easy to supply 1C. The scope of the patent application is the seventh. The capacity is the chip capacitance of the inner layer. Because the surface area of the chip capacitor's electrostatic power supply will not be less than t capacitance, it works at high frequency. "Insufficient" can ensure that the desired range of patent application for the 1C chip is No. 8, θ & Main A-is the inductive reactance of the chip capacitor in the inner layer. Insufficient, can continue to be accompanied by the two W in the southern frequency region of the electric circuit to prevent the desired IC chip from the application of the scope of the patent application of the 9th and 10th. The connection between the openings and the openings of the interlayer window of the electric ore can be respected to the electrode that forms the crystals of the metal film and serves the electricity. Here, the description of the chip and the invention (5) = the two electrodes are S convex on the surface of metallize, = the surface is smooth due to the metal film, even if the heating cycle test is performed, it is And the board and the like broke. The metal film for which the valley is an electrode is preferably provided with any one of copper, nickel, and noble metal. This is because the layers of tin and lead on the built-in capacitors are likely to cause shifts in the results of /, S ®. Therefore, the occurrence of offset can also be prevented. ° t x I ^ can also be roughened on the surface of the chip capacitor. borrow

This 5 y increases the adhesiveness of the ceramic capacitor chip capacitor and resin connection layer and 11 resin insulation layer. Even if the heating cycle test is performed, the bonding layer at the interface and the interlayer resin insulation layer will not peel off. ^ The scope of application for patent No. 11 is to coat at least a part of the electrode of the chip capacitor and store it in a printed circuit board, and obtain electrical connection to the electrode exposed from the aforementioned coating layer. At this time, the metal exposed from the cladding layer is preferably composed mainly of copper. Because it can reduce the resistance. "Applicant No. 12 of the scope of patent application is because a chip capacitor is used in which an electrode is formed on the inner side of the outer edge, and even if it is turned on through the interlayer window, the external electrode is increased." Due to the increase in the allowable range of alignment, the connection is poor. Article 13 of the scope of patent application, because wafer capacitors 5 with electrodes formed in a matrix are used, so it is easy to store large wafer capacitors in the core substrate. Therefore, due to the increase in electrostatic capacity, electrical problems can be solved. Even after various thermal experiences, it is difficult to bend the printed circuit board. Item 14 of the scope of patent application can also use a large number of chip capacitors.

499823 V. Description of the invention (6) ---

Multiple links. In this case, the electrostatic capacity can be adjusted appropriately, and the IC chip can operate properly. L No. 15 of the scope of patent application, the thermal expansion rate of the insulating adhesive is smaller than the thermal expansion rate of the receiving layer, that is, set near the capacitor made of ceramic. Therefore, in the thermal cycle test, even if internal stress caused by the difference in thermal expansion coefficient between the core substrate and the capacitor occurs, it is difficult for the core substrate to break and peel, and high reliability can be achieved. Qe

In order to achieve the above-mentioned object, the invention of the seventh patent scope is: a printed circuit board with a resin insulating layer and a conductor circuit laminated on a core substrate, wherein the core substrate is a plurality of resin substrates bonded together to form a conductor circuit As a result, a capacitor is housed in the core substrate of the seventh description. The invention of claim 18 in the scope of patent application is a printed circuit board in which a resin insulating layer and a conductor circuit are laminated on a core substrate. The core substrate J is formed by bonding a plurality of resin substrates to form a conductor circuit. A capacitor is housed in a recess formed therein. Front = Items 1 and 7 and 18 in the special range. Capacitors can be stored in the core substrate. ^ Γ shortens the distance between the IC chip and the valley device, thus reducing the inductive reactance of the printed circuit. In addition, since the core substrate is formed by a plurality of resins forming a conductor circuit, the wiring density of the core substrate can be increased, and the number of interlayer resin insulating layers can be reduced. ί ^ # a 1 = An interlayer resin insulating layer is provided on the substrate, and an interlayer tree = two i = interlayer windows or through holes to form a conductive layer as a conductor (U1 Id up). Either a semi-additive method or a full-additive method may be used.

Page 10 499823 V. Description of the invention (7) The gap is preferably filled with resin. Since there is no gap between the capacitor and the core " substrate, the operation of the built-in capacitor becomes small, and even if stress starting from the capacitor occurs, the filled resin can be used to relax it. In addition, the tree moon day also has the effect of reducing the adhesion and migration of the power valley and the core substrate. Item 19 in the scope of the patent application is because a plurality of resin substrates are bonded together via an adhesive plate, and thus can be firmly adhered. The scope of application for patent No. 20 is that the core substrate has a high strength because the core material is impregnated with a thermosetting resin. The 21st item in the scope of the patent application is that the resin substrate is impregnated with resin in the core material, so the core substrate has high strength. Item 22 of the scope of patent application 'Since the capacitor is housed in the core substrate, the capacitor can be highly integrated. Item 23 of the scope of patent application is to add a capacitor to the aforementioned printed electric capacitor. Because the device is housed in the printed circuit board, the distance between the 1C chip and the capacitor is shortened, and the circuit power supply is reduced. 2 On the one hand, because the printed circuit board is equipped with a capacitor, a large-capacity Capacitance = surface

Chips have high power. # 易 Supply IC applies for the scope of patent application No. 24, because the chip capacitance on the surface is greater than the capacitance of the chip capacitor on the inner layer,% static electricity: The regional power supply will not be insufficient, which can ensure the desired = high frequency operation. The motion of θ No. 25 in the scope of patent application 1 Because of the surface chip capacitance 11 Inductive reactance

It is because the power supply in the internal supply is smooth, the power failure occurs and the interlayer is generated. 2 Chip capacitors: the above-mentioned inductance is insufficient, which can ensure the desired operating range of the K-chip: the 26th and 27th of the patent scope of the month, and the capacitor 2 formed by electroplating 2 to the capacitor forming a metal film ：: The film mouth is provided with a concave-convex male sheet on the surface of the metallized composition: the heating cycle test will not be performed on the electrode and the metal film 5 of the electrode of the device is preferably provided with copper, nickel, and f. This is because the layers of tin and lead on the built-in capacitor are easy to shift due to the continuation of the mouth. Therefore, it is also possible to prevent misalignment and to roughen the surface of the chip capacitor. By using ^ Γ to increase the ceramic capacitor's chip capacitor and resin composition's connection layer, and the K's adhesion to the insulating layer, even if the heating cycle test is performed, it does not "peel off the bonding layer at the interface or the interlayer resin insulating layer. ^ No. 28 of the scope of the patent application, at least a part of the other coating layer of the electrode of the chip capacitor is routed to the printed circuit board and electrically connected to the electrode exposed from the aforementioned coating layer. At this time, from The metal exposed by the coating layer is preferably copper as the main component. Because it can reduce the connection resistance. The scope of application for patents is 29, because it is a chip capacitor that forms an electrode on the inner side of the outer edge. electrode

If it increases, the allowable range of alignment will increase, so there will be no splicing. No. 30 of the scope of patent application, because chip capacitors are used to form electrodes in a matrix, so it is easy to store large chip capacitors on the core substrate.

2160-3403-Pf-pid Page 12 499823 5. Description of the invention (9). Therefore, as the electrostatic capacity increases, the electrical problem can be solved. • Also, it is difficult to bend or bend the printed circuit board even after various thermal experiences. The 31st scope of the patent application can also connect a plurality of chip capacitors to be used! Thereby, the electrostatic capacity can be adjusted appropriately, and the IC chip can operate appropriately. In the scope of application for patent No. 32, the thermal expansion coefficient of the insulating adhesive is smaller than the thermal expansion coefficient of the valley layer, that is, it is set near the capacitor composed of ceramics. Therefore, in the thermal cycle test, even if internal stress caused by the difference in thermal expansion coefficient between the core substrate and the capacitor occurs, it is difficult for the core substrate to break and peel, and high reliability can be achieved. The method for manufacturing a printed circuit board according to item 33 of the patent application includes at least the following steps (a) to (e): (a) forming a conductor circuit on a plurality of resin substrates; I (b) laminating through a bonding board A plurality of the aforementioned resin substrates; i (c) connecting the aforementioned resin substrate to a core substrate via the aforementioned bonding board; (d) forming a recess on the core substrate; and (e) accommodating a capacitor in the recess. The method for manufacturing a printed circuit board under the scope of patent application No. 34 includes at least the following steps (a) to (e):! (A) Forming a resin base with a through hole and a conductor circuit on the surface (b) A resin substrate with a through hole and a conductor circuit on the surface,

2160-3403-Fi-? Td Page 13 4 ^ 9823 V. Description of the invention αο) -------- (〇 The resin substrate with through holes and the resin substrate without through holes are passed through the bonding board. (D) layering the resin substrate into a core-based I-plate via the bonding plate; and (e) accommodating the capacitor in the through-hole.

…, Please refer to items 33 and 34 in the scope ”Capacitors can be housed in the core substrate, because the distance between the IC chip and the capacitor can be shortened, and the inductance of the printed circuit board can be reduced. In addition, since the core substrate is formed by laminating a plurality of conductor circuits and a resin substrate, the wiring density of the core substrate can be increased, and the number of interlayer resin insulating layers can be reduced. ^ In order to achieve the above-mentioned purpose, the printed circuit board with the scope of patent application No. 35 is applied on the core substrate of the winter capacitor, and the interlayer resin insulation layer and the conductor circuit are alternately laminated, wherein the core substrate for housing the capacitor is A resin substrate, a second resin substrate having a opening for accommodating a capacitor, and a third resin substrate are laminated, and on both sides of the core substrate, interposer windows connected to the terminals of the capacitor are arranged.

The printed circuit board with the scope of patent application No. 35 can be contained in the core substrate. Since the distance between the Ϊ C chip and the capacitor can be shortened, the circuit inductance of the printed circuit board can be reduced. In addition, since the resin substrate is laminated, sufficient strength can be obtained on the core substrate. In addition, the first resin substrate and the third resin substrate are arranged on both sides of the core substrate to form a core substrate smoothly. An interlayer resin insulating layer and a conductor circuit can be appropriately formed on the core substrate, and the printed circuit board can be reduced. Incidence of defective products. In addition, since interposer windows are provided on both sides of the core substrate, iC can be connected in the shortest distance.

21 60-3403-Fi-pid Page 14 499823 I. Description of the Invention (11) Chip and Chip Capacitor ’can supply instantaneous high-power to IC chip from external connection substrate. An interlayer resin insulating layer is provided on the core substrate, and an interlayer window or a through hole is applied to the interlayer resin insulating layer to form a conductive layer which is a circuit formed by a bu 1 i d up method of a conductive circuit. You can also use either the semi-additive method or the full-additive method. In addition, by providing connection wiring, wiring can be applied to the lower portion of the capacitor. Therefore, the degree of freedom of wiring can be increased, and the density and size can be reduced. | The gap is preferably filled with resin. Since there is no gap between the capacitor and the core substrate, the built-in capacitor operation becomes smaller. Even if the capacitor I !, the stress at the starting point, can be relieved by the filled resin. In addition, this i-resin also has the effect of reducing the adhesion and migration of the capacitor to the core substrate. The scope of application for patent No. 36 is that the core substrate has high strength because the core material is impregnated with a thermosetting resin. The 37th item of the scope of patent application is because the core substrates are impregnated with resin in the first, second, and third resin substrates, so the core substrate has high strength. Specifically, a reinforcing material such as glass epoxy or glass phenol can be used. The 38th scope of the patent application is because a plurality of capacitors are housed in the core substrate, so the capacitors can be highly integrated. Therefore, the capacity can be ensured. As described in item 39 of the scope of the patent application, because the conductor circuit is formed on the second resin substrate, the wiring density of the substrate can be increased and the interlayer resin can be reduced. 499823 5. Description of the invention (12) The number of layers of the insulating layer. ☆ Please apply for the scope of the patent. Add capacitors to the capacitors, so shorten the IC crystal to supply power instantaneously, and install capacitors, so the chip has high power. The scope of patent application capacity is the power supply in the crystal area of the inner layer does not work. The scope of the patent application is that the supply of wafer power to the inner layer will not be insufficient. The scope of the patent application continues to that the electrode forming the metal container is gold and the surface is smooth, even if the board or the like is disconnected. Any of the electrodes of a capacitor. Because the connection with the interlayer window is the 40th item, which is in the aforementioned receiver. Because the device inside the printed circuit board is separated, the circuit is reduced.

v Unfair, and it is easy to supply 1C item 41, because the static electricity of the chip capacitor on the surface is the static electricity of the benefit. τ p is above the valley of the power storage, so it is insufficient at high frequencies, which can ensure the desired 1C chip. Item: Because the inductive reactance of the inductive reactance of the chip capacitor on the surface is more than that, in the high frequency region, electricity can ensure the desired 1C chip operation. ‘Item 43 ^, the electrode of a chip capacitor obtained by electroplating a dielectric window. Here, the surface of the wafer is composed of bumps, but because the metal film is subjected to a thermal cycle test, the electrode and the connected metal film will not be tinned. It is preferable to equip capacitors with copper, nickel, and precious metals. Layers such as lead and lead can easily cause partial offsets. Therefore, it is also possible to prevent the occurrence of shifts. 499823 V. Zhaiming explained (13) This 1 can increase the connection between the ceramic capacitor chip capacitor and the resin composition: the adhesion of the resin insulation layer between successive layers, even if the heating cycle test is performed. It will send out the peeling of the interlayer resin insulation layer at the interface. Expose the patent scope item No. 45. The slope of the electrode of the chip capacitor is covered at least in part and housed in a printed circuit board. The electrode exposed by the slope cover. At this time, 9 The metal exposed from the slope cover is preferably copper as the main component D because it can reduce the connection resistance. I I applied for the scope of the patent No. 46 because it is formed on the inner side of the outer edge.

| Electrode chip capacitors. Even if they are turned on through the interlayer window, the increase in the number of external electrodes 丨 increases the allowable range of alignment, so there is no connection failure. I. The scope of patent application No. 47. Since a wafer capacitor is used in which electrodes are formed in a matrix, it is easy to store a large wafer capacitor in a core substrate. Therefore, as the electrostatic capacity increases, the electrical problem can be solved. Also, it is difficult for the printed circuit board to bend even through various thermal experiences. Item 48 of the scope of patent application can also use a plurality of chip capacitors to be accessed, and multiple connections. Thereby, the capacitance can be adjusted appropriately, and the IC chip can operate reliably. ~ Item 49 of the scope of the patent application, the thermal expansion coefficient of the insulating adhesive is smaller than the thermal expansion coefficient of each layer, that is, it is set near the capacitor with a ceramic composition. Therefore, in the thermal cycle test, even if the thermal expansion of the core substrate and the capacitor gate occurs, Due to the internal stress caused by the difference in rate, it is difficult to cause cracks and peeling in the core substrate, and high reliability can be achieved. The method for manufacturing a printed circuit board with a scope of application for item 50 includes at least the following steps (a) to (d):

V. Description of the invention (14) ---... (a) Install the electric cry on the first resin substrate via the adhesive material; (b) Open the third resin substrate with the opening for accommodating the aforementioned electric appliance: = 2 resin substrate and the first resin substrate, the capacitor of the first resin substrate is housed in the opening of the second resin substrate, and the third resin substrate is stuffed into the second resin substrate. The state of the aforementioned openings: 1 state, laminated via a bonding board; (C) forming an opening for an interposer window on which the capacitor is placed on the core substrate by laser irradiation; and I (d) for the interposer window A via window is formed in the opening. | The method for manufacturing a printed circuit board under the scope of patent application No. 51, at least | I includes the following steps (a) to (f): I1 j \ (a) forming an interlayer on a metal film on one side of the i-th resin substrate Opening for window formation; (b) Mounting a capacitor on a non-formed surface of the first resin substrate through a bonding material through a bonding material; (c) A third resin substrate and a second resin having an opening for receiving the capacitor The substrate and the first resin substrate 5 in a state where the capacitor of the first resin substrate is stored in the opening of the second resin substrate, and the third resin substrate is plugged into the opening of the second resin substrate, (D) The first resin substrate, the second resin substrate, and the! 3 resin substrate are heated with a pressure of π to form a core substrate, and i! (E) is irradiated with a laser, and Forming an opening for an interposer window on which the i capacitor is placed on the core substrate; and

I. V. Description of the invention (15) '-' --- G ^ An interstitial window is formed with an opening in the interstitial window just described. · Cry 'Ming patent No. 51, because the capacitor is housed in the printed circuit board. ^ The distance between the IC chip and the capacitor is shortened, and the inductive reactance of the printed circuit board is reduced. In addition, "the first resin substrate on which metal film is formed on one side!" Is set on the top of the first resin substrate, and the opening is "positioned by laser irradiation", except for the resin insulation layer exposed by the mouth, and provided. The opening for the interlayer window ^ Because the opening diameter of the interlayer window is determined by the opening diameter of the metal film, the appropriate opening diameter can be used to form the interlayer window. In addition, similarly, the precision of the opening position of the interposer window depends on the opening position of the metal film. Therefore, even if the precision of the laser irradiation position is low, the interposer window can be formed at an appropriate position. I ^ j The method for manufacturing a printed circuit board under the scope of patent application No. 52, at least I includes the following steps (a) to (f): (a) a first resin substrate and a third resin substrate with a metal film on one side An opening for forming an interposer window is formed on the metal film; (b) a capacitor is mounted on the non-formed surface of the first resin substrate through a bonding material; (c) a third resin substrate and The opened second resin substrate and the first resin substrate receive the capacitor of the first resin substrate in the opening of the second resin substrate, and the third resin substrate is plugged into the second resin substrate. The state of the opening is laminated through the bonding plate;

1 (d) heating and pressing the first resin substrate, the second resin substrate, and the j 3 resin substrate to form a core substrate;

2160-34D3-PI-pid Page 19 499823 V. Description of the invention (16) t (e) Laser irradiation is formed on the aforementioned first resin substrate and the former il third tree !! ί The aforementioned interposer window is formed on the board Using openings' to form openings for the interposer windows where the aforementioned electrical appliances are placed; and (f) forming interposer windows in the aforementioned openings for the interposer windows ^ application for patent range 52, because the capacitor is housed in the printed circuit board | Second, therefore, the distance between the IC chip and the capacitor is reduced, and the j-circuit inductance of the printed circuit board is reduced. In addition, an opening is provided by etching or the like on the metal film of the third and third resin substrates j on which a metal film is formed, and the resin insulation layer exposed from the opening is removed by laser irradiation to the opening, and a window for an interposer is provided. With 2 openings. Thereby, since the opening diameter of the via window is determined by the opening diameter of the metal film, the via window can be formed with an appropriate opening diameter. In addition, similarly, the precision of the opening position of the layer opening depends on the opening position of the metal film | I, so even if the precision of the laser irradiation position is low, a via window can be formed at an appropriate position I i . On the other hand, since the resin substrate is laminated, a core plate with sufficient strength can be obtained. In addition, an i-th resin substrate and a third tree-shaped substrate are arranged on both sides of the core substrate to form a core substrate smoothly. An interlayer resin insulation layer and a conductor circuit can be appropriately formed on the core substrate, and the printed circuit board can be reduced. Incidence of adverse radon. In addition, because interlayer windows are provided on both sides of the core substrate, the IC chip and the chip capacitor can be connected in the shortest distance, and the instantaneous high power can be supplied to the c chip from the external connection substrate. The method for manufacturing a printed circuit board with a scope of application for patent No. 53 includes at least the following steps (a) to (g): | (a) the second resin substrate and the third resin with metal 暝 on one side

2160-3403-Pi-ptd Page 20 499823 V. Description of the invention (17) A through-hole is formed in the metal film of the substrate; (b) a capacitor is mounted on the metal material of the first resin substrate; (c) the first 3 resin substrate and second resin substrate and first resin substrate having an opening for accommodating the capacitor, the capacitor of the first resin substrate is accommodated in the opening of the second resin substrate, and the third resin substrate is placed on the third resin substrate The state in which the opening of the second resin substrate is plugged is laminated via a bonding plate; (d) the first resin substrate, the second resin substrate, and the first resin substrate are heated and pressed to form a core substrate; ^ ( e) the through holes formed in the first resin substrate and the third tree substrate are irradiated with laser light, and openings for the interposer windows of the capacitors are placed in the core substrate; gas (f) removes the metals Thin film or (g) forming a conductor circuit and a via window on the core substrate. Cry, I am in the 53rd item of the scope, because the capacitor circuit is contained in the printed circuit board / ¾ h ^ ^ α The distance of α reduces the road and rainbow of the printed circuit board. In addition, an opening is formed by etching or the like on the metal film on which the metal film is formed on one side, and the opening is formed by the mouth m. "T edge layer, and the interlayer window is provided with a magic opening. Lai · This S interlayer window depends on the diameter of the window, so it can be, because the diameter depends on the opening of the metal film, the mouth; the window ... outside The same setting 'so even if the laser irradiation position; genus = mouth: set and w is low, it can also be in an appropriate position

499823 V. Description of the invention (18) -------- Place the interlayer window on it. In addition, the metal film is removed by etching, and a fine-pitch circuit can be formed because the thickness of the wiring can be thinly formed. Since the resin substrate is laminated thereon, a core substrate having sufficient strength can be obtained. In addition, the first resin substrate and the third tree are arranged on both sides of the core substrate, and the core substrate is smoothly formed. An interlayer resin insulation layer and a conductor circuit can be appropriately formed on the core substrate, and the printed circuit can be reduced. The incidence of defective products. In order to achieve the above purpose, the invention of the 54th patent application is a printed circuit board in which a resin insulation layer and a conductor circuit are laminated on a core substrate, and a capacitor is built in the core substrate to form a connection with the capacitor. The relatively large lower interlayer window is provided with a plurality of relatively small upper interlayer windows connected to one of the aforementioned lower interlayer windows on the interlayer resin insulating layer above the core substrate. The scope of the patent application is No. 54. The capacitor is embedded in the core substrate, and a relatively large lower interlayer I window connected to the capacitor terminals is formed on the electric substrate. On the interlayer resin insulation layer above the core substrate, Suppose that there are a plurality of relatively small upper interlayer windows connected to one | lower interlayer window. In this way, | corresponds to the position of the capacitor, and the terminals of the capacitor and the lower interlayer window 1 can be connected, but the power can be supplied from the capacitor to the chip. Furthermore, by providing a plurality of relatively small upper interlayer windows, the same effect as that of the inductive reactance can be obtained in parallel, and the high-frequency characteristics of the power line and the ground line can be improved, and the power supply shortage or the grounding degree can be prevented The I cj chip moves incorrectly. In addition, since the wiring length can be shortened, the loop j inductance can be reduced.

2160-3403-Ff-ptd Page 22

The support-concave is preferably filled with resin. With no gap between the capacitor and the core, there is no space between the plates, and the built-in container is used as a starting point. The inclusion state of A Zang becomes smaller. Even if electricity is lost, the mister Xu Xiemu Shi with the allowable tree month said to ease it. This (m i 2 has the effect of reducing the adhesion of the capacitor to the core substrate and offset emigration). The lights of Jieming are located at the 55th and 56th of Liganwei. They are filled with a flat surface ^ Window layer interlayer window = Borrow & ’Can be directly connected! A lower interposer Intermediate: interposer window. This can improve the performance of the lower boundary layer window and supply, but can actually carry out the electricity from the capacitor to the U chip.) Hsin: Please apply for the 57th patent scope, which is in the valley of the recess formed in the core substrate. Capacitor. Therefore, because the capacitor is arranged in the core substrate, the distance between the 1C chip and the capacitor is shortened, and the inductance of the circuit can be reduced. The 1 w patent application scope No. 58 is because a large number of capacitors are housed in the recessed portion, so the capacitor can be highly integrated. Gu applied for patents No. 59, 60 of the scope of the patent application, which were obtained by using a plated interlayer window to be connected to the electrode of a chip capacitor forming a metal film. Here, the electrode of the chip electric valleyr has unevenness on the surface of the metallized composition, but the surface is smooth due to the metal film, and even if the heating cycle test is performed, no disconnection will occur between the electrode and the plate. ^ The surface of the chip capacitor is preferably roughened. In this way, the connection layer and interlayer tree of chip capacitors made of ceramic and resin can be made. The adhesion of the insulating layer, even if the heating cycle test is performed, the bonding layer at the ^ interface and the interlayer resin insulation will not occur. Layer peeling. on

499823 I V. Description of the invention (20) " '-Application for patent No. 61, disclosed at least part of the electrode of the chip capacitor and housed in the printed circuit board, and the electrical connection is 1 = j The electrode of the covering layer is exposed. At this time, the gold and t exposed from the slope cover are mainly composed of copper. The reason is that the exposed metal, and the formation of a gold layer by electroplating can also improve the continuity and reduce the continuity resistance. _Apply for the scope of patent No. 62, because it is a chip capacitor using an inner-shaped j-electrode on the outer edge. Even if it is turned on through the interlayer window, the external dip! The 63rd scope of the patent application, because two wafer capacitors are formed in a matrix, makes it easy to accommodate large wafer capacitors in the core substrate. Therefore, as the electrostatic capacity increases, the electrical problem can be solved. Also, it is difficult for the printed circuit board to bend even through various thermal experiences. | The 64th scope of the patent application can also use multiple chip capacitors. Thereby, the capacitance can be adjusted appropriately, and the IC chip can operate appropriately. The scope of application for patent No. 65 is filled with resin between the core substrate and the capacitor. The thermal expansion coefficient of the resin is smaller than that of the core substrate, that is, it is set near the capacitor made of ceramic. Therefore, in the thermal cycle test, even if internal stress caused by the difference in thermal expansion coefficient between the core substrate and the capacitor occurs, it is difficult for the core substrate to crack or peel, and high reliability can be achieved. I The method for manufacturing a printed circuit board under the scope of application for patent No. 66 includes at least the following steps (a) to (e): (a) The capacitor is built in the core substrate as: (b) A resin insulation is formed on the above capacitor. Floor;

499823 V. Description of the invention (21) (c) Form a relatively large lower interlayer window on the resin insulation layer described above to contact the electrodes of the capacitor; (dy) form an interlayer resin insulation layer on the core substrate ; And * (e) a relatively small upper interlayer window connected to one of the aforementioned lower interlayer windows is provided on the aforementioned interlayer resin insulating layer. No. 66 of the scope of the patent application, the capacitor is formed with the capacitor end ® The multiple r-type interlayer windows connected to the upper substrate of the core substrate can be connected to each other, and the capacitors can be connected to each other, but they can be connected in the field. By arranging a plurality of relatively small, anti-parallel connection The same effect 咼 frequency characteristics, and prevent the wrong operation of the power supply IC chip. And, the road inductance is built in. Capacitors are built in the core substrate, and a relatively large lower interlayer resin insulation layer is connected with the sub-connection. 1 relatively small upper interlayer window. As a result, the capacitor terminal and the lower interlayer window capacitor provide power to the IC chip. The upper interlayer window can increase the power because it can be obtained. Insufficient to line and ground line or due to changes in ground level and can be shortened due to the wire length, can reduce back

The scope of patent application is 67, 7

Contains one capacitor. Because of this, because the distance between the IC chip and the capacitor is shortened in the concave portion of the core = core substrate, the capacitor is arranged in the core-capable second substrate. The aforementioned electricity ^ can be highly integrated. Electricity can be accommodated in the recessed portion of the multiple application patent scope item 69, because the right female feminine material is formed with a through hole, and is formed] :: The resin material is made of resin Resin

5. Description of the invention (22)-2 to form a core substrate having a recessed portion. Thereby, a core substrate having a concave portion with a flat bottom can be formed. It also applies for patents Nos. 70 and 71, using a flat surface filled interposer | 1-direction = as the lower interposer window. Thereby, one lower interposer | 1 can be directly connected to a plurality of upper interposer windows. Thereby, the continuity between the lower boundary layer window and the upper interlayer can be improved, and the power supply from the capacitor to the chip c can be performed on the spot.

The invention in item 72 of Shen Qing's patent scope is to apply pressure on the surfaces of a plurality of capacitors in the recess, or tap to average the height of the capacitors. Therefore, when the capacitors are arranged in the recesses, even if the sizes of the plurality of capacitors are changed, the heights can be averaged, and the core substrate can be smoothed. Thereby, the smoothness of the core substrate is not impaired, and since the upper interlayer resin insulating layer and the conductor circuit can be appropriately formed, the incidence of defective products on the printed circuit board can be reduced. [Simplified illustration] | Fig. 1 is a diagram showing the manufacturing steps I of the printed circuit board according to the first embodiment of the present invention. f-FIG. 2 is a drawing showing the manufacturing steps of the printed circuit board according to the first embodiment of the present invention. Fig. 3 is a drawing showing the manufacturing steps of the printed circuit board according to the first embodiment of the present invention. FIG. 4 is a manufacturing step of a printed circuit board according to the first embodiment of the present invention. FIG. C FIG. 5 is a manufacturing step of the printed circuit board according to the first embodiment of the present invention.

2160-3403- ?: .pU page 26 499823

I. Explanation of the invention (23)! Π I diagram. Fig. 6 is a drawing showing the manufacturing steps of the printed circuit board according to the first embodiment of the present invention. Fig. 7 is a sectional view of a printed circuit board according to the first embodiment of the present invention. I FIG. 8 is a cross-sectional view showing a state where an I c crystal I sheet is placed on a printed circuit board shown in FIG. 7 and a daughter board is mounted. i j FIG. 9 is a cross-sectional view showing a state where a C wafer is placed on a printed circuit board according to the first other example of the first embodiment of the present invention. Fig. 10 is a diagram showing the manufacturing steps of a printed circuit board according to the first modification of the embodiment i of the present invention.

Fig. 11 is a sectional view of a printed circuit board according to a first modification of the first embodiment of the present invention. Fig. 12 is a graph showing changes in voltage and time supplied to the IC chip. Fig. 13 is a sectional view showing a chip capacitor housed in a printed circuit board according to a first modification of the first embodiment of the present invention. Fig. 14 is a plan view showing a chip capacitor housed in a printed circuit board of the present invention.

FIG. 15 is a plan view showing a chip capacitor housed in a second modified printed circuit board of the second embodiment of the present invention.

= 16 is a plan view showing a chip capacitor housed in a Motoichi printed circuit board. U brother Z map. Fig. 17 shows the manufacturing steps of the printed circuit board according to the second embodiment of the present invention. Fig. 18 shows the manufacturing steps of the printed circuit board according to the second embodiment of the present invention. 5. Explanation of the invention (24). Fig. 19 is a printed mine according to Example 2 of the present invention. Fig. 20 is a cross-sectional view of the plate. A cross-sectional view of the state of the daughter board on I, I. The 1C crystal placed on the rabbit board is shown in the figure. 4Θ The printed step diagram of the printed circuit board of the second embodiment 2 The drawing shows the manufacturing process of the printed circuit board of the second embodiment of the present invention * The second 3 is a sectional view of the state of the invention sheet f The printed circuit cup of the second embodiment

Circuit board mounting IC, said 24th figure is a printed circuit board diagram of the present invention + the two rows of a state where a corpse wafer is mounted. 〃 1 is the manufacturing steps of the printed circuit board of the third embodiment of the invention. Brother 2 6 Figure repairs the gg diagram. 4 \ Manufacturing steps of the printed circuit board of the third embodiment The figure shows the manufacturing steps of the printed circuit board of the third embodiment of the present invention. FIG. 1 is a manufacturing step of a printed circuit board according to the third embodiment of the present invention. FIG. 4 is a manufacturing step of a printed circuit board according to the third embodiment of the present invention. FIG. Manufacturing steps diagram

2160 ~ 3403-Pf · ptd Page 28 Description of the invention (25) Figure 31 is a cross-sectional view showing the state of the daughter board mounted on 篦 m ®. IC and chip are placed on the printed circuit board. The drawing shows the first to third embodiment of the present invention. The third embodiment is a printed circuit board of the third modified example of the 11th example of the shipbuilding step 11 of the present invention. Example of a printed circuit and a cross-sectional view of the state of 1C Japanese sheet η Manufacturing step diagram Variation of the printed circuit board Fig. 34 shows the manufacturing method of the present invention ^ t Λ Dipping ▲ The first modification of the third embodiment of the invention Steps illustration. Manufacture = Printed circuit board of the first modified example of the third embodiment of the present invention Printed circuit board of the first modified example of the third embodiment of the present invention 4 steps for manufacturing printed circuit board FIG. 38 shows steps for manufacturing printed circuit board according to Embodiment 4 of the present invention FIG. 39 shows steps for manufacturing printed circuit board according to Embodiment 4 of the present invention FIG. 40 shows implementation of the present invention Manufacturing Process of Printed Circuit Board of Example 4 FIG. 41 is a manufacturing process of the printed circuit board of Embodiment 4 of the present invention. FIG. 42 is a sectional view of the printed circuit board of Embodiment 4 of the present invention. Fig. 43 is a cross-sectional view showing a state where a printed circuit board is mounted on the fourth embodiment of the present invention. Figure 44 is an enlarged view of the interposer window 66 in Figure 42 and Figure 44 (B) is the arrow B diagram in Figure 44 (A). Fig. 45 is a diagram showing the manufacturing steps of a printed circuit board I according to a first modification of the fourth embodiment of the present invention. Figs. 4 to 6 are diagrams showing manufacturing steps of a printed circuit board according to the first modification of the fourth embodiment of the present invention. Figures 4 to 7 are diagrams showing manufacturing steps of a printed circuit board according to a first modification of the fourth embodiment of the present invention. Fig. 48 is a diagram showing the manufacturing steps of a printed circuit board j j according to a first modification of the fourth embodiment of the present invention. |

j Fig. 49 is a diagram showing the manufacturing steps of the printed circuit board I according to the first modification of the fourth embodiment of the present invention. Fig. 50 is a drawing showing the manufacturing steps of a printed circuit board according to the first modification of the fourth embodiment of the present invention. Fig. 51 is a diagram showing the manufacturing steps of a printed circuit board according to a first modification of the fourth embodiment of the present invention. Fig. 52 is a cross-sectional view showing an IC chip mounted on a printed circuit board according to the first modification of the fourth embodiment of the present invention.

Fig. 53 is a cross-sectional view showing an IC chip mounted on a printed circuit board according to a second modification of the fourth embodiment of the present invention. [The best mode of the invention implementation] i Embodiment 1; the following 5 will be described with reference to the embodiment of the present invention 3

2150-3403-? [≪ p.30499823 V. Description of the Invention (27) First, a printed circuit board according to an embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 shows a printed circuit. The cross section of the board 10, FIG. 8 shows the state where the 1C chip 90 is placed on the printed circuit board 10 shown in FIG. 7, and the state of the attack is on the side of the daughter board 95. The printing shown in FIG. The circuit board 10 is composed of a core substrate 30 which contains a plurality of wafers, and a wiring layer 8 0 A, 8 0 B. The stacked wiring layer 8 0 A, 8 0 B is a resin layer It is composed of 40 and interlayer resin insulation layers 140 and 14. The upper resin layer 40 is formed with a conductor circuit 58 and an interlayer window 60, and the upper and lower interlayer resin insulation layers 14 are formed. There are conductor circuits 158 and interlayer windows 160, and conductor circuits 159 and interlayer windows ΐβ4 are formed on the upper and lower interlayer resin insulation layers 141. Solder photoresistors are arranged on the interlayer resin insulation layers 141. (Soider resist) layer 70. The superimposed wiring layer 80A and the superimposed wiring layer 80B pass through the through holes 5 formed in the core substrate 30. The chip capacitor 20 is composed of a first electrode η and a second electrode 22 as shown in FIG. 17 (A), and an electromotive body 23 sandwiching the first and second electrodes. A plurality of second conductive electrodes 24 connected to the i-th electrode 2 丨 side and a second conductive film 25 connected to the second electrode 22 side are arranged opposite to each other on the upper side. As shown in FIG. A is provided with solder bumps 76u of pads 92P1 and 92p2 for connection to the 1C chip 90. On the other hand, a solder pad 5 of 94P1 and 94P2 is formed on the lower stacked wiring layer 80B. Bump 76D. The pad 92P1 for grounding of the IC chip 90 is passed through the bump 76U_guide circuit 159-interlayer window 164 -conductor Rabbi ^ isoforged circuit U 8-interlayer window 160-a guide Electricity

2160-3403-Ff-pid

Page 31 499823 V. Description of the invention (28) Road 58-Interlayer window 60 is connected to the chip capacitor 20! Electrode 5l. On the other hand, on the one hand, the pad 94P1 for grounding of the daughter board 95 is via the bump 76D—the dielectric layer window 164—the conductor circuit 158—the dielectric window 160—through hole 56—the conductor circuit 5 8—the dielectric window 60 is connected to the first electrode 21 of the chip capacitor 20. The pad 92P2 for the power supply of the 1C chip 90 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76U-interlayer window 164-conductor circuit 158-interlayer window 160-conductor circuit 58-interlayer window 60. On the other hand, the pad 94P2 of the power source 板 of the plate 95 is connected via the bump 76D-via window 164-j conductor circuit 158-via window 160-through hole 56-via window 60

To the second electrode 22 of the wafer valley state 20. Although not shown, the signal pad of the ic chip is a signal pad connected to the daughter board via a conductor circuit of the printed circuit board, a via window, and a through hole. As shown in FIG. 7, the core substrate 30 of this embodiment is a first resin substrate 3 (^, and a resin layer (adhesive plate) 3) through which a conductive pad portion 34 of a continuous chip capacitor is formed on one side. 8a is connected to the first resin substrate | 30a of the second resin substrate 30b, and the third resin substrate 30c is connected to the second resin substrate 30b through the bonding resin layer (adhesive plate) 38b. The second resin substrate An opening 30B capable of accommodating the chip capacitor 20 is formed on the 3Ob. With this, the chip capacitor 20 can be accommodated in the core substrate 30, and the distance between the IC chip and the chip capacitor 20 can be shortened, thereby reducing the printed circuit. The loop inductance of the board 10. In addition, since the third resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c are laminated, a core substrate 30 with sufficient strength can be obtained. Dubbing & Cap

499823 Description of the invention (29) " ~ ^ '' One resin substrate 30a and third resin substrate 30c smoothly constitute the core base plate 30, and a resin layer 4Q and a conductor circuit 5 are appropriately formed on the core substrate 30. 8, 1 5 8, 1 5 9 can reduce the occurrence rate of defective products on printed circuit boards. I i § In this embodiment, as shown in FIG. 1 (D), the insulating adhesive agent 33 is interposed between the first resin substrate 30a and the chip capacitor 20. Here, the thermal expansion coefficient of the adhesive 36 is smaller than that of the core substrate 30, that is, it is set near the capacitor 20 made of ceramic. Therefore, in the heating cycle test, even if the thermal expansion coefficient occurs between the core substrate i and the bonding layer 40 and the chip valleyr 20! Internal stress, the core substrate is difficult to generate cracks, peeling, etc., and can achieve high j I Reliability. It can also prevent the occurrence of offset. | Continued, the manufacturing method of the printed circuit board described above with reference to FIG. 7 will be described with reference to FIG. (1) A copper foil 3 is laminated on one side of an i-th resin substrate 30a hardened by impregnating a core material such as a glass cloth having a thickness of 0.1 mm with a bismaleic acid | anhydride di Dfazine (BT) resin. The copper laminated laminate of 2 is used as the starting material (see figure i (I)). Ij I:: Then, on the copper foil 32 side of the steel laminated laminate, pattern etching is performed on the first resin substrate. The conductive pad portion 34 is formed on one side of 30a (see Fig. 1 (B)) ....,

丨 #, substrates such as ceramics and ΑΝΝ cannot be used as the core substrate. This · | The soil plate has poor formability and cannot accommodate capacitors. Even with resin i, voids will be generated. After that, I 2), the conductive pad portion 34 is coated with solder using a printer.

2160-3403- ?: Page 33 4 ^ 9823 I. Explanation of the invention (30)-| glue (? &Amp; 37: 6), conductive adhesives, etc. 36 (refer to Figure 1 (^) Figure ' At this time, in addition to 4 coating, it can also be poured (po 11 i ng). The solder paste can use any of Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu. Therefore, the conductive pad Resin filler 33 is arranged between 34 (refer to the figure j (D)). I J Here, as described above, the space between the chip capacitor 20 and the first resin substrate 30 can be filled, and then, i. The pad 34 holds a plurality of ceramic capacitors 20 made of ceramic, and is connected to the capacitor 20 on the conductive pad 34 through the bonding material 36 (refer to FIG. 2 (a)). The chip capacitors 20, one It is also possible to use a plurality of capacitors, but by using a plurality of chip capacitors 20, it is possible to achieve a high accumulation of capacitors. | (3) Next, prepare a core material such as glass cloth (impregnated) in the ring j I ^ The second resin substrate 3ob (thickness J · 4_), the third resin, and the third resin, which are hardened with Bτ resin, are made of a resin layer (a resin layer) 38a, 38b and a core material containing i-impregnated glass cloth. Plate 30c (thickness 0.1 mm). Through-holes 38 A and 30B that can accommodate chip capacitors 20 are formed in the subsequent resin layer 38a and the second resin substrate 30b. First, the third resin substrate 30c is passed through The second resin substrate 30b is placed on the resin layer 38b. Then, the first resin substrate 30a is inverted and placed on the second resin substrate 30b via the bonding resin layer 38a. That is, the second resin substrate 30b is connected to the first resin substrate 3 The chip capacitor 20 of 0a is stacked toward the resin layer 38a, and the chip capacitor 20 is accommodated in the through-hole formed in the second resin substrate 30b (refer to FIG. 2 (B)). As a result, the core can be provided. The substrate 30 can house chip capacitors and reduce the circuit inductance of the printed circuit board.! (4) So, using hot extrusion and pressure to squeeze the stacked substrate, and 499823 V. Description of the invention (31 ) The first, second, and third resin substrates 30a, 30b, and 30c are multilayered and integrated to form a core substrate 3 0 having a plurality of chip capacitors 20 (see FIG. 2 (C)) 5 An epoxy resin composed of resin layers 3 8a and 38 Edge resin), and fill the gap between the opening 30B and the chip capacitor 20. In addition, the epoxy resin is hardened by heating at the same time as the pressure, and the resin layers 38a and 38b are then interposed with the resin. The first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c are firmly adhered. Furthermore, in this embodiment, the opening 3 is filled with epoxy resin that overflows from the resin layer. The gap in 〇B, but instead, a filler may be arranged in the opening 30B. Here, since both surfaces of the core substrate 30 are the smooth first resin substrate 3 0 a and the third resin substrate 3 0 c, the smoothness of the core substrate 3 is not impaired. In the steps to be described later, the core substrate 3 can be appropriately The formation of the resin layer 4 on the 〇 and the conductor circuit 58 can reduce the incidence of defective products on the printed circuit board. In addition, a core substrate 30 of sufficient strength can be obtained. (5) After the substrate 30 having undergone the above steps, the substrate 30 is heated to 50 ° to 15 °° C and laminated under vacuum at a pressure of 5 kg / cm2, and an interlayer resin insulation layer 40 is provided (see FIG. 2 (D)). The degree of vacuum during vacuum pressing was 10 _ {^. |

I I Φ

(6) Next, an interlayer window opening 42 for forming a conductor bushing portion 34 is formed on the interlayer resin insulating layer 40 and the first resin substrate 30a by a laser (refer to Section 3 (A ) Figure). (7) Then, a through hole 44 is formed in the core substrate 30 by drilling or laser (see FIG. 3 (B)). After that, an oxygen plasma was used to remove the residue. Or use a chemical solution such as peracid to remove the residue.

2160-3403-Fi * ptd Page 35 V. Description of the Invention (32)-Next, SV-4540 manufactured by Japan Vacuum Technology Co., Ltd. was used to investigate, investigate, and form a roughened surface 46 on the entire surface of the core substrate 30. Day j: Plasma treatment was performed for 2 minutes using lice gas as an inert gas under the conditions of electric power 200W, gas pressure G. and ^ C. After that, Ni and 7 are used as dry materials to form low-grade ore, and the surface of the interlayer resin insulation layer 40 is formed with 2Λ 丄 (see Figure 3 (c)). Here, you can use splash hunting, t After electroless plating forms metals such as copper and nickel π i, i ^ ί After formation of sputter plating, electroless plating may also be formed, and σ1 biting oxidant may be subjected to roughening treatment. In addition, the roughened layer is preferably b / zm 〇7 Photometric (: film connection: load = cover% metal film 48 on the surface of the photoresist 50 with a predetermined pattern on the market, and exposure and development processing 'The forming plate 30 is immersed in the electrolytic cell (3_ (D) diagram). Therefore, a current is flowed through the core base in the photoresistor 50 non-ferrous metal layer * Nl-CU under the following conditions, and the coating 52 (refer to Section 4 ( A, 1 ^ into the electrolytic plating, forming electrolytic electricity (a, a) Figure) [Electrolytic plating aqueous solution ^ copper sulfate copper sulfate coating film 0 · Φ additive 2.24mo1 / 1 0 · 26 mol / 1 HL) .y Company Manufacturing force eight 5κ 19.5 mo I / 1 1 A / d m2 1 2 0 minutes [Electrolytic plating conditions] Current density time

2160-3403-Pf-ptd p. 36 499823

2 2 ± 2 〇C V. Description of the invention (33) Temperature (10) Peel off the photoresist 50 at 5% N a Η Η, and then etch the resistance 50 times with a mixture of nitric acid and sulfuric acid and hydrogen peroxide The Mi-Cu layer 48 was dissolved and removed | removed to form a 16 I through-hole 56 and a conductor circuit 58 (including the interlayer window 60) composed of the Ni-Cu layer 48 and the electrolytic copper plating film 52. Γ 于 | j 疋 水洗After the substrate is dried, the remaining etching liquid is blown on both sides of the substrate, and the surface of the through-hole 56 and the conductor circuit 58 (including the interposer window 刻) is etched by j, and the through-hole 56 and the conductor circuit 58 (including the dielectric circuit) A roughened surface 62 is formed on the entire surface of the layer window go) (see FIG. 4 (B)). The etching solution is made of taste! 丨 Salt copper (II) composite body is composed of 10 parts by weight, 7 parts by weight of glycolic acid, and 5 parts by weight of sodium chloride. (11) Fill in the through-hole 56 The resin i filler 64 containing epoxy resin as a main component is dried by heating (see FIG. 4 (c)). (12) After that, using the thermosetting epoxy resin sheet of step (5), the interlayer resin insulating layer 140 is provided by heating the layer to 50 to 150 ° C and pressing the layer 真空 under a pressure of 5 kg / cm2 under vacuum (see Section No. 4 (D) figure). The vacuum degree when 9 is true is 10 mmHg. 〃 工 g Stomach! (13) Next, an interlayer resin insulating layer 140 is formed with a laser * | mouth opening 142 (see FIG. 5 (A)). ^ Window

(14) Afterwards, 'by repeating the steps (8) to (1Q) above, the Ni-Cu metal layer 1 4 8 is formed on the resin insulation layer 1 4 0 and the thickness of the electrolytic power ore gland 16 is 16 Bandit's conductor circuit 158 (including vias 160, 152; roughened surface 158α (see Figure 5 (B)). And (15) Repeat steps (12) to (14) to form the upper layer. Interlayer tree shrew

499823 I. Description of the invention (34) I The insulating layer 1 4 1 and the conductor circuit 丨 5 9 (including the interlayer window 丨 g 4) are used to roughen the surface 159 a (refer to Figure 5 (c)). (16) Subsequently, 50% of the epoxy group of the cresolase-type epoxy resin (manufactured by Japan Chemical Co., Ltd.) is dissolved in DMDG at a concentration of 60% by weight in an alkylated, low-sensitivity polymer ( 1 igomer) (molecular weight 4000): i 46.67 parts by weight, 80% by weight of bisphenol a-type ring dissolved in fluorenyl ethyl ketone | Oxygen Mould (Oilification >, Manufacturing, Epi cote 1001) 15. 0 parts by weight, bee sclerosing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN:) 1.6 parts by weight, polyvalent alkyl monomers with photosensitive monomers (manufactured by Benwa Chemicals, R6 04 ) 3 parts by weight, the same polyvalent alkyl monomer (Kyoeisha Chemical Co., Ltd., DPE6A) _ 1 · 5 parts by weight, dispersing defoamer (manufactured by Daimon Daimon 3, S-65) 〇 71 weight In the container, stir and mix to adjust the mixing composition, and then add the photoinitiator benzophenone I (made by Seki Chemical Co., Ltd.) to the above mixture. 2 parts by weight, the photosensitizer Michelinone jMlchler 's ketone) (manufactured by Kanto Chemical) 0.2 parts by weight, and a solder resist composition (with a viscosity of 2 5 C adjusted to 2 · 〇pa · s (with Resin insulating material). In addition, the viscosity measurement is based on a B-type viscosity meter (manufactured by Tokyo Keiki Co., Ltd., DVL-B type). At 60 rpm, the rotor ν ·· 4 and 6 rpm are converted.

丨 No · 3. * WJ (1Ό Next, apply the fresh tin photoresist composition on the two sides of the substrate 30 at a thickness of 20 / zm, and then dry the film at 70 t for 20 minutes and 70 ° C for 30 minutes. A # degree 5mm mask with a pattern of solder resist openings is tightly adhered to solder resist layer 70 and exposed to 1000 m J / cm2 ultraviolet rays τ

2160-3403-? F · 〇td Page 38 499823 V. Description of the invention (35) Light, developed with DMTG solution, t 71U, 71D (refer to Figure 6 (A): 200, diameter, opening (18) Next, the substrate on which the film 70 is formed is immersed in a sodium chloride-containing resist (organic resin insulating layer) sodium α.δχΙΟ— ^ οΙ / ΐ), ^ .3xl0_lmoi / 1), In the electroless plating solution of hypophosphite 4.5, the acid / (= xl ~ 1/1), a nickel plating layer with a thickness of 5 7 7 ΓΛ 钟 将 'open σ, 71D shape (7.6xl0, .l / 1 ) 'Second general: Helium Electrolyte Batteries containing gold cyanide and potassium cyanide) and: Human Sodium Phosphite (1.7xl0-imol /: [) were immersed for 7 5 minutes at 80 t. Then, a gold plating layer 74 having a thickness of 0.03 mm is formed on the recording power 72 (refer to the figure (19), and then a solder paste is printed on the openings 7111 and 710 of the solder resist layer 70. It is melted (refl0w) at 200 to form solder bumps | 7t > U, 76D. Thereby, a printed circuit board 10 having solder bumps 7611 and 76D can be obtained (see FIG. 7). Next, Referring to FIG. 8, description will be given to the 1C wafer to be printed to complete the above steps. The circuit board 10 and the sub-board 95 are mounted. The 1 (: wafer 90's fresh tin linings 92P1 and 92P2 are corresponding to the solder bumps 76U of the completed printed circuit board 10, and a 1C chip 90 is placed thereon. The IC chip 90 is mounted by performing a soft solution. Similarly, the pads 94P1 and 94P2 of the daughter board 95 are corresponding to the solder bumps 76D of the printed circuit board j 〇, and the printed circuit board is subjected to a soft solution. Mounted to the board 95 〇j The above resin film contains hardly soluble resin and soluble particles

2160-3403-Fi -ptd

For chemical agents and other ingredients, the following explanations are used in the t :: $: method. The resin thin m used in the method is the acid or oxidant T is Sanco > Gu Lazi (the remaining loss, ^ ^ chemical agent). Disperse poorly soluble resin (two particles), or in acid or hydration, the so-called present invention; "m capacitive resin). At the same time, it is immersed in the same kind of hydration, "soluble", which is the abbreviation of fast dissolving speed & "when it is in solution", which is relatively difficult to dissolve. "", And the above-mentioned soluble particles having a relatively slow dissolving speed are, for example, _ I · particles (hereinafter, soluble resin particles) 4 ^ soluble resin granule particles (hereinafter, soluble inorganic particles "= in the agent = neutral none Metal particles + (hereinafter, soluble gold particles can be used alone, or two or more of them can be used in combination), etc .... bath particles such as spherical and broken shapes. The shape of the flakes is not particularly limited. ^: The shape of the soluble particles is preferably ',,,' >: Roughened surface having unevenness with average thickness. The normal particle size is preferably °. 1,-. The average particle size of the particle size is. There are 5 two: to: two with the same particle size. That is, it contains excellent soluble particles such as flat soluble particles and amphoteric particles with an average particle diameter of 3㈣: the roughened surface, and the conductor The length of the longest part of the circuit-soluble particles.... The particle size of the cereal particles is soluble by the fat. === Thermosetting resin, thermoplastic tree is immersed in a solution composed of acid or reducing agent.

i V. Description of the invention (37) It is particularly limited to a resin / mixture of resins composed of the above-mentioned soluble fats, polyurethanes, and the like. The above-mentioned rubber, (meth) rubber with a methacrylic acid is soluble. Finally, it is dissolved with an acid to dissolve a relatively weak concentration. As a general rule, the surface agent is roughened, and the catalyst is not as described above. The above-mentioned difficult resin resin, which is composed of a group of soluble compounds and | bow compounds, may also be used. Examples of the soluble resin are acrylonitrile-based) acrylic resins. Inorganic inorganic, If-formed particles, the dissolution of the tree particles is selected from thin resin particles such as polybutadiene modification, etc., particles become soluble, soluble agents dissolve salts, and resins are dissolved. For example, a resin based on a resin and a polymer of a polysaccharide can also use a diene rubber or various modified butadiene rubber-soluble rubber solutions to dissolve the resin particles when dissolving the resin particles. In addition, there are no acids or chlorides used, for example, at least the magnesium compound is higher. · Such as bad oxygen resin, phenol resin, fluorine tree species, or two kinds of rubber group, epoxy to polybutadiene, etc. It can also be used by acid or by particles. When it is chromic acid, it is oxidant. When it is catalyst, resin particles, urethane rubber, etc. are used. It can be oxygen or low residue other than strong acid. After that, a compound selected from the group consisting of aluminum compound and silicon compound mentioned above is given as an example. Younu red — for example, thorium carbonate, hydroxide 4 #weathering Shao, etc. ' The above-mentioned compound may be potassium acid, the above-mentioned compound may be carbon, chloro-basic magnesium carbonate, etc., the above-mentioned milk, white, stone (do1⑽ite (zeonte), etc.) may be mentioned, for example ⑦, sea stone early alone, you can also use two or more.

-I. V. Description of the invention (38) The above-mentioned soluble metal particles may be, for example, at least one lead, dilead, lead, gold, silver, aluminum, magnesium calcium = steel, nickel, and sub-Xun. In addition, the above-mentioned soluble metal particles may be coated with a resin on the surface layer for the purpose of forming particles with a composition. The combination of the above-mentioned soluble particles and the use of two or more kinds of soluble particles. The combination of e = particles is preferred. The resin particles and the inorganic particles are low in conductivity, so the resin film can be ensured in both places. The thermal expansion between the adjustment and the poorly soluble resin does not occur: it is easy to peel off between circuits. The insulation layer and conductor are described as insoluble resin on the interlayer insulation layer. When forming the roughened surface, as long as it can maintain the shape of the roughened surface, such as thermosetting resin, thermoplasticity, etc. Resin, the above compound & = 树脂 is a photosensitive resin which imparts the sensitivity of the above resin. By using the grease, an opening for an interposer window can be formed in the interlayer resin insulating layer by exposure and development processing. Among the above, those containing a thermosetting resin are preferred. Thereby, the shape of the roughened surface can be maintained even with a plating solution or various heat treatments. # Specific examples of the above-mentioned poorly soluble resin are, for example, epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin, fluorine resin, and the like. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in the molecule is preferred. It can form the aforementioned roughened surface, and is also excellent in heat resistance, etc.

HI IMI Page 42 2160-3403-Pi.ptd 499823 V. Description of the invention (39) ^ = Under the condition, there will be no stress concentration in the metal layer, and it is difficult to cause the metal layer to peel off. 1 Today's epoxy resins can be cresol phenolic solid i ^ c ^ Oiak 'type Emulsion resin' bisphenol A type epoxy resin, bisphenol f = biphasic type epoxy resin, Burning radicals: type milk ίί 、 =, condensation of aromatic aldehydes with phenols and phenolic hydroxyl groups, etc., tricid (glycidyi) heterotrimer _ 口 物 ayanurate), wax ring epoxy Resin, etc. The above can be used alone or in combination. Thereby, it can be excellent in heat resistance. '、 了 _ ^ In the resin film used in the invention, the above-mentioned soluble particles are almost evenly dispersed in the above-insoluble resin, and the roughened surface is uneven, and it can also be exposed outside the tree with no acid or oxidant. The two-layer part is insulated with a fatty insulating layer between conductor circuits. ",,, '' The interlayer tree resin resin described above, the blending amount dispersed in the poorly soluble resin is preferably 3 to 40 weight percent of the resin film. If the desired surface cannot be formed, and if it exceeds 40% by weight, when using a coarser of acid or oxygen, it cannot be dissolved in the deep part of the resin film, and the _ place: the conductor of the interlayer resin insulation layer composed of the soluble granular film Between circuits ::

2160-3403-Pi.ptd p. 43

Cause of short circuit. In addition to the above, it is preferable to contain a hardener, other components, etc. in addition to the above-mentioned soluble particles and the above-mentioned poorly soluble resin. Examples of the above hardener include bee saliva-based hardener, guanidinej-based hardener !, h ^, ^ ^ adduct ^^ capsule ^ ^ ^ P_Γ. ephosphlne), organophosphine compounds such as tetraphosphonium phosphonium and borate, and the like. The content of the hardener is preferably from 0. 0 to 5 to 0. 0% by weight of the resin film, and 0. 0 to 55% by weight. k 'The resin film is not sufficiently hardened. Therefore, the acid% agent is known to be incorporated into the resin film. The degree is increased, and the resin film is damaged: ^. On the other hand, when it exceeds 10% by weight, an excessive amount of the hardener component deteriorates the composition of the resin, leading to a decrease in reliability. The other components mentioned above include, for example, fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. Examples of the inorganic compound include silicon, aluminum, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic acid I resin, polyimide resin, polystyrene resin, melanin resin, and olefin. Department of resin and so on. By including the filler ′ described above, it is possible to achieve integration of thermal expansion coefficients and increase in heat resistance and chemical resistance, etc., thereby improving the performance of printed circuit boards. The resin filler may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone; ethyl acetate, butyl acetophenone, cellosolve acetate, and aromatic hydrocarbons such as benzene and xylene. The above can be used alone or in two types

2160-3403-Pf-ptd Page 44

Used above. (First Alternative Example of Embodiment 1) A printed circuit board according to a first alternative example of Embodiment 1 of the present invention will be described with reference to FIG. 9. A printed circuit board according to a first alternative example of the first embodiment is substantially the same as the first embodiment. However, the printed circuit board of the first alternative example is formed by disposing a conductive pickup 296 and obtaining a connection state with a daughter board via the conductive bolt 296. Further, in the above-mentioned first embodiment, only the chip capacitor 20 accommodated in the core substrate 30 is provided, but the first alternative is to mount a large-capacity chip capacitor 86 on the surface and inside. The 1C chip consumes large amounts of power instantly and performs complex calculations. Here, in order to supply large power to 1C chip, No.! Another example is a chip capacitor 20 and a chip capacitor 86 provided on a printed circuit board with both power sources. The effect of this chip capacitor will be described with reference to FIG. 12. In Fig. 12, the vertical axis is the voltage supplied to the c-chip, and the horizontal axis is time. Here, the two-dot chain line C shows the voltage fluctuation of the printed circuit board without the power supply capacitor. If there is no power supply capacitor, the large voltage will be reduced. A dotted line A indicates a change in electric f of the printed circuit board of the surface mount chip capacitor. Compared with the two-point chain line described above, the voltage does not decrease significantly. However, due to the increase in the length of the loop (100), rapid power supply cannot be performed sufficiently. That is, when the supply of electric power is started, the voltage drops. In addition, as shown in FIG. 8, the two-dot chain line B indicates that the voltage of the printed circuit board having the above-mentioned chip capacitor is decreased. The loop length is shortened, but because a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage varies. Here, ^

499823 V. Description of the invention (42) Line E shows the voltage variation of the printed circuit board in the first example of the chip capacitor 20 in the above-mentioned core substrate with reference to FIG. 9 and the large-capacity chip capacitor 86 on the surface. . There are chip capacitors 20 near the IC chip, and chip capacitors 8 6 with a large capacity (that is, relatively large inductive reactance), and the voltage variation is minimized. (First Modified Example of Embodiment 1) ϊ f I Continuing, a method of manufacturing a printed circuit board according to a modified example i of the first embodiment of the present invention will be described with reference to FIG. 11. The printed circuit board of the first modification is substantially the same as the first embodiment described above. However, in the printed circuit board 14 of the first modification, the conductor circuit 5 is formed on one side of the first resin substrate 30a and the third resin substrate 30c, and the second resin substrate is provided with an opening 30B for receiving the chip capacitor 20 Conductor circuits 37 are formed on both sides of 3Ob. In the first embodiment, the conductor circuit 35 is formed on one surface of the first resin substrate 30a and the third resin substrate 30c, and the conductor circuit 37 is formed on both surfaces of the second resin substrate 30b. Therefore, the wiring density can be increased and the overlap can be reduced Advantages of the number of layers of the interlayer resin insulating layer. In addition, the first modified example of the printed circuit board 5 chip capacitor 2 is as shown in FIG. 13 (A). After the third electrode 21 and the second electrode 2 2 are completely peeled off, the coating layer (not shown) Covered with a copper plating film 29. Therefore, the first and second electrodes 21 and 22 electrically connected to the copper plating film 29 are obtained through the interlayer window 50 formed by copper plating. Here, the electrodes 21 and 22 of the chip capacitor have irregularities on the specific surface of the metallized composition. On the other hand, in the first modification, the surface of the first and second electrodes 21 and 22 is smoothed by the steel plating film 29, so that the capacitor electrode is not deflected without causing displacement. 499823 V. Description of the invention (43) ------ Furthermore, the above-mentioned copper plating film 29 is a stage of the printed circuit board mounted on the substrate, and the manufacturing stage of the chip capacitor is covered on the metal layer 26. The nickel / tin layer on the surface is peeled away. Alternatively, at the stage i of the manufacturing stage of the chip capacitor 20, the copper plating film 29 may be directly coated on the metal layer 26. That is, in the first modification, a laser is provided to the opening of the steel plated film 29 of the electrode, and then a residue removal process is performed to form a via window by copper plating. Therefore, an oxide film is formed on the surface of the copper plating film 29, and the oxide film is removed by the above-mentioned laser and I residue removal treatment, so that proper contact can be obtained.丨 Furthermore, as shown in FIG. 13 (B), a part of the i-th electrode 21 and the second electrode 22 of the second electrode 22 with the capacitor 20 removed may be used. Min Yefei The exposure of the second electrode 22 and the second electrode 22 can improve the continuity, because a roughened layer 23 α can also be provided on the surface of the electric capacitor 23 of the ceramic capacitor of the chip capacitor 20. Therefore, the chip capacitor with ceramic composition and the first resin substrate 30a with a resin composition are improved in adhesion, and even if the heating cycle I test is performed, the first resin substrate 30a does not peel off at the interface. This roughened layer 23a is formed by polishing the surface of the wafer capacitor 20 after firing, or by roughening it 5 before firing. In addition, the first modified example improves the adhesion with the resin by roughening the surface of the capacitor, but may instead apply a silane coupling treatment to the surface of the capacitor. The manufacturing steps of the printed circuit board according to the first modified example of the present invention will be described with reference to Figs. 10 and 11. (1) A first resin substrate 30a is prepared by impregnating a core material such as glass cloth having a thickness of 0.1 mm with BT resin and hardening it. On the first resin substrate 30a,

2160-3403-Fi-ptd p. 47 499823

15. Explanation of the Invention (44) A conductive pad portion 34 is formed on one side, and a conductor circuit 35 is formed on the other side. Next, a plurality of chip capacitors 20 are soldered to the conductive pad portion 34 and placed on the conductive pad portion 34 via a bonding material 36 such as a conductive adhesive, and the chip capacitors 20 are connected to the conductive pad portion 34 (see FIG. 10 (A)). I, 2) The recipient's heart is prepared by impregnating the heartwood such as glass cloth with epoxy resin, and then the resin layer (then the resin layer is dipped) 38a, 38b and the heartwood impregnated with glass cloth and other materials are hardened with BT resin. 2 resin substrate 30b (thickness: 0.4mm), and third resin substrate 30c (thickness: 0.1mm). On the subsequent resin layer 38a | and the second resin substrate 3 0 b, a through hole m | 38 3, 3 (^.) For accommodating the chip capacitor 20 is formed on both sides of the second resin substrate 301. ! 路 37 'A conductor circuit 35 is formed on one surface of the third resin substrate 30c. First, the second resin substrate 30b is placed on the surface of the third resin substrate 30c on which the conductor circuit 35 is not formed, followed by a tree-moon layer 38b. The first resin substrate 30a is inverted and placed on the second resin substrate 30b via the resin layer 38a for bonding. In other words, the chip capacitor 20 connected to the first resin substrate 30a is stacked toward the resin layer 38a, and the chip capacitor 20 is accommodated in the through-hole formed in the second resin substrate 30b (see No. 10). (B)). (3) Then, the overlapped substrates are pressed by hot pressing, and the first, second, and third resin substrates 30a, 30b, and 30c are integrated in multiple layers to form a plurality of chip capacitors. 2 Core substrate 3 〇 (refer to Figure 1 〇 | (C)). First, an epoxy resin (insulating resin) composed of resin layers 1 3 8 a and 3 8 b is pressed out by pressing around, and the opening is filled! . In addition, at the same time as pressing, a thermosetting bad oxygen resin ’is added, and the resin layers 3 8 a and 3 8 b are used as the bonding resin.

2160-3403-?]-Ptd page 48 499823 V. Description of the invention (45)! 叩 ’! In between, the third resin substrate 30a and the second resin-based substrate 30b and the third resin substrate 30c are firmly adhered.

After passing through the above steps, the substrate 30 is heated to 50 to 150 ° C and laminated with a vacuum pressure of 5 kg / cm2, and an interlayer resin insulation layer 40 is provided (Mai Zhao No. 10 (D)). The vacuum degree at the time of vacuum pressing is 10 mmHg 〇 (5). On the top and bottom of the substrate 30, a laser is used to form an opening 42 for an interposer window connected to the conductor pad portion 34 and the conductor circuits 35 and 37 ( Refer to Figure 10 (E)). The following steps are the same as (7) to (9) of the above-mentioned first embodiment, so the description is omitted. (Second Modified Example of Embodiment 1) The configuration of a printed circuit board according to a second modified example of Embodiment 1 will be described with reference to Figs. The structure of the printed circuit board of the second modification is substantially the same as that of the first embodiment. However, the chip capacitor 2 stored in the core substrate 3 is different. Figure 14 shows a plan view of a chip capacitor. Figure 14 (A) shows a plurality of chip capacitors taken before cutting, and a chain line in the figure shows the cutting line. In the printed circuit board of the first embodiment described above, the first electrode 21 and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of FIG. 14 (B). Fig. 14 (C) shows a plurality of chip capacitors used in the second modification. A chain line in the figure shows a cut line. In the printed circuit board of the second modification, the first electrode 21 and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of FIG. 14 (D).

2160-3403-Ff-ptd Page 49 499823 "Fifth, the description of the invention (46) '-! _ The printed circuit board of the modified example uses the chip capacitor 1120 formed on the inner side of the outer edge of the 纟, so a large capacity can be used. The chip capacitor cries. Continuing, a circuit board of a second modification of the second modification will be described with reference to FIG. 15.

Fig. 15 is a plan view showing a chip capacitor 20 housed on a core substrate of a printed circuit board of the i-th example. In the first embodiment described above, a plurality of small-capacity chip capacitors are housed on a core substrate, but the first other example is a large-capacity large-scale chip capacitor 20 being housed on a core substrate. Here, the chip capacitor 20 includes a first conductive film 24 ′ connected to the first electrode 21 and a second electrode 22, and an electric inducer 23, and a second conductive film 25 connected to the second electrode 22 side. It is composed of electrodes 27 for connection to the upper and lower surfaces of the chip capacitor which are not connected to the first conductive film 24 and the second conductive film 2b. The IC chip side and the daughter board are connected through the electrodes 27. ^ The printed circuit board of the modified example of 5 daddy 1 is because a large-scale chip is used. Gu Yi 20 ′ can use a large-capacity chip capacitor. In addition, because a large chip capacitor 20 is used, even if the heating cycle is repeated, the printed circuit board does not bend.

The printed circuit board of the second alternative example will be described with reference to FIG. 16. Figure 16 (A) shows most of the chip capacitors taken out. A chain line in the figure shows the general cutting line. Figure 16 (B) shows the plan view of the chip capacitor. As shown in Fig. 16 (B), this second example uses a large number of chip capacitors connected to a plurality (the example in the figure is three) and uses a large-scale chip capacitor.

2160-3403-ff.〇td Page 50 Large-capacity chip capacitors 20, even if the heating is repeated. In addition, because of the use of large-sized wafers and capacitors, the above-mentioned embodiment does not bend on the printed circuit board. However, it is also possible to use a chip capacitor built in a printed circuit board instead of a chip capacitor. A plate-shaped capacitor in which a conductive film is provided on a ceramic plate. According to the device of the first embodiment, the 1C chip method can be shortened, and the capacitor's circuit sense can be stored in the core substrate. + The distance from /, the valley state can reduce the core substrate of the printed circuit board: and the core board can be obtained with sufficient strength due to the laminated resin substrate. On the q1, the first resin base is arranged on both sides of the core substrate. : The plate forms the core substrate smoothly, so the core #double 2 can be filled with resin between the core substrate and the capacitor. Therefore, even if stress due to the capacitor occurs, it can be alleviated without shifting. , ^ = Will affect the glass and dissolution of the junction between the capacitor electrode and the interlayer window. Therefore, reliability tests can be performed to maintain desired performance. Also, when the capacitor is coated with copper, the occurrence of offset can be prevented (Embodiment 2)! First, a printed circuit board according to Embodiment 2 of the present invention will be described with reference to Figs. 19 and 20. FIG. 19 shows a cross section of the printed circuit board 210, and FIG. 20j shows a state where the iC chip 29 is mounted on the printed circuit board 210 shown in FIG. 7 and is mounted on the side of the daughter board 295. The printed circuit board 21 0 shown in FIG. 19 is composed of a plurality of wafers.

2160-3403-Pi ptd Page 51 499823 V. Description of the Invention (48)

The core substrate 230 of the capacitor 220 and the overlay wiring layers 280A and 280B are formed by the overlay wiring layer 28 (^ and the overlay wiring layer 28 (^ are connected through the through-holes 2 56. The overlay wiring layers 280A and 280B are formed by Interlayer resin insulation layers 240 and 340. Interlayer resin insulation layer 240 on top of superimposed wiring layer 28a is formed as a dielectric layer that is connected to conductor circuit 358 and first electrode 221 and second electrode 222 of chip capacitor 220. The window 260 and the interlayer resin insulating layer 340 are formed with the conductor circuit 3 58 and the interlayer window 360. On the other hand, the conductor circuit 258 is formed on the interlayer resin insulating layer 240 on the side of the superimposed wiring layer 280B side, and the interlayer resin A conductor circuit 358 and a via window 360 are formed on the insulating layer 340. A solder photoresist layer 27 is formed on the interlayer resin insulating layer 340 of the stacked wiring layers 280 A and 280B. The chip capacitor 220 is shown in FIG. 19 The first electrode 221 and the second electrode 222 shown are composed of an electrophoretic body 23 sandwiching the first and second electrodes, and a plurality of first conductive films connected to the first electrode 221 are arranged on the electromotive body 23 oppositely. 224, connected to the second electrode 222 side The second conductive film 225. As shown in FIG. 20, a solder bump 276U of pads 292E, 292P, and 292S for connecting to the 1C chip 290 is arranged on the upper layer of the wiring layer 28a. On the other hand, solder bumps 276D for pads 294E, 294P, and 294S that are connected to the daughter board 295 are formed on the superimposed wiring layer 28〇β on the D side. * As shown in FIG. 20, the signal of the 1C chip 290 The pad 292S used is a pad 294S for signal connection to the daughter board 295 via the bump 276U-conductor circuit 358-interlayer window 360-through hole 256-interlayer two® port 360-solder bump 276D.

499823 V. Description of the invention (49) The pad 292E for grounding of the 1C chip 290 is connected to the first electrode of the chip capacitor 220 via the bump 276 U: interlayer window 360-conductor circuit 2 5 8-interlayer window 260 221. On the other hand, the ground pad 294E of the daughter board 295 is connected to the second electrode 222 of the chip capacitor 220 via the bump 2 76D-the via window 360 -the through hole 2 56 -the via window 260. The pad 29 2P for the power supply of the IC chip 290 is connected to the second electrode 222 of the chip capacitor 220 via the bump 276U-interlayer window 360-conductor circuit 258-interlayer window 260. On the other hand, the pad 29 4P for power supply of the daughter board 295 is connected to the second electrode 222 of the chip capacitor 220 via the bump 276D-the via window 360-the through hole 256-the via window 260. As shown in FIG. 19, the core substrate 230 of this embodiment is connected to the second resin substrate 230a from the first resin substrate 230a to the second resin substrate 230a through the first resin substrate (adhesive plate) 238a. The resin substrate 230b is composed of a third resin substrate 230c that is connected to the second resin substrate 230b via the adhesive resin layer I (adhesive plate) 238b. In addition, the first resin substrate 23a, the second resin substrate 230b, and the third resin substrate 230c are processed with counterbore to form a recessed portion 334 that can accommodate the chip capacitor 220, and the recessed portion 334 accommodates the chip capacitor 220.

Thereby, the chip capacitor 220 can be accommodated in the core substrate 230, and the distance between the IC chip 290 and the chip capacitor 220 can be shortened, so that the loop inductance of the printed circuit board 210 can be reduced. In addition, the core substrate 23 is formed by laminating the first resin substrate 230a, the second resin substrate 230b, and the third resin substrate 230c on which conductor circuits 235 are arranged on both sides, thereby improving the core substrate 23〇 |

The internal wiring density 'can also reduce the number of interlayer resin insulating layers. II § ΙΚΒΙΙ ΙΗ1II 2160-3403-? I-pid Page 53 499823 V. Description of the invention (50) I In addition, "exemplary 2" is shown in Fig. 18 (A), and the adhesive 2 3 6 j is introduced Between the lower surface of the through hole 34 of the core substrate 230 and the chip capacitor 22

^ Fill the resin filler between the side of the through hole 337 and the chip capacitor 22. 2 3 3. Here, "the thermal expansion coefficient of the adhesive 2 3 6 and the resin filler 2 3 6 is smaller than that of the core substrate 2 3 0", that is, set near the capacitor 2 2 0 of the ceramic composition. Therefore, in the heating cycle test, even if internal stress caused by the thermal expansion coefficient occurs between the core substrate 230 and the chip capacitor 220, the core substrate 23 is less likely to generate cracks and peeling, and high reliability can be achieved. And, I! Stops the offset from occurring. Continued 'The method of manufacturing the printed circuit board described above with reference to Figs. 9 to 9 will be described with reference to Figs. (1) Copper sheet laminates with copper foil 232 laminated on both sides of a resin substrate 231a hardened by impregnating βτ resin with a core material such as glass cloth with a thickness of 0.3 mm |! 231M as the starting material (refer to Section 17 (Eight ) Figure). The copper foil 232 of this copper laminated layer ij plate 23 li is engraved with a pattern-like surname to form first, second, and third resin substrates 23a, 23b, and 23 having a conductor circuit 235 on both sides. 0c (Figure 17 (B)). Then, the third resin substrate 23c and the second resin substrate 230b are impregnated with a core material such as glass cloth and impregnated with an epoxy resin, and then a fat layer 238b is laminated. Similarly, the 2nd resin substrate 23A and the 1st month substrate 230a are laminated | stacked via the adhesive resin layer 238a. (Figure 17 (c ϋ)). Furthermore, substrates such as ceramics and ΑΝΝ cannot be used as the core substrate. This substrate has poor formability and cannot accommodate capacitors. Even if it is filled with resin, voids are generated. ,

Page 54 499823 V. Description of the invention (51) (2) Then, the superimposed base # plates are pressed by hot pressing and the first, second, and third resin substrates 230a, 2 30b, and 230c are pressed. The multilayer substrate is integrated to form a core substrate 230 (see FIG. 17 (D)). Here, firstly, the epoxy resin (insulating resin) 5 using the resin layers 238a and 238b is then pressed out by pressing to make the first, second, and third resin substrates 230a, 2 3 0 b, 2 3 0 c close. In addition, the epoxy resin is hardened by heating at the same time as the pressure, and the resin layers 238a and 238b are used as bonding plates therebetween, and the first resin substrate 2 30a and the second resin substrate 230b and the third Resin substrate 230c. I (3) Next, the core substrate 2 30 is processed by countersinking to form a receiver.

The concave portions 334 of both the capacitor capacitors 220 (FIG. 17 (E)). Here, a recessed portion for accommodating a capacitor is provided by countersinking, but a core substrate including a accommodating portion may be formed by bonding an insulating resin substrate provided with an opening and a resin insulating substrate without an opening. (4) Then, the bottom surface of the recessed portion 334 is coated with a thermal j-curing or UV-curing bonding material 2 36 using a printer (Fig. 18 (A)). In this case, 'in addition to coating, it may be poured. Next ', a chip capacitor 220 is placed on the bonding material 236 (No. 18 stomach (Bj picture). The chip capacitor 22 may be one or plural, but

(2) By using a plurality of chip capacitors 2205, a high integration of the capacitor can be achieved. (, 5) After that, the thermosetting resin is filled in the recessed portion 334, and heated to form a resin layer 233 (Fig. 18 (C)). In this case, the thermosetting resin is preferably epoxy, phenol, polyimidazole, or trioxane. Thereby, it is fixed to the recess

2160-3403-Fi.ptd Page 55 499823 5. The chip capacitor 220 in (52) 334 of the invention description, and the gap between the chip capacitor 220 and the wall surface of the recess 334 is filled. (6) The substrates 2 to 30 after the above steps are heated to 50 to 150 I ° C while being laminated by vacuum pressing at a pressure of 5 kg / cm2, and an interlayer resin insulation I layer 240 is provided (see FIG. 18 (D)). . The steps after the vacuum pressing are 110 mmHg ° and subsequent steps are the same as the steps (7) to (9) of the first embodiment, so the description is omitted. Next, referring to Fig. 20, the description will be made as to placing the IC chip 290 on the printed circuit board 21 which has completed the above-mentioned steps, and mounting the IC chip 290 on the daughter board 295. The solder bump 276U of the completed j printed circuit board 210 corresponds to the solder lining of the 1C chip 290 | 搴 i pad 29 2E '29 2P, 29 2S, and the IC chip 290 is placed to perform ic with soft solution, and the chip 2 9 0 installation. Similarly, the solder bump 276D of the printed circuit board 21 0 is mounted on the daughter board 2 95 by soldering in accordance with the solder pads 294E, 294P, and 294S of the daughter board 295. The thermosetting epoxy j resin sheet forming the interlayer resin insulating layers 240 and 340 described above contains a poorly soluble resin, soluble particles, a hardener, and other components. Individually, it is the same as the first embodiment described above, and therefore description thereof is omitted. (First Modified Example of Embodiment 2) Next, a printed circuit board 212 according to an i-th modified example of the second embodiment of the present invention will be described with reference to Fig. 23. The above-mentioned embodiment 2 is explained by the person who sets up the BGA. The structure of the first modified example of the second embodiment is a structure in which the PGA method is connected via the conductivity " 296. In addition, the above-mentioned second embodiment. The recessed portion 334 of the chip capacitor 220 is provided on the core substrate 23ι 499823 by countersinking. 5. Description of the invention (53) I, and the chip capacitor is accommodated § 220. The first modified example of the second embodiment is that the first resin substrate 230a provided with through holes 230A and the second and third resin substrates 230b provided with no through holes are bonded together by using resin layers (adhesive plates) 238a and 23 8b. 230c to form a core substrate 230 having a recessed portion 335 for accommodating the chip capacitor 220, and a plurality of chip capacitors 2 2 0 are accommodated in the recessed portion 3 3 5. With reference to Figs. 21 and 22, a method for manufacturing a printed circuit board according to a first modification of the second embodiment of the present invention will be described. A person (1) made a core material such as glass cloth with a thickness of 0.3 mm impregnated with βτ resin and hardened a resin substrate 2 31 a on both sides of which a copper foil 2 3 2 was laminated with a copper laminate layer 23 1 Μ as a starting material ( Refer to Figure 丨 7 (a)). The copper 羯 232 of the copper-clad laminated board 231M was pattern-etched to form second and third resin substrates 2 3 0b and 230c with conductor circuits 2 35 (the 17th (B; / Figure 5) In addition, the first resin substrate 23oa (FIG. 21 (B)) including the conductor circuit 235 is formed to form a through hole 230A at the same time as pattern etching. Then, the third resin substrate 230c and the second resin substrate 230c are formed. Resin substrate 23Ob is impregnated with a core material such as glass-breaking cloth by impregnating the epoxy resin with a resin layer 238b. Similarly, the second resin substrate 230b and the first tree-shaped substrate 230a forming the through hole 230A are bonded to Laminate with the resin layer 238a. (Figure 21 (C) 丨).-(2) Then 'press the laminated substrates using hot extrusion and pressure, and place the first, second, and third resin substrates 2 30a, 230b, and 230c are multilayered and integrated to form a core substrate j 230 having a recessed portion 3 3 5 for accommodating chip capacitors 220 (refer to FIG. 21 (D)). Here, first, the surroundings are pressurized. Pressure 499823 V. Description of the invention (54) --- Use the epoxy resin (insulating resin) of the resin layers 238a and 238b to make = 1, 2nd, 2nd 3 The resin substrates 230a, 230b, and 230c are in close contact. In addition, the epoxy resin is hardened by heating at the same time as the pressure, and then the resin I layers 2383, 2381) are interposed therebetween, and they are firmly bonded. The second tree month is a substrate 230a, a second resin substrate 23Ob, and a third resin substrate 230c. 0) Then, a thermally curing or UV curing adhesive 236 is applied to the bottom surface of the recessed portion 334 using a printer (see (E)). In this case, in addition to coating, pouring may be performed. Next, a chip capacitor 220 is placed on the bonding material 236 (see figure j 苐 22). By accommodating a plurality of chip capacitors 220 'in the core substrate, it is possible to achieve a high accumulation of capacitors. (After 5 \, between the chip capacitors 220 in the recessed portion 334, a thermosetting resin 2 is filled and heated to harden to form a resin layer 233 (Fig. 22 (B) | Brown.), When the thermosetting resin is preferred It is epoxy, phenol, polyimidazole, and triple I. By this, the chip capacitor 22o fixed in the concave portion 335 is filled, and the gap between the crystal s 2 | yi 2 2 0 and the wall surface of the concave portion 3 35 is filled. : And (6 \ The substrate 230 after the above steps is heated to 50 ~ 150 Jiezhi = pressure 5kg / Cm2 vacuum pressure lamination, and an epoxy resin group insulating resin 240 is provided (refer to Section 22 ( C) Figure). /) Next, the interlayer resin insulation on the resin substrate 2 3 〇a side was formed by 2 4 0 I w to the first terminal 2 21 and the second terminal 1 1 of the chip capacitor 220. 42 (Fig. 22 (D)). * The steps after μ 'are the same as (8) to (21) of the first embodiment, and therefore the description is omitted.

Page 58 499823 V. Description of the invention (55) '一 " " " (First alternative of the first modification of the second embodiment) · Continue, referring to FIG. 24 to explain the second embodiment of the second embodiment of the present invention. !! Modified Example The printed circuit board of the first alternative. The first modified example of the second embodiment described above includes only the chip capacitor 2 2 0 housed in the core substrate 230, but the j ^ 1 example is a chip capacitor 286 having a large capacity mounted on the surface and the inside. -IC chip is used for complex calculation processing which consumes large power instantly. Here, in order to supply a large amount of power to the IC chip, in this embodiment, a chip capacitor 220 and a chip capacitor 286 for power are provided on a printed circuit board. The effect of the chip capacitor will be described with reference to FIG. 12. Fig. 12 shows the voltage supplied to the IC chip on the vertical axis and time on the horizontal axis. Here, the 'two-point chain line c' shows the voltage variation of the printed circuit board without the power supply capacitor. When no power supply capacitor is provided, the high voltage 5 is weak. A dotted line A indicates a change in electric f of the printed circuit board of the surface mount chip capacitor. Compared with the two-point chain line described above, the voltage does not decrease significantly, but because the length of the loop (1οορ) increases, rapid power supply cannot be performed sufficiently. That is, when the supply of electric power is started, the voltage drops. In addition, referring to FIG. 23, the two-dot chain line B indicates that the voltage of the printed circuit board having the above-mentioned chip capacitor / voltage drop is displayed. The loop length is shortened, but due to the core: the core 5 plate 230 contains a large-capacity chip capacitor, and the voltage varies; here, the line E is shown with reference to Figure 24, since she, 1 ^ container 220, but also the right description The chip voltage in the core substrate has a large amount of change in the voltage of the printed circuit board on the surface of the MC wafer. Of change example 22. There are also chip capacitors with large capacity (ie phase V, large chip near-chip capacitor 286, which minimizes voltage fluctuations. Why?)

499823 I V. Explanation of the invention (56) In addition, in the first example of the second embodiment, the chip capacitor 22 is formed by completely peeling off the first electrode 221 and the second electrode 222 as shown in FIG. 13 (A). After the layer (not shown) is coated with a copper plating film 29. Then, the first and second electrodes 221, 222 electrically connected to the copper plating film 29 are obtained through the interlayer window 260 formed by the copper electrical key. Here, the electrodes 221, 222 of the chip capacitor are uneven on the surface of the metallized composition. Therefore, in a state where the metal layer is exposed, and the non-through hole 242 is formed in the connection layer 240, resin remains on the IH3 protrusion. At this time, due to the residual resin, poor contact between the i-th, second electrodes 221, 222 and the interlayer window 260 may occur. In contrast, the modified example of j is to smooth the surface of the first and second electrodes 221 and 222 by the copper plating film 29, and to insert non-through holes on the interlayer resin insulation coated on the electrodes. In the case of the hole 42, no resin remains, and the reliability of connection with the electrodes 221 and 222 when forming the interlayer window 260 | I can be improved. In addition, the electrodes 221 and 222 of the copper plating film 29 are formed with the electrical window 260 to improve the continuity between the electrodes 221 and 222 and the interlayer window 2f. Even if a heating cycle test is performed, the electrode 221 There will be a break in the middle of the window 260 on the 222th floor. Neither the offset nor the failure of the connection portion of the interlayer window of the capacitor will be caused. Moreover, the above-mentioned copper plating film 29 is a step for mounting a printed circuit board

In the step, the nickel / tin layer coated on the surface of the metal layer 26 in the manufacturing stage of the chip capacitor is peeled and provided. Instead, at the manufacturing stage j of the chip capacitor 22Q, a copper plating film 29 may be directly coated on the metal layer 26. That is to say, j, in the first other example, a laser is provided to the opening i of the steel plating film 29 of the electrode, and then residues are removed to form a via window by copper plating. because

Page 60 499823 j V. Description of the invention (57) ---- j I Here, an oxide film is formed on the surface of the copper plating film 29, because the oxide film is removed by the above-mentioned laser and | | Touch properly. j In addition, a roughened layer 23 α may be provided on the surface of the dielectric body 23 of the ceramic composition of the chip capacitor 220. Therefore, the adhesion between the ceramic capacitor 220 having a ceramic composition and the interlayer resin insulating layer 24 made of resin is improved, and even if a heat cycle test is performed, peeling of the interlayer resin insulating layer j | 240 at the interface does not occur. This roughened layer 23 α is formed by polishing the top surface of the wafer 220 after firing, or by roughening before firing. In addition, in the first alternative, the surface of the capacitor is roughened to improve the adhesion with the resin, but it may be applied to the surface of the capacitor instead.

Silane combined treatment. Furthermore, as shown in FIG. 13 (B), a part of the coating 2 8 of the first electrode 21 and the second electrode 22 of the capacitor 220 may be removed. Therefore, exposing the first electrode 21 and the second electrode 22 can improve the continuity. (Second Modification of Second Embodiment) The structure of a printed circuit board according to a second modification of the second embodiment of the present invention will be described with reference to Figs. The structure of the printed circuit board of the second modification is substantially the same as that of the first embodiment. However, the chip capacitors 20 accommodated in the core substrate 30 are different. Figure | | 14 is a plan view showing a chip capacitor. Figure 14 (A) shows a number of chip capacitors taken before cutting, and a chain line in the figure shows the cutting line. In the printed circuit board of the first embodiment described above, the first electrode 2 1 and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of FIG. 14 (B). Figure 14 (C) shows the majority of the second modification. J ϊ _____—__ 丨 1 1 1 1 I 1 1 1 2160-3403-Pi-Ptd Page 61 499823 5. Description of the invention (58) Wafer Capacitor, a chain line in the figure shows the cut line. The second modified example is a printed circuit board in the state I shown in the plan view of FIG. 14 (D), and the first electrode 21 and the second electrode 22 are arranged on the side edges of the chip capacitor. r,! The printed circuit board of the second modification uses a chip capacitor 20 in which electrodes are formed on the inner side of the outer edge. Therefore, a chip capacitor having a large capacity can be used. Continuing, a printed circuit board according to a first modification of the second modification will be described with reference to FIG. 15. Fig. 15 is a plan view showing a chip capacitor 20 accommodated on a core substrate of a printed circuit board of the first alternative. In the first embodiment described above, a plurality of small-capacity chip capacitors are housed on the core substrate, but the first other example is a large-capacity large-scale chip capacitor 20 housed on the core substrate. Here, the Xin-chip capacitor 20 is connected to the first conductive film 24 connected to the first electrode 21 by the first electrode 21 and the second electrode 22 and the electromotive body 23 and to the second conductive layer connected to the second electrode 22 side I The film 25 is composed of an electrode 27 for connection to the upper and lower surfaces of a chip capacitor not connected to the first conductive film 24 and the second conductive film I 25. The IC chip side and the daughter board are connected via the electrode 27. — Since the printed circuit board of this first modification uses a large-sized chip capacitor 20 ', a large-capacity chip capacitor can be used. In addition, because the large chip capacitor 20 is used, even if the heating cycle is repeated, the printed circuit handle does not bend. The printed circuit board of the second alternative example will be described with reference to FIG. 16. The 16th (a) | _ picture shows most of the chip capacitors taken. The one-point chain line in the figure shows an unusual cutting line, and the 16th (β) picture shows the flat picture of the chip capacitor. As shown in Fig. ΗU), the second example is connected by a plurality of

2160-3403-Pf-ptd Page 62 V. Description of the Invention (59) The example in use is 3) Most of the chip capacitors used are large, "The 2nd example" is because the county's idle female sentence 丨 20 Even if the heating cycle is repeated, in the above-mentioned embodiment of J == capacitor, the “Densa” snow *! Board will not bend. & Each of the moon-packs is contained in a buckle, but it is also possible to replace the chip capacitor with a top-coat having a conductive film provided on a ceramic plate. As described above, the plate-shaped electric valley device of the body film is based on the method of accommodating the capacitors in the plate of the second embodiment, which can reduce the distance between the capacitors of the printed circuit board and reduce the resin substrate of the circuit. And forming two; r, a plurality of layers are formed to form a conductor electrical wiring density, which can reduce the network and thus improve the core substrate. In addition, because of: the number of layers of the edge. The reason is that the capacitor is filled with resin between the capacitors. Therefore, the capacitors will not be affected. Therefore, the capacitors can be alleviated without shifting. Dissolution, etc. Therefore, ^ ^ ^ interlayer is implemented. The peeling of the connection part of f 0 and ... the steel 'maintains the desired performance. ~ The order of the order ~ The occasion 5 can also prevent the occurrence of the offset (Example 3) Refer to Figures 30, 31 +, B + Circuit board. Figure 30 is%: Xiongming's printed electrical display of the third embodiment of the present invention. Figure 30 shows the stamp = the cross section of the printed circuit board 410. Figure 31 shows the shape on the side of the daughter board 495. Bear, board 410 mounts IC chip 490 and installs

2160-3433-?:-?: d Page 63 499823 I V. Description of the Invention (60) | The printed circuit board 410 shown in the second figure is composed of a core substrate 430 that houses a plurality of chip capacitors 420 and an overlay wiring Layers 480A, 480B. The stacked wiring layers 480A and 480B are composed of interlayer resin insulating layers 540 and 541. Conductor circuits 558 and interlayer windows 560 are formed on the interlayer resin insulation layers 5 4 0 I of the superimposed wiring layers 4 8 0 A, 4 8 0 B, and conductor circuits 559 are formed on the interlayer resin insulation | edge layer 541 And an interposer window 564. On top of the interlayer tree | grease insulation layer 141, a solder photoresist layer 470 is provided. The core substrate 4 30 is provided with an interlayer window 460 connected to the chip capacitor 420 and a conductor circuit 4 58. The superposed wiring layer 480A and the superposed wiring layer 480B are connected via a through-hole 456 formed in the core substrate 430.

The chip capacitor 420 is composed of the first electrode 421 and the second electric electrode 422 shown in FIG. 30, and the electric induction body 423 sandwiching the first and second electrodes. A plurality of the electric induction body 4 23 are relatively arranged. The first conductive film I 424 connected to the first electrode 421 is connected to the second conductive film 425 connected to the second electrode 422. As shown in FIG. 31, solder bumps 476E of pads 492E, 492P, and 492S that are connected to the 1C chip 490 are arranged on the superposed wiring layer 480A on the upper side. On the other hand, solder bumps 476D for pads 494E, 494P, and 494S to be connected to the daughter board 495 are formed on the stacked wiring layer 480B on the lower side. ϊ

The pad 492S for the signal of the 1C chip 490 is via the bump 476U-conductor circuit 5 59-via window 564-conductor circuit 5 58-via window 560-through hole 456-via window 560-conductor circuit 558-via The layer window 564-conductor circuit 55 9-bump 476D is connected to the signal pad 494S of the daughter board 495. The pad 492E for grounding the 1C chip 490 is via a bump 476U-mediated

216D-3403-FI · ptd Page 64 499823 V. Description of the invention (61) ~ j I layer window 564-conductor circuit 558-interlayer window 560-conductor circuit 45δ-interlayer I window 460 and connected to the chip capacitor 420 First electrode 421. On the other hand, the pad 494E of the grounding perimeter of the daughter board 495 is connected via the bump 476D-via window 564-conductor circuit 5 58 -via window 560 -through hole 4 56 -conductor circuit 458 -via window 460 To the first electrode 421 of the chip capacitor 420. ! 'Grounding pad 494E2 is connected via bump 4761)-via window 564-conductor circuit 5 58-via window 560-conductor circuit 4 5 8-via window 460 | continued to chip capacitor The first electrode of 420 is 421. 1C chip 490's lining 492P for power supply is the second one connected to chip capacitor 420 via bump 476U-via window 564-conductor circuit 5 58-via window 560-conductor circuit 4 58-via window 460 Electrode 422. On the other hand, the pad 494P for the power supply of the daughter board 495 is via the bump 476D-via | window 564-conductor circuit 5 58 -via window 560 -through hole 4 56 -conductor circuit | | 458 -via window 460 is connected to the second electrode 4 22 of the chip capacitor 420. Another 5 € source view 494P2 is connected to the first electrode 422 of the chip capacitor 420 via the bump 476D-interlayer window 564-conductor circuit 558-interlayer window 560-conductor circuit 458-interlayer window 460. In this embodiment, the first and second electrodes 421 and 422 are connected from the daughter board 4 95 side to the chip capacitor 420 through the through holes 4 56. However, the connection through the through holes may be omitted. As shown in FIG. 30, the core substrate 430 of the present embodiment is connected to the first resin substrate 4 30a of the chip capacitor 420 via a bonding material, and is connected to the first resin substrate (adhesive plate) 438a via a bonding resin layer The second resin substrate 430b of the first resin substrate 430a and the third resin substrate 430c connected to the second resin substrate 43Ob through the resin layer (adhesive plate) 4 3 8b for bonding

1 1 ί I 1 I 2160-3403-ff-ptd page 65 5. Description of the invention (62). The second resin substrate 43ob is formed with an opening 430B capable of accommodating a chip capacitor 420. As a result, the chip capacitor 420 and the chip capacitor 42 can be shortened because the chip capacitor 420 can be accommodated in the core substrate 430. Therefore, the loop inductance of the printed circuit board 410 can be reduced. In addition, since the first resin substrate 430a, the second resin substrate 430b, and the third resin substrate 430c are laminated, a core substrate 43 with sufficient strength can be obtained. In addition, since the first resin substrate 43 ° and the third resin substrate 43 ° c are disposed on both surfaces of the core substrate 430 to smoothly constitute the core substrate 430, the resin layers 540 and 541 can be appropriately formed on the core substrate 30. And the conductor circuits 558 and 559 and the interlayer windows 5 60 and 5 6 4 ′ can reduce the incidence of defective products on the printed circuit board. And 'this embodiment is provided with an interlayer window 4 6 0 on both sides of the core substrate 43 ’, so that the jc wafer 4 9 0 and the chip capacitor 420 can be connected in the shortest distance, and the daughter board 4 95 and the chip capacitor 420, so It can instantly supply large power from the daughter board to the IC chip. In this embodiment, as shown in FIG. 25 (D), an insulating adhesive 4 3 6 is interposed between the first resin substrate 4 3 0 a and the chip capacitor 4 2 0. Here, the thermal expansion ratio of the connector 4 3 6 is smaller than that of the core substrate 4 3 0, that is, it is set near the capacitor 420 made of ceramic. Therefore, in the heating cycle test, even if internal stress caused by the thermal expansion coefficient occurs between the core substrate and the connector layer 436 and the chip capacitor 420, the core substrate is difficult to generate cracks and peeling, and high reliability can be achieved. It can also prevent the occurrence of offset. The manufacturing method of the printed circuit board described above with reference to FIG. 30 will be described with reference to FIGS. 25 to 30.

2160-3403-FI'Ptd

499823 V. Description of the invention (63) — (1) Impregnated with a BT core | grease and hardened resin substrate 430a, a core sheet of glass cloth with a thickness of 0.1 mm is laminated with a copper foil laminate 430M of copper foil 430M (No. The first resin substrate 430a and the third resin substrate 430c are used as starting materials (see FIG. 25 (A)). · I j Next ', the copper foil 43 2 of the copper-clad laminate 430M is pattern-etched to form an opening 432a for forming an interposer window in the copper box 432 (see FIG. 25 (B)). / ^ (2) After that, on the surface of the copper foil 432 on which the first resin substrate 43 0 & is not laminated, a thermal curing or ϋν curing adhesive 4 4 6 is applied using a printing machine (refer to Section 2). 5 (C) figure). In this case, in addition to coating, injection can also be performed. … Next ', a plurality of ceramic capacitors 420 are placed on the bonding material 4 3 6, and the wafer capacitor 420 is bonded to the first resin substrate 430 a via the bonding material 436 (see FIG. 25 (D)). There may be one or more chip capacitors 420, and by using a plurality of chip capacitors 420, a high accumulation of capacitors can be achieved. r | (3) Next, the second resin substrate hardened with BT resin is prepared by impregnating a core material such as glass cloth with epoxy resin, and then using a resin layer (a subsequent resin layer) 438a, 438b and a core material impregnated with glass cloth or other material to BT resin. 430b (thickness 0.4mm). Through-hole resin layers 438a and second resin substrate 430b are formed with through holes 36A and 430B that can accommodate chip capacitors 420. First, a second resin substrate 4 3 Ob is placed on the third resin substrate 4 3 0 c under the surface of the laminated copper and metallurgy 4 3 2 via a bonding resin layer 4 3 8 b j. Next, the first resin substrate 430a is inverted and placed on the second resin substrate 430a via the resin layer 438a for bonding. and also

2i60-3403 ~? F-ptd P.67 499823 V. Description of the Invention (64) That is, the chip capacitor 42 connected to the first resin substrate 430a is directed toward the bonding resin layer 438a side, and the The state of the opening 430B formed by the chip is superimposed on the state of the chip capacitor 42 (see FIG. (A)). In this way, a printed circuit board capable of accommodating chip capacitors 42 in the core substrate 430 and reducing the inductance of the circuit can be provided. Furthermore, substrates such as ceramics and AIN cannot be used as the core substrate. This substrate has poor formability and cannot accommodate capacitors. Even if it is filled with resin, voids are generated. '(4) Then, the overlapped substrates are pressed by hot pressing, and the first, second, and third resin substrates 430a, 430b, and 430c are multilayered and integrated.

The core substrate 430 includes a plurality of chip capacitors 420 (see FIG. 26 (B)). Here, first, an epoxy resin (insulating resin) composed of I resin layers 438a and 438b is pressed out by pressing, and the gap between the opening 4 3 0 B and the chip capacitor 4 2 0 is filled. In addition, the epoxy resin is hardened by heating at the same time as the pressure, and the resin layers 438a and 438b are used as the resin to be interposed therebetween, and the first resin substrate 4403 and the second tree substrate 4 3 are firmly bonded. 0 b and 3 resin substrate 4 3 0 c ° Furthermore, in this embodiment, the gap in the opening 4 3 〇B is filled with epoxy resin that overflows from the resin layer, but instead, it can be in the opening 430B. Configure the filler.

Here, because both sides of the core substrate 430 are smoothly arranged with the i-th resin substrate 4 30a and the third resin substrate 430c, the smoothness of the core substrate 430 is not impaired. Forming interlayer I resin insulation 540, 541, conductor circuits 558, 559, interlayer windows | 560, 564 can reduce the incidence of defective products on printed circuit boards. In addition,

2160-3403-?!-Ptd page 68 499823! 5. Description of the invention (65) | A core substrate 430 with sufficient strength is obtained. (5) Next, the part exposed from the opening 432 of the interlayer window formation 432 of the steel foil 432 is removed by laser, and the interlayers of the first electrode 4 21 and the second electrode 4 22 of the chip capacitor 420 are formed. Window opening 442. That is, a conformal mask is used to form an opening 44 2 for an interposer window on the core substrate 430 by laser. After that, the same procedure can be performed on the other I side of the substrate (see FIG. 26 (C)). §

j (6) Next, two through holes 44 penetrating the I-hole are formed on the core substrate 30 by drilling or laser (see FIG. 26 (D)). The residue is then treated with an oxygen plasma. Or use a chemical solution such as permanganic acid for residue removal treatment. (Then, sv-454, manufactured by Japan Vacuum Technology Co., Ltd. was used to remove the residue.) The inspection process 5 forms a roughened surface on the entire surface of the core substrate 4 3 G. At this time, 'the argon gas is used as the inert gas and the electric power 2 is used. 〇〇w, gas pressure 0.6 Pa, temperature 70. (: conditions, plasma treatment was performed for 2 minutes. After that, Ni and Cu were used as targets, and the core substrate 43 () metal layer 448 ( See Zhao No. 27 ίΑ). + Π # / 0…, Futu). Here, sputtering can be used, but the metal layer of copper, nickel, etc. can be formed by electroless plating. Optionally, an electroless plated film may be formed after sputtering is formed. Or an oxidizing agent may be subjected to a roughening treatment. Further, the roughened layer is preferably 0 · b 5 # m (8) Next, a Ni—Cll metal film 448 is formed. The surface is covered with a light dry film and loaded with ^ ^. 0 A ^ The feeling of the city mouth is set to check μ firstly, then exposure and first development processing

2160-3403-Pf.ptd Miscellaneous, r ^ case photoresist 45. Then, the core substrate 430 was immersed in the electrolytic lightning, and no current was passed through the 1 ^ -Cu metal layer 448. The following conditions were applied to the electroplating of the non-forming portion of the resistance 450 in the following conditions: B) Figure). [Electrolytic solution of electrolytic ore 1 copper sulfate sulphate additive (r   5 > f HL) [Electrolytic plating conditions] Current density; time and temperature to form electrolytic plating film 452 (refer to 2.24mo 1/1 0.26 mo 1/1 evening Xiqiba > made by the company

19.5 mol / 1 1 A / dm2 1 2 0 minutes 22 ± 2 0C (9) Peel off the photoresist with 50% NaOH to remove 50% of the photoresist, and then etch the resistance 450 times with a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide. The Ni-Cu layer 448 is dissolved and removed to form a conductor circuit 458 (including a via window 460) composed of the copper foil 432, the Ni-Cu layer 448, and the electrolytic copper plating film 452. Therefore, after washing the substrate and drying the substrate, the remaining liquid is blown on both sides of the substrate, and the surface of the through-hole 4 56 and the conductor circuit 458 (including the interlayer window 460) are blown, and the entire surface of the through hole 45 6 The surface and the entire surface of the conductor circuit 458 (including the interlayer window 4 6 G) form a roughened surface 4 6 2 (see FIG. 27 (C)). The remaining solution is an etching solution composed of an imidazole copper (Π) complex, a weight portion of 7 g of glycolic acid, a portion E, a weight portion of sodium gasification, and a weight portion of 78 weight portions of ion-exchanged water. (1) Use a printing machine to apply a resin filler 464 containing epoxy-based resin as the main component to both sides of the substrate 430, and fill the conductor circuit 458 or the through hole

2160-3403-Pi-ptd Page 70 499823 V. Description of the invention (67) 456, heat and dry. That is, by this step, the resin filler 464 is filled between the conductor circuits 458, the via window 460, and the through-hole 456 (see FIG. 27 (D)). (11) Polish one surface of the substrate 4 30 completed in (10) above with a belt sander using a belt-shaped abrasive paper (manufactured by Sankyo Rika Co., Ltd.), The surface and the ridge surface 456a of the through-hole 456 are polished in a state where no resin filler remains, and then the light polishing using the above-mentioned belt grinder to remove damage is performed. The series of grinding processes are similarly performed on the other surface of the substrate 430. Then, the filled resin filler 464 is heat-hardened. This state “removes the surface layer portion of the resin filler 464 filled in the through-hole 456 and the like and the roughened surface 462 on the conductor circuit 458, and both sides of the smooth substrate 430 are firmly adhered to the resin through the roughened surface 462 The filler 464 and the conductor circuit 458 are in close contact with the inner wall surface of the through-hole 456 and the resin filler 4 6 4 through the roughened surface 462. Next, the same etching solution using the above (9) etching solution is sprayed with a sprayer! Di Blow is attached to both sides of the substrate 430, and the surface of the conductor circuit 458 and the ridges of the through holes 456 once planarized at a later time. The surface 456a forms a roughened surface 458α on the entire surface of the conductor circuit 458 (see FIG. 28 (A)). (12) On the substrate 430 that has undergone the above steps, the thermosetting epoxy resin sheet is heated to 50 to 150 ° C on one side and vacuum-pressed at a pressure of 5 kg / cm2: laminating, and an interlayer resin insulating layer 540 ( Refer to Figure 28 (B) Figure I). The degree of vacuum during vacuum pressing was 10 mmHg. (1 3) Next, an interlayer is formed on the interlayer resin insulating layer 5 4 0 by laser.

2160 ~ 3403-Ρί · p td Page 71 499823

[^, Description of the invention (68) II window fixed opening 542 (refer to FIG. 28 (C)).丨 (1 4) Next, in the step (7), a residue removal treatment is performed using SV-4540 manufactured by Japan Vacuum Technology Co., Ltd. to form a roughened surface 540 α on the surface of the interlayer resin insulating layer 540 (refer to Section 28 (D) Figure). Here, the roughening treatment may be performed with an acid or an oxidizing agent. In addition, the roughened layer is preferably 0. 1 to 5! I // m. After j \ \ (1 5), as in step (7), Ni and Cu are sputtered to form an iNi_Cu metal layer 548 on the surface of the interlayer resin insulating layer 540 (see FIG. 29 (A)). ). Here, sputter plating may be used, but metal layers such as copper and nickel may also be formed by electroless plating. In addition, an electroless plated film can be formed after the field of view is formed by sputtering. I (16) Next, as in step (8), a commercially-available photosensitive dry film is attached to the surface of the Ni-Cu metal film 548, and a photomask film is placed on the surface of the Ni-Cu metal film. A photoresist 544 of a predetermined pattern is formed. Then, the substrate is immersed in an electrolytic plating solution, a current flows through the Ni-Cu metal layer 5 4 8 and electrolytic plating is applied to the non-formed portion of the photoresist 544 to form an electrolytic plating film 552 (see section 29 (B)). Figure). I (17) is followed by the same process 5 as in step (9) to form a Ni-Cu metal layer i 548 and a conductive circuit 558 (including a via window 560) composed of an electrolytic plating film 552. Then, the substrate was washed with water, dried, and the remaining liquid was etched by spraying on both sides of the substrate with a sprayer to etch, and a roughened surface was formed on the entire surface of the conductor circuit 558 (including the interlayer window 5 6 0) 1 5 4 (Refer to Figure 29 (C)). ί (1 8) Repeat steps (1 2) to (1 7) to form an interlayer resin on the upper layer | f \

2160-3403- ?:-? Td page 72 499823

The I insulating layer 541 and the conductor circuit 559 (including the interlayer window 5β4) are used to roughen the I surface 565 (see FIG. 29 (D)). The subsequent steps are the same as (6 to (9) in the first embodiment described above, so the description is omitted. "In addition, the 1C chip 490 is placed on the printed circuit board that completes the above steps, and is mounted on the daughter board. The embodiment 丨 is the same, so the description of 0 fj is omitted (the first other example of Embodiment 3) |

Tea Photo Fig. 32 illustrates a printed circuit board according to the first alternative example of the third embodiment of the present invention. The printed circuit board of the first other example is substantially the same as the third embodiment. However, the printed circuit board of the first other example is provided with a conductive bolt 496, and a state of connection with the daughter board is obtained through the conductive bolt 496.

I

j Further, in the above-mentioned Embodiment 3, only the crystal I chip capacitor 420 housed in the core substrate 430 is provided, but the first alternative is to mount a large-capacity chip capacitor 486 on the surface and inside. ^ IC chips are complex calculations that consume large amounts of power instantly. Here, in order to supply a large amount of power to the 1C chip, the i-th alternative is that a chip capacitor 420 and a chip capacitor 486 for power are provided on a printed circuit board. The effect of the chip capacitor will be described with reference to Fig. 12. · ^ In Fig. 12, the vertical axis is the voltage supplied to the IC chip, and the horizontal axis is time. Here, the one-dot chain line C shows the voltage fluctuation of the printed circuit board without the power supply capacitor. If no power supply capacitor is provided, the large voltage will be reduced. The dotted line A is the 499823 showing the printed circuit board of the chip capacitor on the surface. V. Description of the invention (70) Voltage fluctuation. Compared with the above two-point chain line, the voltage does not decrease significantly, but because the length of the loop (1 ο ο P) increases, fast power supply cannot be performed. That is, when the supply of electric power is started, the voltage drops. In addition, the two I i point chain lines β show that the voltage of the printed circuit board with the chip capacitor built therein described above is referred to FIG. 31. The circuit length is shortened, but because the chip capacitor with a large capacity cannot be accommodated in the core substrate 430, the voltage varies. Here, the 'solid line E' shows the voltage variation of the printed circuit board of the i-th other example of the chip capacitor 420 in the above-mentioned core substrate with reference to FIG. 32 and a surface-mounted large-capacity chip capacitor 48 6. The chip capacitors near the 1C chip | | 42 0 ′ also have chip capacitors 4 8 6 with large capacity (that is, relatively large inductive reactance) to minimize voltage fluctuations. (First Modification of Embodiment 3) ^ "Continued" A first modification of Embodiment 3 of the present invention will be described with reference to FIGS.

A manufacturing method of the printed circuit board 414 in a modified example. The printed circuit board of the i-th modification of the third embodiment is substantially the same as the third embodiment described above. Referring to FIG. 301, the third embodiment described above is configured with the conductor circuit 458 by three layers of the copper foil 432, the Ni-Cu metal layer 448, and the electrolytic plating film 452. On the other hand, the printed circuit board 412 according to the first modified example of the third embodiment is composed of two layers of an electroless plated film 443 and an electrolytic plated film 4 5 2. That is, the copper foil 432 is removed, the thickness is reduced, and the conductor circuit 458 is formed at a fine pitch. In addition, in the printed circuit board 41 of the first modification of the third embodiment, a conductor circuit 435 is formed on both sides of the second resin substrate 43〇1} of the opening 430B that houses the chip capacitor 420. In the third modification of the third embodiment, conductor circuits 435 are formed on both surfaces of the second resin substrate 430b. Core base

2160-3403-Pi-ptd page 74 499823 j V. Description of the invention (71) The wiring density in the board 4 30, and it can reduce the number of layers of the interlayer resin insulation layer. In addition, in the printed circuit board according to the first modified example of Embodiment 3, the chip capacitor 420 is a strip coating (not shown) of the first electrode 421 and the second electrode 422 as shown in FIG. 13 (A). (Illustrated), and then covered with a copper key film 29. I is the first and second electrodes 421 and 422 which are electrically connected to the copper-plated film 29 on the interlayer window 460 made of copper plating. Here, the electrodes 421 and 422 of the chip capacitor have irregularities on the specific surface of the metallized composition. Therefore, in the state where the metal layer is exposed, the step of forming the non-through hole 442 in the first resin substrate 430a causes resin to remain on the unevenness. At this time, it will occur that the resin remains and the first, second electrodes 421, 422, and the interlayer window 460! Poor contact. On the other hand, the first modification of the third embodiment is to smooth the surfaces of the first and second electrodes 421 and 422 by the copper electro-membrane film 29, and to provide openings in the first resin substrate 430a covering the electrodes. At 442, no resin remains, and I can improve the reliability of connection with the electrodes 4 21 and 4 2 2 forming the interlayer window. In addition, since the interlayer window 460 is formed by electroplating the electrodes 421 and 422 on which the copper plating film 29 is formed, the continuity between the electrodes 421 and 422 and the interlayer window 460 is improved. No disconnection will occur between the electrodes 42; [, 422 and the interlayer window 460. Neither the offset nor the defect of the capacitor electrode is caused. · Furthermore, the above-mentioned copper electrical clock film 29 'is provided in a stage I, a stage where a printed circuit board is mounted, and the nickel / tin layer coated on the surface of the metal layer 26 at the stage of manufacturing the chip capacitor is peeled off. Instead, at the manufacturing stage of the chip capacitor 42

499823 V. Description of the invention (72) (2) The copper plating film 29 can be directly coated on the metal layer 26. That is, in the first modification of the third embodiment, a laser is provided to the opening of the copper plating film 29 of the electrode, and a residue removal process is performed to form an interlayer window by copper plating. Therefore, an oxide film is formed on the surface of the copper plated film 29, and the oxide film is removed by the above-mentioned laser and residue removal treatment, and appropriate contact can be obtained. In addition, a roughened layer 23a is provided on the surface of the electromotive body 423 of the ceramic composition of the chip capacitor 42. Therefore, the adhesiveness of the chip capacitor 420 of ceramic composition and the adhesion layer μ 8 of resin composition and $ 3 8 b is improved, and the first resin substrate 43 which does not occur at the interface even if a heating cycle test is performed. The peeled-off roughened layer 23a is formed by polishing the surface of the wafer capacitor "ο" after firing, or by applying a roughening treatment before firing. Furthermore, the first modification of Example 3 is because The surface of the capacitor is roughened to improve the adhesiveness with the resin, but instead of applying a combination of stone sintering to the surface of the capacitor, it can also be shown in Figure 13 (B). It is used by removing part of the cover 28 of the first electrode 21 and the second electrode 22 of the capacitor 420. Because the first electrode 21 and the second electrode 22 are exposed, the connection with the interlayer window can be improved. 3 to 5 illustrate the manufacturing steps of the printed circuit board according to the first modification of the third embodiment of the present invention. 〇9) Prepare a core material such as glass cloth with a thickness of 0 · imffi by impregnating a τ resin with a Bτ resin and curing the substrate 430a. Laminated copper 432 copper sheet laminate 430M (first resin substrate 4 30a and the third resin substrate 430c) In addition, a copper substrate of 430N is laminated on both sides of a copper substrate 430N (refer to FIG.

2160 > 3403-F [-ptd

Μ page 76 499823 V. Description of the invention (73) Figure 33 (A)). · I (20) Next, the copper foil 432 of the copper-clad laminate 430M is pattern-etched to form an opening 432a for forming an interlayer window on the copper foil 432. Similarly, the copper foil 432 on both sides of the copper laminated laminate 430N is pattern-etched, and the conductor circuit 435 is formed. (Refer to Figure 33 (B)). In the first modification of the third embodiment, since the conductor circuits 435 are formed on both sides of the second resin substrate 43Ob, the wiring density of the core substrate can be increased, and the number of interlayer resin insulation layers can be reduced. After j (2!), the copper foil 432 of the first resin substrate 430a is not laminated.

On the surface ', a thermal curing system or a UV curing system adhesive material 4 3 6 is applied using a printer (see FIG. 3 3 (C)). In this case, in addition to coating, pouring may be performed. Next, a plurality of ceramic wafers | capacitors 420 are placed on the bonding material 4 36, and the wafer capacitors 420 are bonded to the first resin substrate 430a via the bonding material 4 36 (see FIG. 33 (D)). The number of chip capacitors 420 may be one or more. By using a plurality of chip capacitors 420, a high accumulation of capacitors can be achieved. (2 2) Next, a core material such as glass cloth is impregnated with epoxy resin, and then a resin layer (a resin layer for bonding) 438a, 438b and a second resin substrate 430b are prepared. Through-hole resin layers 438a and second resin substrate 430b are formed with through holes 36A and 430B that can accommodate chip capacitors 42. First, a second resin substrate 43ob is placed on the third resin substrate 4300c under the surface of the laminated steel hall 432 via the adhesive resin layer 438b. Next, the first resin substrate 4 30 a is reversely loaded on the second resin substrate 403 a) through the bonding resin layer 438 a.

499823 V. Description of Invention (74). That is, the state where the opening 43B capacitor chip capacitor 420 formed in the second resin substrate 430b is superimposed (see FIG. 34 (A)). Thereby, the chip capacitor 42 can be housed in the core substrate 430, and the printed circuit board can be reduced in road inductance / L. — Furthermore, substrates such as ceramics and AI N cannot be used as core substrates. This substrate has poor formability and cannot accommodate capacitors. Even if it is filled with resin, voids are generated. '(23) Then, the overlapped substrates are press-pressed using hot extrusion, and the first, second, and third resin substrates 430a, 430b, and 43c are multi-sound-integrated to form a plurality of wafers. The core of the capacitor 42 is "in accordance with Fig. 34 (B)". (Furthermore, in this embodiment, the filler is extruded from the inner space of the == which is then extruded with a resin layer, but instead, a filling material may be arranged in the opening =. Here, the two sides of the core substrate 430 are arranged smoothly. The substrate 430a and the third resin substrate 430c do not damage the half of the core substrate 43. In the steps to be described later, the resin insulation layers 540 and 541 and the conductor circuits 558 and 559 can be appropriately placed on the core substrate 43. Layers of 5 60, 5 64 can reduce the incidence of defective products on printed circuit boards. Second, a core substrate 430 with sufficient strength is obtained. Bu 'ke (24) Then, the opening 432 from the copper foil 432 is removed by laser. The exposed portion is formed to the chip capacitor 42. The opening is formed by the laser capacitor. The first electrode and the second electrode 422 are < the opening for the interlayer window 442. That is, the uniform cover is used to cover the core substrate 43 with a laser. 〇Intermediate window official sentences are formed

V. Invention Description (75) ---- 442. The same can be done later (Figure 34 (C)). With this, the other surfaces of the mesh f are carried out. (The opening diameter of the layer window according to the first interlayer window 43 " is based on the opening diameter of the copper foil 432 to form the interlayer window opening; f, so Appropriate density also depends on the dielectric window of copper foil 432. "The opening position of the 3 mound mouth is fixed, so even if the laser layer ^ ten-port-shaped opening / 4 / opening position position, a dielectric window is formed. "The degree is low.

Face apart! From :: == Engraving the two-degree difficult circuit 458 of the core substrate 430, may form a thin thick string in steps | ί or laser on the core substrate 430 to form a through hole +, ^ ...... d4 ( (D) Figure). After that, the oxygen plasma is subjected to decontamination treatment. * Or a residue removal treatment with a chemical solution such as permanganic acid. (26) Next, a residue removal treatment made by Japan Vacuum Technology Co., Ltd. is used. A roughened surface 446 is formed on the entire surface of the core substrate 43 (refer to FIG. 35 (A)). At this time, using argon gas as an inert gas and electric power of 200 W, gas pressure of 0.6 Pa, and temperature of 70, The plasma treatment is performed for 2 minutes. The roughening treatment may also be performed with an acid or an oxidizing agent. Further, the roughening layer is preferably 0.1 to 5 / zm.

(27) Next, the substrate 430 is immersed in an electroless copper electroplating aqueous solution having the following composition, and an electroless copper electroplated film 443 having a thickness of 0 to 30 minutes is formed on the entire roughened surface 446 (refer to Section 35 (B)). Figure). [Aqueous electroless plating solution]

NiS04 〇. 003 mol / l

V. Description of Invention (76)

HCHO NaOH tartaric acid sulfate 〇.200 mol / 1 〇. 0430 mol / 1 0.050 mol / 1 0.100 mol / 1 aa ^ bipyridy 1 40mg / l ethyl acetate, ethylene glycol ηιη / ι r. ^ Seed 0 · 10g / l [Conditions of electroless plating] 3BT liquid temperature of 40 minutes-Although electroless plating is used from m, it can also be sputter-plated to form copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, aluminum, or copper. In addition, depending on the situation, electroless plating can also be performed after forming by sputtering. (8) Attach a photosensitive dry film available on the market to the electroless steel lightning coating 4 ^ 3, place a photomask, expose it at 100 mJ / cm2, and develop the solution with sodium carbonate aqueous solution. , And set a plating photoresist 4 020 map with a thickness of 30 Am. (B)). Next, the substrate 43 was washed with water at 500 ° C to be degreased, washed with water at 25 ° C, and then washed with sulfuric acid, and was subjected to copper plating under the following conditions to form an electrolytic plating film 452 (refer to Section No. 35 (C) Figure) ^ "Solution [Electrolytic plating aqueous solution] ° & Baumann 2.24moI / l copper sulfate 0.26 mol / 1 square 5 > p HL) 19.5 mol / 1 [Electrolytic plating conditions] Current Density 1 A / dm2

2160-3403-Pi.Dtd 499823 V. Description of the invention (77) Time 6 5 minutes ·

Temperature ^ 2 + 9 ° Q & After removing the photoresist 45 °, the electroless plating film M3 at a resistance of 45 ° is etched with a mixed solution of nitric acid and sulfuric acid and lice, and dissolved and removed to form an electroless copper electrode. A through hole 456 with a thickness of 18 μm and a conductive circuit 458 (including a dielectric window 46G) composed of the plating film 443 and the electrolytic copper plating film 452. The third example! In the modified example, the steel 432 is removed in advance as described above, so that the thickness of the conductor circuit 458 can be reduced, and 彳 can be formed at a fine pitch. Here, the copper foil 432 is completely removed and peeled off, but the copper foil 432 may be thinned by line etching, which may reduce the thickness of the conductor circuit 458 or may be formed at a fine pitch. Subsequent steps are the same as (丨 0) to (丨 8) of the third embodiment described above, and therefore descriptions are omitted. In the first modified example of the above embodiment, via windows are provided on both sides of the core substrate, but via windows may be formed on only one side. In addition, although the two uniformly-covered covers are used as the openings 432a of the copper foil 432 on the surface of the core substrate 430, the uniformly-covered covers of the core substrate 430 may be used instead of the uniformly-covered covers to provide openings to the capacitors. (Second Modification of Example 3)

I Continue 'The structure of a printed circuit board according to a second modification of the third embodiment will be described with reference to Figs. The structure of the printed circuit board of this second modification is substantially the same as that of the embodiment i. However, the chip capacitors 20 accommodated in the core substrate 30 are different. Fig. 14 is a plan view showing a chip capacitor. Figure 4 (a) shows more

Hi 2160-3403-? Ί Page 81 499823 V. Description of the Invention (78) ---- Several chip capacitors taken before cutting, a chain line in the figure shows the cutting line. The above embodiment! The printed circuit board has an i-th electrode 21 j and a second electrode 22 on the side edges of the chip capacitor as shown in the plan view of I in FIG. 4 (β). Fig. 14 (C) shows a plurality of chip capacitors taken in the second modified example. A chain line in the figure shows a cut line. In the printed circuit board of the second modification, the first electrode 21 and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of Fig. 14 (D). I The printed circuit board of the second modified example is formed on the inner side of the outer edge

| The chip capacitor 20 of the electrode, so a chip capacitor having a large capacity can be used. I! Continuing, the printed circuit board of the first modification of the second modification will be described with reference to FIG. Fig. 15 is a plan view showing a chip capacitor 20 housed on a core substrate of a printed circuit board of the first alternative. In the first embodiment described above, a plurality of small-capacity chip capacitors are housed on a core substrate, but the first other example is a large-capacity large-scale chip capacitor 20 housed on a core substrate. Here, the chip capacitor 20 is composed of a first electrode 21 and a second electrode 22, and an electric inducer 23, a first conductive film 24 connected to the first electrode 21, and a second conductive layer connected to the second electrode 22 side. The film 25 is composed of an electrode 27 for connection to the upper and lower surfaces of a chip capacitor which is not connected to the first conductive film 24 and the second conductive film 25. The 1C wafer side and the daughter board are connected via the electrode 27. ! Since the printed circuit board of the first modification uses a large chip capacitor 1§20 ′, a chip capacitor with a large capacity can be used. In addition, since the large chip capacitor 20 is used, even if the heating cycle is repeated, the printed circuit board does not bend.

2160-340 3-P ί · ptd Page 82 499823 丨 Description of Invention (79) The printed circuit of the second example will be described with reference to Figure 16 This figure shows the most used chip capacitors. As for the general cutting line, Fig. 16 (B) shows the wafer 1 picture. As shown in Fig. 16 (B), the second example is a three-chip example. It is used for a large number of chip capacitors. This second example uses a large chip capacitor with a large chip capacitor. In addition, because a large 20 is used, even if the heating cycle is repeated, the printed circuit board is not included in the above-mentioned embodiment. The chip capacitor is built in I, but i can be replaced by a conductive film provided on a ceramic plate. Chip capacitors. The manufacturing method according to Example 3 can be used in the core base unit to shorten the distance between the 1C chip and the capacitor, and reduce the loop inductance. In addition, a resin substrate can be laminated to obtain a core substrate. And because the i-board and the third resin substrate are arranged on both sides of the core substrate, the core substrate is smoothly formed, and an interlayer resin insulation layer is appropriately formed on the rear substrate and the defective rate of the printed circuit board is reduced. In addition, according to the manufacturing method of the third embodiment, the interlayer window t is determined by the opening diameter of the metal film, so that the window can be opened appropriately. Similarly, the opening position precision of the interposer window depends on the opening position. Therefore, even if the laser irradiation position is precise, the interposer window is formed at an appropriate position. ί. The (A) point chain-shaped line shows [the plane junction of the container is plural (Figure j uses a large-scale | The core of the circuit board has sufficient strength. The first resin base 3 can be used in the core circuit. The opening diameter can be reduced by 2. The opening diameter is formed by the aperture. The density of the metal film is also low.

499823 V. Description of the invention (80) '----, = can also be connected from the lower part of the capacitor, so shortening the distance of the loop inductive reactance is a structure that increases the freedom of deployment. In addition, since the resin is filled between the core substrate and the capacitor, even if stress due to the capacitor occurs, it can be alleviated without shifting. Therefore, it does not affect the glass and dissolution of the junction between the capacitor electrode and the interlayer window. Therefore, even if a reliability test is performed, the desired performance can be maintained. Also, when a capacitor is covered with a steel slope, it is possible to prevent the occurrence of offset. (Embodiment 4) First, a printed circuit board according to Embodiment 4 of the present invention will be described with reference to Figs. Fig. 42 shows a cross section of the printed circuit board 610, and Fig. 43 shows a state where the IC chip 690 is mounted on the printed circuit board 61 shown in Fig. 42 and mounted on the daughter board 694 side. Fig. 44 (A) is an enlarged view of the interposer window 660 in Fig. 42 and Fig. 44 (B) is a view showing the interposer window 660 in Fig. 44 (1) viewed from the arrow b side. State of the via window 760. The printed circuit board 6 10 shown in FIG. 42 is an interlayer | I resin insulating layer 650 composed of a core substrate 630 that houses a plurality of chip capacitors 620 and additional layers 680A and 680B. Multiple wafers housed in the core substrate 630! The electrodes 621 and 622 of% Valleyr 62 0 are connected to a relatively large interlayer window mo. In addition, the superimposed wiring layers 680 A and 680 B are composed of an interlayer resin insulating layer 40 and _ 7 41. A conductor circuit 7 58 and a relatively small interlayer window 760 are formed on the interlayer resin insulation layer 7 4 0, and a conductor circuit 759 and a relatively small interlayer window 764 are formed on the interlayer resin insulation 741. Interlayer resin insulation;

2160-3403-Pi-ptd Page 84 --- ^ 499823 V. Description of the Invention (81) 741 is equipped with a solder photoresist layer 670 The chip capacitor 620 is the first electrode shown in Figure 13 (A) "I It is composed of the second electrode 6 2 2 and the electromotive body 23 which sandwiches the first and second electrodes. On the electromotive body 23, a plurality of second electrodes connected to the first electrode 621 side are arranged! The conductive film 24 and The second conductive film 25 is connected to the side of the second electrode 622. Alternatively, two parts of the first electrode 21 and the second electrode 22 of the capacitor 620 shown in FIG. 13 (B) may be exposed to cover 28 The exposure of the first electrode 21 and the second electrode 22 can improve the continuity of the interlayer window with the clock.

As shown in FIG. 43, a bump 67611 is formed on the interlayer window 764 of the superimposed wiring layer 680A on the upper side to be connected to the pad 692 of the IC chip 690. On the other hand, on the lower interposer window 760 of the superimposed wiring layer 6608, a bump & 676d is formed around the pad 694 which continues to the daughter board 695. The core substrate is made of resin. For example, it can be used for general printed circuit boards, such as a glass-breaking epoxy resin, a 3π substrate, and a resin-impregnated substrate. However, do not use substrates such as ceramics and aluminum substrates as core substrates. This substrate has poor formability and cannot accommodate capacitors, and voids may still be generated during filling. Shen Yueshu said that because of the storage in the recess 734 formed in the core substrate 630. Since the capacitor 620 can be used to arrange the chip capacitors 2π at a high density, and since a plurality of chip capacitors 620 are housed in the recess 734, the height of the 6 ^ 0V tender crystal capacitors 620 can be averaged to the chip capacitance Rfin 1 , The height of ㈢640 can form the interlayer window bb U appropriately. Probably, ixj vl can reduce the distance between the C chip 690 and the chip capacitor 6 2 0 so that the loop inductance can be reduced.

2 160-3403-FI-ptd p. 85 499823

Fifth invention description (82) In addition, as shown in FIG. 44 and FIG. 44 (A) of the enlarged view of the via window 660 of FIG. 42 and FIG. 43, the via window 760 of the overlay wiring layer 680A on the upper side is connected in succession. To 1 via window 660. The large interlayer shown in Fig. 44 (B) | I window 66 is an inner diameter of 125 / zm, a ridge diameter of 165 / zm, a small interlayer window of 760, an inner diameter of 2 5/2 m, and a ridge diameter of 6 5 # m. On the other hand, the chip capacitor 6 2 0 is formed in a rectangular shape, and the first electrode 621 and the second electrode 622 are also formed in a rectangular shape with a side 2 5 0 // m. Therefore, even if the placement position of the chip capacitor 6 2 0 is several tens, the connection between the first electrode 6 21 and the second electric electrode 622 of the chip capacitor 620 and the interlayer window 660 can be obtained, and the chip capacitor can be carried out on the spot. | | 620 to 1C chip 690 power supply. In addition, by providing a plurality of interlayers | I window 7 6 0, the same effect as that of the inductive reactance can be obtained in parallel. Therefore, the high-frequency characteristics of the power supply line and the ground line can be improved, and insufficient power supply can be prevented. Or the 1C chip may malfunction due to a change in the degree of grounding. In addition, since the wiring length from the 1C chip to the chip capacitor 620 can be shortened, the loop inductance can be reduced. As shown in FIG. 42, the interlayer window 660 is filled with electroplating to form a filled interlayer window with a flat surface. Thereby, a plurality of vias 760 can be directly connected to the vias 660. Thereby, the continuity of the interlayer window 660 and the interlayer window 760 can be improved, and the power supply from the chip capacitor is 620 to the IC chip 690 can be performed on the spot. Furthermore, in this embodiment, a filled interlayer window is formed by using electric filling, but instead, a filled interlayer window in which a metal film is arranged on the surface after filling the resin with ^^ is used instead. In addition, the thermal expansion coefficient of the resin filler 633 and the lower part of the chip capacitor 62〇 || The material 636 is smaller than the core substrate 630 and the resin insulation 64.

499823 Γ-—I. V. Description of the Invention (83) That is, it is set near the ceramic capacitor 6 2 0 of the chip. For this reason, in the heating cycle test, even if internal stress caused by the thermal expansion coefficient occurs between the core substrate 630 and the resin insulating layer 640 and the chip capacitor 620, it is difficult for the core substrate 6 3 0 and the resin insulating layer 6 4 0 to crack and peel. And so on, and can reach | into a high reliability. In addition, since the through-hole 6 5 6 is formed in the resin layer 633 between the chip capacitors 620, and the chip capacitor 6 2 0 composed of ceramics does not pass through the signal line, no discontinuity due to the inductance of the high electromotive body will occur. Reflection and delay due to transmission through highly electromotive bodies. Furthermore, since wiring is also provided at the lower portion of the capacitor, it is possible to increase the degree of freedom 5 of the external terminals such as wiring and bolts, and to increase the density and size. The chip capacitor 6 2 0 is coated with a copper plating film 29 on the surface of the metal layer 26 constituting the first electrode 6 21 and the second electrode 622 as shown in FIG. 13 (A). The slope of the plated film is formed by electrolytic plating, electroless plating, or the like. Then, as shown in FIG. 42, the first and second electrical electrodes 6 21, 622 coated with copper plating film 29 are plated with copper through the dielectric layer window 66, and electrical connection is obtained. Here, the electrodes 621 and 622 of the chip capacitor have irregularities on the surface of the metallized composition I. Therefore, in a state in which the metal layer 26 is exposed, and an opening 6 3 9 is formed in the resin insulating layer 640, which will be described later, resin will remain on the unevenness. At this time, poor contact between the first and second electrodes 621 and 622 and the interlayer window 660 may occur due to the residual resin. On the other hand, in this embodiment, the surfaces of the first and second electrodes 621 and 622 are smoothed by the copper plating film 29, and an opening 6 3 9 ^ is formed in the resin insulating layer W 0 that covers the electrodes. At this time, no resin remains, which can improve the connection reliability between the electrode 499823 and the electrode 499823 when forming the interlayer window 60. (84)-~ -1 | 621, 622. j; On the electrodes 621 and 622 where the copper plating film 29 is formed, since the interlayer window 660 is formed by electroplating, the continuity between the electrodes 621 and 622 and the interlayer window 6 60 is increased. No disconnection will occur between 621, 622 and the interlayer window 660. I Further, the above-mentioned copper plating film 29 is provided by separating the nickel and tin layers on the surface of the metal layer 26 at the stage of mounting the printed circuit board with the nickel capacitor layer tinned to the surface of the metal layer 26 during the manufacturing stage. Instead, in the manufacturing stage of the chip capacitor 62, a copper plating film 29 may be directly sloped on the metal layer 26. That is to say, in the present embodiment, after the opening of the copper plating film 29 provided with a laser to the electrode is subjected to a process such as residue removal, the interlayer window is formed by copper plating. Therefore, an oxide film is formed on the surface of the copper plating film 29, and the oxide film can be appropriately connected because the oxide film is removed by the above-mentioned laser and I j residue removal treatment. j In addition, it is also possible to use a ceramic composition of the chip capacitor 620 as an inducer 23

A roughened layer 23α is provided on the surface of. Therefore, the adhesion between the wafer capacitor 620 made of ceramics and the resin insulation layer 640 made of resin is improved, and even if the heat cycle test is performed, the resin insulation layer 64 is not peeled off at the interface. This roughened layer 23 α is formed by polishing the surface of the wafer capacitor 62 0 after firing, or by subjecting the roughened layer to a roughening treatment before firing. Furthermore, in this embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin, but a silane bonding treatment may be applied to the surface of the capacitor instead. Continuing, the manufacturing method of the printed circuit board described above with reference to FIG. 42 will be described with reference to FIGS. 37 to 42.

2160-3403 *-?]-Pid p. 88 499823

V. Description of the invention (85) U) Firstly, a core substrate 63 composed of an insulating resin substrate (J is the starting material (refer to FIG. 37 (A)). Then, a countersink is provided on the -I 1 surface of the core substrate 630 Process or provide through-holes in the insulating resin, and extrude them to form capacitor recesses 734 (refer to Figure 37 (B)). The recesses 734 are larger than the number of recesses. Capacitors are formed in a large size. By this, a plurality of capacitors 0 can be reliably arranged on the core substrate 6 3 〇

After that, on the recessed portion 734, an adhesive material I | material 636 is applied using a printer (see FIG. 37 (C)). At this time, in addition to coating, methods such as depositing, depositing, laminating, and bonding a thin plate may be used to coat the recessed material. The material 636 is made of a material having a smaller thermal expansion coefficient than that of the core substrate. Next, a plurality of ceramic capacitors 620 are bonded to the recessed portion 734 via the bonding material 636 (see FIG. 37 (d)). Here, by arranging a plurality of chip capacitors 620, | on the bottom-smooth recessed portion 734 described later, the height of the plurality of chip capacitors 620 can be averaged. Thereby, a resin insulating layer 64 of an average thickness can be formed on the core substrate 630 in a step described later, and an interlayer window 660 can be appropriately formed. Yes, the upper surface of the plurality of chip capacitors 620 is squeezed or tapped to have an average south degree (refer to FIG. 2 (A)), and the upper surfaces of the plurality of chip capacitors 620 are at the same height. With this step; when a plurality of chip capacitors 62G are arranged in ij in the recess ⑽, even if the two chip capacitors 620j are changed slightly, the height can be completely averaged, and the core substrate 630 (3) The chip capacitors 620 in the recess 734 are filled with heat. V. Description of the invention (86) " A hardening resin is cured by heating to form a resin layer 633 (refer to FIG. 38 (a)). The chip capacitor 620 is preferably epoxy, phenol, polyimidazole, or triphine, which can be fixed in the recess 734. Resin layer! 633 is the one that makes the thermal expansion coefficient of 罔 smaller than that of the core substrate. ▲ In addition, resins such as thermoplastic resins can also be used. In order to integrate the thermal expansion rate in the resin, a filler (f 丨 丨 ler) may also be impregnated. The filler is an inorganic filler, a ceramic filler, a metal filler, or the like. The dagger (4) is coated with a resin composed of an epoxy-based resin described later using a printer to form a resin insulating layer 64 (see FIG. 38 (B)). In addition, j 'can also be affixed with a resin film instead of coating resin. In addition, resins such as thermosetting resins, thermoplastic resins, composites of photosensitive resins, thermosetting resins and thermoplastic resins, and composites of photosensitive resins and thermoplastic resins can be used. Resins composed of two or more layers may be used. (5) Next, a relatively large dielectric layer opening 639 is formed in the resin insulating layer 64 with a laser (refer to FIG. 38 (c)). After that, the residue removal process is performed. It is also possible to perform "exposure" development processing instead of laser. Therefore, a through hole 644 for a through hole is formed in the resin layer 633 by drilling or laser, and is hardened by heating (see Fig. 38 (D)). As appropriate, Roughening treatment of permanganic acid and other chemical liquids and plasma treatment can also be applied. This can ensure the adhesion of the roughened layer. (6) After that, electroless copper plating is used. A copper plating film 729 is formed on the surface of the resin insulating layer 64 (refer to FIG. 39 (A)). It can also be used instead of electroless plating for sputtering of Ni-CU alloy as a target, or

2160-3403-Fi -Ptd Page 90

499823] V. Description of the invention (87) A " " A! If Ni-Cu alloy layer is provided, it may also be formed by sputtering to form an electrolytic plating film. (7) Next, a photosensitive dry I film 'is attached to the surface of the copper plating film 729, a photomask is placed thereon, and exposure / development processing is performed to form a predetermined pattern of light | resist 649. Then, the core substrate 6 30 is immersed in the electrolytic plating solution, and a current flows through the copper electrode | plating film 7 2 9 to fill the non-formed portion of the photoresist 6 4 9 with the electrolytic plating 6 5 1 (refer to FIG. 3 (B)). (8) After removing the photoresist photoresist 6 4 9 with 5% Na Na Η, the copper electrostrip film under the photoresist photoresist 6 4 9 is treated with this combined solution of sulfuric acid and peroxide peroxide for a while | 729 is dissolved and removed to form a relatively large interlayer window and interlayer window 656 of a filled interlayer window structure composed of copper electroplated film 729 and electrolytic copper electroplated film 651. The diameter of the large via window is preferably in the range of 100 to 60 () / zm. Particularly good is 125 ~ 350 / zm. In this case, it is formed by 165. The perforation is formed at 2 5 0 // m. Then, on both sides of the substrate, an etching solution is blown on. The surface of the opening 660 and the land surface of the through-hole 656 are etched, and the entire surface of the interlayer window 660 and the through-hole 656 is etched. Shape! Form a roughened surface 6 6 0 α (refer to Figure 39 (C)). (9) After that, the through-hole 656 is filled with a resin filler 664 containing an epoxy resin as a main component and dried (refer to FIG. 39 (D)). (10) Both sides of the substrate after the above steps are heated to 50 ~ 150 t on one side: and a pressure of 5 kg / cm2 is used to press and laminate a thickness of 50 thermosetting epoxy resin sheets (shee t), and An epoxy resin composition | interlayer resin insulating layer 74 0 is provided (refer to FIG. 40 (B)). The vacuum degree is 1 OmmHg. Cycloolefin resin can also be used instead of epoxy lime tree.

2160-3403-Pi-ptd Page 91 499823 V. Description of the Invention (88) Fat. U is connected to 4, and a CO2 gas laser is provided on the interlayer resin insulation layer 74o to provide a relatively small interlayer window opening of 6 5 // in 6 4 2 (refer to FIG. 4 (b)). The diameter of the relatively small interlayer window is preferably in the range of 25 to 100 "melons. After that, the residue is removed using a gas-electric paddle.

I (12) Next, the surface of the interlayer resin insulating layer 740 was roughened using a residue removal treatment process made by Nippon Vacuum Technology Co., Ltd. to have a thickness of 646 (see Fig. 4 () (c)). At this time, argon gas is used as the inert gas, and the electric violet treatment is performed for 2 minutes under the conditions of electric power of 200 W, gas pressure of 0.6 Pa, and temperature of 7 (rc). Roughening may also be performed using oxygen or an oxidizing agent. A roughened layer is preferred For 〇 ·〗 ~ 5, melon. German officials used the same 4 ′ exchange argon gas 爰 ... U as the target and sputtered at a pressure of 0.6pa, a temperature of 80t, a force of 20f, The time of 5 minutes of Gedu, 隹 —electrical μ I ^ π conditions, and the thickness of the Ni-Cu alloy ® LL layer 648 formed on the surface of the interlayer resin insulation layer 740 is 0.2 _ t6 昭 48 This ;; 'formed Ni-Cu metal / xm I refer to Figure 40 (d)). It is also possible to apply a red + electro-deposited upper ore film, or to apply an electric ore film on sputtering. The photosensitive dry film was formed and the substrate was processed at 63 °: on both sides ^ ^ The film was developed with 0.8% sodium carbonate imaging film after exposure with 1GGm " 2, 650. Next, the following circuit photoresist electrolytic plating film 652 with a thickness of 15 ((see; electroplating to form an additive in the solution with a thickness of 15_ is: f, (f 41 (A))) ° Furthermore, the electrolytic plating hydraulic HL. -499823 made by the company V. Description of the invention (89) [Electrolytic plating solution]

2.24mo 1/1 0.26 η ο 1/1 μ > 19.5 mo 1/1 1 A / d m2 manufactured by the company 6 5 minutes 22 ± 2 ° C sulfuric acid copper sulfate

Additive (7 h at C ^ ^ '> F HL) [Electrolytic plating conditions] Current density time temperature (15) stripped with 5% NaOH to remove the plating photo resist wo, then contacted with a mixture of nitric acid and sulfuric acid and hydrogen peroxide The Ni-Cu gold 1 layer 648 under the electric photoresist is engraved and dissolved and removed to form a conductor circuit 7 58 and a dielectric window 6 6 which are composed of Cu metal layer 648 and electrolytic steel plating film 652. Multiple relatively small interposer windows on 0? 60 (refer to FIG. 41 (b)). In this embodiment, the via window structure filled with the via window 66 is used to directly connect a plurality of via windows 760 to the via window. Then, refer to page 43. The figure illustrates the placement of the IC chip on the printed circuit lake (refer to Figure 42) and the mounting on the daughter board; solder! == solder pad 692 corresponds to the fresh tin of the completed printed circuit board 61 The bump 676U is placed on the IC chip 690 to perform the soft dissolving wafer 690. Similarly, the pad β9m of the daughter board 695 is corresponding to the solder bump 6 dove of 61 ° for soft dissolving and printing is performed. It is mounted to the daughter board 695. The above-mentioned resin film is composed of hardly soluble resin, soluble particles, hard

Issue 9823

Chemical agents, other ingredients. j (First Modified Example of Embodiment 4)! Continuing, a printed circuit board 61 2 of a first modified example of Embodiment 4 of the present invention will be described with reference to FIG. 52. The above-mentioned embodiment 4 is explained by the person who sets up the BGA. The first modified example of the fourth embodiment is substantially the same as that of the fourth embodiment, but is formed by continuing the PGA method via the conductive contact bolt 69 6 as shown in FIG. 52. The manufacturing method of the printed circuit board according to the first modification of the fourth embodiment of the present invention described above with reference to FIG. 32 will be described with reference to FIGS. 45 to 5 continuously. j (1) First, four resin layers are impregnated with epoxy resin,

638 is laminated on the laminated plate 730α to form a chip capacitor receiving through hole 733a. On the other hand, it is prepared to laminate the two layers with the resin layer 638 to form a laminated plate 730/3 (see FIG. 45 (A)). Here, in addition to epoxy and I, a reinforcing material containing BT, a phenol resin, or a release cloth can be used as the | then obtained by using a resin layer 6 3 8. 'j (2) Next, the laminated plate 730α and the laminated plate 730 and 5 are laminated and heated to be hardened. A core substrate 6 3 0 having a recessed portion 735 capable of accommodating a plurality of chip capacitors 620 is formed 6 3 0 (refer to FIG. 4 5 (B). ). (3) Therefore, infusion of capacitors in the recesses 7 3 5 is used.

(dispenser) and apply the adhesive material 636 (see FIG. 45 (C)). Alternatively, a bonding material may be applied to the recessed portion by printing, die bonding, and bonding to a thin plate. Thereafter, a plurality of chip capacitors 620 made of ceramic are housed in the recess 735 via the bonding material 636 (see FIG. 45 (D)). less

V. Description of the invention (91) π # After that, the chip capacitors 62 in the recess 735 are filled with a thermosetting resin: thermosetting by two holes to form a resin layer 633 (refer to FIG. 46 (A), FIG. 4; t: ' The thermosetting resin is preferably epoxy, polystyrene, or polyphenol. The chip capacitor 620 in the recessed portion 735 can be fixed to the pig. Λ # v5 二 亚 And the ring described later is applied using a printer. Oxygen-based resins are coated with turpentine to form a resin insulating layer 640 (see FIG. 46 (B)). Alternatively, a resin film (fi 1 m) may be attached instead of the coating resin.

(6) Next, a relatively large opening for an interposer window 63 9 is formed on the resin insulator 64 by exposure development processing or laser (see FIG. 46 (c)). The diameter of the large via window is preferably in the range of 100 to 60 (). Particularly good is 125 ~ 350 / zm. In this case, it is formed at 165 / 2m. Then, through holes or lasers with a diameter of 25 mm are formed in the resin layer 633 by drilling or laser, and heat-hardened (see FIG. 46 (D)). (7) Then, palladium catalyst was applied to the substrate, and the core substrate was immersed in the electroless plating solution, and the electroless plated film 745 was deposited on average (see FIG. 47 (A)). … S, the inside of the opening 639 of the electroless plated film 74 5 is filled with a resin filler and dried. Thereby, a resin layer 747 is formed inside the opening 639 (refer to FIG. 47 (B)).

After that, a photosensitive dry film is laminated on the surface of the electroless plated film 745, and a photomask film is placed on the surface of the electroless plated film 745, and exposed to beta development processing to form a predetermined pattern of photoresist 649. Then, the core substrate 630 is immersed in the electrolytic plating solution to change from the electroless plating film to the cap plating 7 51 (see FIG. 47 (C)). (9) After the above steps, strip and remove the photoresist with 5% NaOH

^ 160-3403-Fi-ptc Page 95 499823 V. Description of the invention (92) The electroless plating film 745 under the plating photoresist β 4 9 was etched with a mixed solution of LI and peroxide lice to dissolve and remove A relatively large via window 661 and a through-hole 656 (refer to 47, 1) forming the structure of the filled via window are shown in FIG. With the structure of the interposer window ⑽1 as a filled interposer window, a plurality of interposer windows 760 can be directly connected to one interposer window 661 in the step described later. (10) Then, after washing the substrate 630 with acid and degreasing, soft etching is performed. Then, the etching solution is etched on both sides of the substrate 63 and the surface of the via window 661 and the through hole 656 are etched. Ridge surface and inner wall, and a forms a roughened surface 6 63 on the entire surface of the interposer window 661 and the through hole 656 (refer to FIG. 48 (A)). The etching solution is composed of 10 parts by weight of copper imidazole (丨 丨) composite, 7 parts by weight of glycolic acid, and 5 parts by weight of sodium chloride. (11) Next, the bisphenol F-type epoxy monomer (oilification >; manufactured by t children's company, molecular weight .310, YL983U) 100 parts by weight, coated with silane bonding agent on the surface average particle diameter of 1 · 6 // m, the largest particle diameter of Si02 spherical particles below 5 # m (Manufactured by Qin F 亍 · ν Xi Co., CRS 1 1 01 -CE) 1 70 weight part and plane agent (1 eve 1 1 i ng) (Dream > / text 3 manufactured by Epy) 1 · 5 weight The part is placed in a container, and a resin filler having a viscosity of 45 to 49 Pa at 23 ± 1 c is prepared by stirring and mixing. Also, use microphones. Set hardener (manufactured by Shikoku Chemical Co., Ltd., 2E4MZ-CN) 6 · 5 parts by weight as hardener.

After that, the resin filler 646 is filled in the through-holes 656 and dried (see FIG. 48 (B)).

21 60-3403-Ρί · ρΐα Page 96 V. Description of the Invention (93) (U) Next, the bisphenol humanoid is cyclized > Engineering 3 made by N Corporation-Bu Yue Yue (epoxy equivalent 469, oil § 30 parts by weight per phenolic solid epoxy resin (epoxy 1! 弋), manufactured by Cresol Industry Co., Ltd. " $ 215, Dainippon hk chemical structure, built solid epoxy tree, m 旨 2, 3 times Japan Ink Chemical Industry Co., Ltd. manufactures lice milk base 1120, a large number of parts are heated and dissolved in beta A KA-7052 while stirring) 30 weight ethylene glycol acetic acid 20 weight parts. , And then add the terminal epoxidized polybutene rubber (yin manufactured by Li Pi Kasei Kogyo Kogyo Co., Ltd .. 51) If the heavy part and 2-phenyl-4,5-bis (hydrogenmethyl) flavor Saliva ί I, r, '^ ^ ^ ^ ^ ^ ^ ^ # 10. 5 t inside to prepare a% oxygen resin composition. Inside: The known epoxy resin composition is applied to a PET film having a thickness of // m by a roller coater, and the thickness is 50%, and then dried at a 80-120 C for 10 minutes to produce an interlayer. A resin film for a resin insulating layer. 0 3) On both sides of the substrate, a resin film for an interlayer resin insulation layer slightly larger than the substrate 63 prepared in (12) is placed, at a pressure of 4 kgf / c m2, a temperature of 80 ° C, and a pressing time After being pressed and cut under the conditions of 10 seconds, it was pasted using a vacuum laminator apparatus in the following manner to form an interlayer resin green layer 740 (Fig. 48 (C)). That is, the resin film for an interlayer resin insulating layer was laminated on the substrate 630 under the conditions of a vacuum of 0.5 Torr, a pressure of 4 kgf / cm2, a temperature of 80 ° C, and a pressing time of 60 seconds, and thereafter, it was allowed to stand at 1 70 ° C. Heat hardened for 30 minutes.

2ί60-3403-Ρί-ptd p.97 499823

% ， Hundred Fatty Fat Insulating Layer V. Description of the Invention (94)! (14)

1.2 Photomask 757 with 75h of through holes, with a CD2 gas laser on the thick U-lipid insulation layer 740 to form a relatively small interlayer window with a diameter of 65 trees

642 (Figure 48 (D)). The diameter of the relatively small interposer window is in the range of / zm. v J ibU (15) The substrate 63 that forms the opening 642 for the interlayer window is immersed in a solution containing 60 g / l of peracid for 10 minutes, and the ring existing on the surface of the interlayer j resin insulating layer 740 is dissolved and removed. Oxygen resin particles 5 so that the surface of the interlayer resin insulating layer 74o containing the inner wall of the mouth opening 642 is a roughened surface II 646 (Fig. 49 (A)). The roughening treatment may be performed with an acid or an oxidizing agent. The roughened layer is preferably 0. 1 to 5 // m. (16) Next, the substrate 630, which has been subjected to the above-mentioned processing, is immersed in a neutralization solution (> p γ) and washed with water. The catalyst core is attached to the surface of the interlayer resin insulation layer 740 and the opening 642 j I of the interlayer window by applying a palladium catalyst on the surface of the substrate with a roughening treatment (roughening depth 3 # m). Inner wall surface. I | (17) Next, the substrate was immersed in an electroless copper electroplating aqueous solution having the following composition, and an electroless copper electroplated film 763 (Fig. 49) having a thickness of 0.6 to 3.0 / zm was formed on the entire roughened surface 646. (B)).

I

ί [Aqueous solution of electroless plating] L 〇β 003 mol / 1 0,200 m ο 1/1 0.030 mol / 1 0 · 050 mol / 1 J NiS04 1 Tartrate I Copper sulfate

HCHO

2160-3403-Pi.pid Page 98 499823 I. Description of the invention (95) | I Na0H 〇. 100 mol / 1 a 5 α-Bipyridyl 40mg / l Polyethylene glycol (PEG) (KlOg / i! [Electroless plating conditions] j Liquid temperature of 35 ° C for 40 minutes I (丨 8) A commercially available photosensitive dry film was attached to the electroless copper plating film 763, and light was placed thereon. The mask was exposed at 100mj / cm2, and then developed with a 0 · 8% sodium carbonate aqueous solution to develop a plating resist 650 with a thickness of 30 / zm (Fig. 13! (▲)). Then the substrate was washed with 50 of its water. 6 30 and degreased, washed with 25 ° (: | | water, washed with sulfuric acid, and applied electrolytic copper plating under the following conditions, to form an electrolytic copper plating film 652 with a thickness of 20 / ZΠ1 (Figure 49 (C )). I [Electrolytic solution of electroplating] sulfuric acid 2. 24 mol / i copper sulfate 0.2 26 mol / 1 19,5 mo 1/1 manufactured by the company, square ,,? 5 > P HL) lA / dm2 6 5 minutes

Additive (7 h y y A > [Electrolytic plating conditions] Current density time

Temperature 2 2 ± 2 | (1 9) After stripping and removing the plating photoresist 6 50 with 5% NaOH, it was treated with a mixed solution of sulfuric acid | and hydrogen peroxide to dissolve and remove the photoresist under the electric forging photoresist j 650. The electroless key film 763 forms a conductor circuit 758 with a thickness of 18 // m and a relatively small 499823 composed of the electroless copper plating film Mg and the electrolytic copper plating film 652. V. Description of the invention (96) The interlayer window 760 (refer to FIG. 49) (D)). After " like processing, the row J containing the second copper complex and the organic acid is the same as (10), 6 2 (refer to Figure 50 (A)). The formation of the x liquid 'is roughened (20), and the above-mentioned interlayer resin insulating layer 741 and the conductor circuits q, and V are repeatedly formed by repeatedly operating the above-mentioned 丨 3 to 丨 9, and then formed 764 (refer to FIG. 50 (B)). ). 1 and the interlayer window (21) Next, and the embodiment! In the same manner, a finished product (organic resin insulating material) is obtained. Dry, first-resistance group (22) Next, on both sides of the multilayer circuit board, a solder resist composition prepared by (2 1) is applied. After that, a drying process was performed under the conditions of 70 ° C = 0 ° C and 70 ° C for 30 minutes, and then a solder mask = a mask having a thickness of 5 mm, in which the opening pattern of the solder mask was drawn in close contact. 1000mJ / cm2 ultraviolet exposure, and then treated with DMTG solution development, forming diameter openings 6 71U, 6 71 D. Therefore, heat treatment was performed at 81TC for 1 hour and 10 (TC for 1 hour, and 120% for 1 hour) to harden the solder resist composition to form openings.

671U, 671D solder resist layer 670 with a thickness of 20 // m (refer to Figure 51 (A y)) ° The above-mentioned solder resist composition can also use a commercially available solder resist composition.

(23) Next, the substrate on which the solder resist layer 670 is formed is immersed in an electroless plating solution in the same manner as in Example 1, and nickel plating with a thickness of 5 // m is formed in the openings 6 71 U and 6 71 D. Layer 672. This substrate was immersed in an electroless gold plating solution in the same manner as in Example 1 to form a gold plating layer 674 having a thickness of L03 / m on the nickel plating layer 672 (Fig. 51 (B)).

2160-3403-?!-Ptd Page 100 V. Description of the invention (97), 24) After that, a solder photoresist layer 670 containing a tin-lead surface is printed on the opening 671U of the substrate, and printed within 6m of the opening. Solder glue as: resistance. = Another:, Attach guide 697 to the appropriate tether retaining device. Then, the conductive portion 6 98 # of the fixed portion of the bolt 696 is supported by the bolt 696, and then the adhesive m is adhered. Then, the soft adhesive 98 is used to fix the conductive adhesive 697 in the junction 6A. Induction of electrical contact ^ ㈣ 696 with conductive electrical contact 1 接触 6 96 Installation method 杲 邋 邋 Receptive agent 6 9 7 Bonding to fixed mail rq δ worker &#% can also make it soft Solve 8 while women's conductive contact fine 6,

After that, the solder pad 692 of the iC chip 690 is placed in a state corresponding to the solder bump 676U of the opening 671_ of the printing mine I, the plate 612, and the core piece is 69G, and the IC chip is installed with a soft solution. (Refer to Figure ^). (Second modification of embodiment 4)

,,,,, '| A printed circuit board according to a second modification of the fourth embodiment of the present invention will be described with reference to Fig. 53. The printed circuit board 6 of the second modification of the fourth embodiment is substantially the same as that of the fourth embodiment. However, the printed circuit board 614 according to the second modification of the fourth embodiment is housed in a recessed portion 736 formed in the core substrate 630 | one chip capacitor 6 2 0. Because the chip capacitor 620 ′ is arranged in the core substrate 630, the distance between the iC chip 69 and the chip capacitor 62 can be shortened, and the loop inductance can be reduced. (Third modified example of the fourth embodiment) The configuration of a printed circuit board according to the third modified example of the fourth embodiment will be described with reference to Figs.

499823 I V. Description of the Invention (98) | The structure of the printed circuit board of the third modification is substantially the same as that of the first embodiment. However, the chip capacitors 20 accommodated in the core substrate 30 are different. Fig. I 14 shows a plan view of a chip capacitor. Fig. 14 u) The figure shows multiple | several chip capacitors taken before cutting, and a chain line in the figure shows the cutting line. In the printed circuit board of the first embodiment described above, the first electrode 2 i I and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of FIG. 4 (B). Fig. 14 (C) shows a plurality of chip capacitors for fetching | I in the second modification, and a dot chain line in the figure shows a cutting line. The printed circuit board of the second modification I | the modified example is in a state shown in a plan view of FIG. 14 (D), and the first electrode 2 and the second electrode 22 are arranged on the side edges of the chip capacitor. The printed circuit board of the third modification uses a chip capacitor in which an electrode is formed on the inner side of the outer edge. Therefore, a large-capacity chip capacitor can be used. jcontinued 'A printed circuit board of the first modification of the third modification will be described with reference to FIG. 15. Figure 15 is a plan view showing the chip capacitor 20 of the valley chip on the core substrate of the printed circuit board of the first alternative. In the above-mentioned embodiment i, a plurality of small-capacity chip capacitors are housed on a core substrate, but the other example is that a large-capacity large-scale chip capacitors 20 are housed on a core substrate. Here, the I chip ★ Electric Valley Fastener 20 is connected to the first electrode 21 and the second electrode 22, and the electric induction body 23, I = to > the first, first conductive film 24 of the electrode 21, and to the second electrode The second toad 2 and 3 on the electrode 22 side i is composed of an electrode 27 for connecting the upper and lower surfaces of the sheet-like valley state which are not connected to the second conductive film 24 and the second conductive film 25. The IC chip side and the daughter board are connected via the electrodes 27. 4The first printed circuit board used a large-scale chip because

P.102 499823 Description of the invention (99) Container 2 0 can be used. Capacitor chip capacitor 2 0 will not bend. 1 large chip capacitor. In addition, since a large circuit is used, the printed circuit board of the second example will be described with reference to FIG. 16 even if the heating cycle is repeated. Figure 16 (A) shows a chip capacitor for most biases, and a chain line at one point shows an unusual cutting line. Figure 16 (B) shows a plan view of the chip capacitor. As shown in FIG. 16 (β), the second example is a large-scale use of a plurality of chip capacitors (three fc examples in the figure) are connected and used in a large scale. Since a large chip capacitor is used, a large chip capacitor can be used. In addition, since a large chip capacitor 20 is used, even if the heating cycle is repeated, the printed circuit board does not bend. In the above-mentioned embodiment, the chip capacitor is embedded in the printed circuit board.

In the "i", instead of a chip capacitor, a plate-shaped capacitor I in which a conductive film is provided on a ceramic plate may be used. j ^ 〃 In addition, the fourth embodiment of Gongda only includes a crystal capacitor f5 accommodated in a core substrate. However, similar to the first example of the first embodiment, a large-capacity chip capacitor can be mounted on the surface and inside j. β As mentioned above with reference to Figures 12 and 12, the core substrate, that is, the vicinity of the c chip, is provided with a chip capacitor 20, or a chip capacitor with a large capacity (and a large inductive reactance) on the surface and inside, which can change the voltage Press to the minimum. j Here, the inductive reactance of the chip capacitor 6 2 0 embedded in the core substrate in the printed circuit board of Example 4 and the chip capacitor mounted on the inside of the printed circuit board (side of the daughter board side) were measured. Inductive reactance is shown below.

2160-3403-Pi-ptd Page 103 499823! 5. Description of the Invention (loo) 1

^ I

In the case of I capacitor unit j buried shape 137 pH | inside mounted shape 287 pH |!

I

Where 8 capacitors are connected in parallel I

! Buried 60 dH I-"

The internal mounting type 72 pH is shown above. When a single capacitor is used or connected in parallel to increase the capacity, the built-in chip capacitor can reduce the inductive reactance.

I Next, the results of the reliability test will be described. Here, the change in the capacitance of the chip capacitor in the printed circuit board of Example 4 was measured. Capacitance change rate (measurement frequency 100Hz) (measurement frequency 1 Hz) Steam 168 hours 0.3% 〇 β 4%! HAST 100 hours-0.9% -0.9% 1 Ί! TS 1 0 00 Cycle 1.1% 1.3% 1 Vapor test is to store steam at 100% humidity. In the HAST test, the relative humidity was 100%, the applied voltage was 1.3 V, and the temperature was 121 ° C for 100 hours. The TS test is repeated at -125 ° C for 30 minutes and 55 cycles for 30 minutes _ 100 0 times.

! In the above-mentioned reliability test, it was found that

ί The circuit board can also achieve the same reliability as the existing surface-mounted capacitors. I | i. Also, as mentioned above, the TS test shows that

2ί6ΰ-3403-? Ί · μίά Page 104 499823 ι .............................. .............. j. V. Description of the invention (ιοί) j

The thermal expansion coefficient of the core substrate and interlayer resin insulation layer composed of j street grease

Similarly, even if internal stress occurs, no disconnection will occur between the chip capacitor electrode and the interlayer I window, peeling will occur between the chip capacitor and the interlayer resin insulation layer, and the interlayer resin insulation layer will break, which can Long-term reliability. II The structure of the fourth embodiment is formed between the conductor circuit and the capacitor, forming the interlayer window of the fourth embodiment, so it will not operate due to insufficient power supply. I is slow, and the desired performance can be maintained, even The reliability test will not cause problems. I In addition, with this interlayer window, even if an interlayer resin insulation layer is formed,

^ I I interlayer window, causing a change in position, because its allowable range increases, can still confirm the electrical continuity. j

2L3403-P ('i) td Page 105

Claims (1)

499823 i Sixth, the scope of patent application | ι · A printed circuit board on the core substrate that houses the capacitor, interspersed with an interlayer resin insulation layer and a conductor circuit, wherein the core substrate that houses the capacitor is a first resin through a bonding board The substrate is laminated with a second resin substrate and a third resin substrate having an opening for accommodating an electric valley device. 2. The printed circuit board according to item 丨 in the scope of application for a patent, in which the core sheet is impregnated with a thermosetting resin. j The printed circuit board according to item 1 of the scope of patent application, wherein the second and third resin substrates mentioned above are impregnated with a core material in the resin. 4 · The printed circuit board according to item 1 of the scope of patent application, wherein the aforementioned capacitors are plural. < 5 The printed circuit board according to item 1 of the scope of patent application, wherein a conductor circuit is formed on the aforementioned second resin substrate. ^ 6. The printed circuit board according to item 1 of the scope of patent application, wherein a capacitor is mounted on the surface of the printed circuit board. 9. The printed circuit board according to item 1 of the scope of patent application, wherein the electrodes of the capacitor are opened with a metal film. 10 · The printed circuit board according to item 9 of the scope of patent application, wherein the metal film formed on the electrodes of the capacitor is a copper-based electroplated film 2160-3403-Ρί-ptd Page 106 499823 11 As described in item 1 of the scope of the patent application, the coating layer of the electrode of the aforementioned capacitor is exposed to at least the other layer electrically connected to the electrode of the exposed insect c printed circuit board, of which a part is obtained from the foregoing / such as The printed circuit board described in the scope of the patent application, using a chip capacitor formed with an electrode on the inner side of the evening edge as the aforementioned capacitor. 13. The printed circuit board described in the scope of the patent application, described above, wherein A chip capacitor forming an electrode is used as the aforementioned capacitor. '1 4 · The printed circuit board described in item 丨 of the scope of patent application, wherein a plurality of chip capacitors taken from the evening are used as the aforementioned ΫΒ. In the printed circuit board, the first resin substrate and the capacitor are bonded with an insulating adhesive, and the insulating adhesive has a smaller thermal expansion coefficient than the first resin substrate. 16. · A method for manufacturing a printed circuit board, including at least the following steps (a) to (d): (a) forming a conductor pad on a first resin substrate; (b) a conductor on the first resin substrate The capacitor is connected to the pad via a conductive adhesive; (c) a third resin substrate and a second resin substrate having an opening for accommodating the capacitor, and the first resin substrate; and the first resin substrate described above The capacitor is housed in the opening of the second resin substrate, and the third I resin substrate is inserted into the opening of the second resin substrate, and the laminate is laminated through the bonding plate; the first resin is ash (d). Substrate, the second resin substrate, and the third 2160-3403-Pf-ptd p. 107 499823 The resin substrate is heated and pressurized to form a core substrate. 1 ·· A printed circuit board having a resin insulation layer and a conductor circuit laminated on a core substrate; wherein the core substrate is bonded to form a plurality of resin substrates of the conductor circuit, and a capacitor is housed in the core substrate. j 18. A printed circuit board 5 has a wax insulation layer and a conductor circuit laminated on a core substrate, wherein the core substrate is bonded to form a plurality of resin substrates of the conductor circuit, and a capacitor is accommodated in a recess formed in the core substrate. . I 19. The printed circuit board 5 according to item 17 or 18 of the scope of the patent application, wherein the plurality of resin substrates are bonded via a bonding board. | 1, 20 · The printed circuit board 5 described in item 19 of the scope of patent application, in which the core board is impregnated with a thermosetting resin. 2 1 · The printed circuit board as described in item 17 or 18 of the scope of patent application, where the resin substrate is impregnated with a core material in the resin. I 22 · The printed circuit board according to item 17 or 18 of the scope of patent application, wherein the capacitor is plural. 1 23 * The printed circuit board according to item 17 or 18 of the scope of patent application, wherein a capacitor is mounted on the surface of the aforementioned printed circuit board. 1. 24. The printed circuit board according to item 23 of the scope of the patent application, wherein the capacitance of the chip capacitor on the surface is greater than the capacitance of the chip capacitor on the inner layer. I. The printed circuit board described in item 23 of the scope of patent application, where f is the chip capacitor on the surface and the chip capacitor on the inner layer is above the inductive reactance. -< a- Page 108 499823 6. Application scope 26 'The printed circuit board as described in the scope of application patent scope 17 or 18', wherein a metal lin is formed on the electrode of the aforementioned capacitor to be electroplated and electrically connected to the aforementioned metal film. electrode. 27. The printed circuit board according to item 26 of the scope of the patent application, wherein the metal film formed on the electrode of the capacitor is a copper-based electroplated film. 28. The printed circuit board as described in the 17th or 18th in the scope of patent application, In which, at least a part of the coating layer of the electrode of the capacitor is exposed, and the exposed electrode can be electrically connected from the coating layer. 2 9 · The printed circuit board according to item 17 or 18 of the scope of patent application, wherein a chip capacitor having electrodes formed on the inner side of the outer edge is used as the foregoing capacitor. | 30. The printed circuit board as described in item 17 or 18 of the scope of patent application, wherein a chip capacitor with electrodes formed in a matrix is used as the aforementioned capacitor 31. · As described in item 17 or 18 of the scope of patent application The printed circuit board uses a plurality of connected chip capacitors as the aforementioned I capacitors. I | 32 · The printed circuit board according to item 17 or 18 of the scope of application for patent, I j wherein the first resin substrate and the capacitor are bonded with an insulating adhesive, and the insulating adhesive is lower than the first resin substrate The thermal expansion rate is small. 3 3 · — A method for manufacturing a printed circuit board, including at least the following steps (a) to (e): 1 j (a) forming a conductor circuit on a plurality of resin substrates; i (b) laminating a plurality of layers through a bonding board Each of the aforementioned wax substrates; 2i60-3403-Pi-ptd Page 499499823 I Sixth, the scope of patent application '| (c) The aforementioned resin substrate is connected to the nucleation | core substrate through the aforementioned bonding plate; 乂! (D) on the aforementioned core substrate Forming a recess; and (e) accommodating the capacitor in the recess. 34 · —A method for manufacturing a printed circuit board, including at least the following steps (a) to (e): (a) forming a resin-based i-board having a through hole and a conductor circuit arranged on the surface; (C) A resin substrate with a through-hole and a resin substrate without a through-hole as described above are laminated via a bonding board without a through-hole; I (d) The resin substrate is connected to the nucleus | core substrate through the bonding plate; and Λ | I (e) stores the capacitor in the through hole. 3 5 · — a printed circuit board on the core substrate that houses the capacitor, The interlayer resin insulation layer and the conductor circuit are alternately laminated, wherein the core substrate for accommodating the capacitor is formed by laminating the i-th resin substrate, and the second resin substrate and the third resin substrate with openings for accommodating the electric power through a bonding board 5 On both sides of the core substrate, an I interlayer window is provided, which is connected to the terminals of the capacitor. 36. The printed circuit board according to item 35 of the scope of the patent application, wherein the core board is impregnated with a thermosetting resin. 37. The printed circuit board according to item 35 or 36 of the scope of patent application, 499823 6. Scope of patent application Wherein the aforementioned first, second and third resin substrates are impregnated with resin in the core material. 38. The printed circuit board according to item 35 of the scope of patent application, wherein the aforementioned capacitor is plural. 31. The printed circuit board 5 according to item 35 of the scope of patent application, wherein a conductor circuit is formed on the second resin substrate. 40. The printed circuit board according to item 35 of the scope of patent application, wherein a capacitor is mounted on the surface of the aforementioned printed circuit board. Yi Yi 41. The printed circuit board as described in item 40 of the scope of patent application, wherein the capacitance of the chip capacitor on the surface is greater than the capacitance of the chip capacitor on the inner layer. 4 "· As for the printed circuit board described in item 40 of the patent scope, the inductive reactance of the chip capacitor on the surface is above the inductive reactance of the chip capacitor on the inner layer. ▲ 4 ^ As in the fifth of the scope of patent application In the printed circuit board described in the above item, a metal film is formed on the electrode, and the electrode is returned to the metal film by electroplating and electrically connected to the electrode. 、 形 # The printed circuit as described in item 43 of the scope of patent application Plate, bean 1 formed in the aforementioned thunderstorm. 1 Aoba, the metal film of the r W electrode is a copper-based electric ore film The printed circuit board described in item 35 of the above-mentioned V Rongshen Second Specialized Scope, wherein the coating layer is electrically exposed to at least a part of the coating layer, so that the exposed electrode can be continued from the electric shield. The printed circuit board described in the 35th aspect of the patent application, wherein a chip capacitor with electrodes formed on the inner side of the substrate is used as the aforementioned capacitor. Six, apply for a special "quotation" " " " " ---------- ~ --- use ,; if you ask for the printed circuit board described in item 35 of the patent scope, where M The chip capacitors in which the electrodes are formed in a matrix are used as the capacitors. Use the printed circuit board described in item 35 of the scope of patent application, in which: a plurality of chip capacitors taken out are connected as the aforementioned capacitor. I The printed circuit board described in item 35 of scope of patent application, where Two = i resin substrate and the capacitor are bonded with an insulating adhesive, and the thermal expansion coefficient of the first resin substrate is smaller than that of the first resin substrate. 5 〇—A method for manufacturing a printed circuit board includes at least the following steps (a) to (d): I (a) mounting a capacitor on a first resin substrate through an adhesive material; I (b) placing a third A resin substrate and an opening for accommodating the capacitor; an I 2nd resin substrate and a first resin substrate; and a front return valley of the i-th resin substrate is received in the opening of the second resin substrate, and Put the 3rd resin substrate into the opening of the 2nd resin substrate, and laminate it via the bonding plate; (c) forming a dielectric layer on the core substrate with the laser irradiation 'on the core substrate An opening for a window; and I (d) forming an interlayer window on the aforementioned opening for an interlayer window. 51. A method for manufacturing a printed circuit board, including at least the following steps (a) to (f): | (a) forming an opening for forming an interlayer window on a metal film on one side of the first resin substrate; i; (b) bonding on the non-formed surface of the metal film of the first resin substrate 499823 I Sixth, apply for patent scope | Material and install capacitor I (C) Put the third resin substrate and the second resin substrate and the first resin substrate with an opening to accommodate the capacitor, and place the front of the i-th resin substrate ίν The capacitor is housed in the opening of the second resin substrate, and a state in which the third resin substrate is plugged into the opening of the second resin substrate is finally laminated on the board; ^ I (d) 1 resin substrate, the second resin substrate, and the third I i resin substrate are heated and pressurized to form a core substrate; j (e) is irradiated with laser light, and an opening for a dielectric window for placing the capacitor is formed on the core substrate. And (f) forming an interposer window in the aforementioned interposer window opening. 5 2 · — A method for manufacturing a printed circuit board, including at least the following steps: (a) to (f): I \ (a) The first resin substrate and the third resin-based I board with a metal film on one side An opening for forming an interposer window is formed on the metal film; (b) a capacitor is mounted on the non-forming surface of the metal film of the first resin substrate through a bonding material; j (c) a third resin substrate The opened I 2 resin substrate and the first resin substrate house the capacitor of the first resin substrate in the opening of the second resin substrate, and the third resin substrate is inserted into the second resin substrate. The state of the opening of the resin substrate is laminated via a bonding plate; (d) heating and pressing the first resin substrate, the second resin substrate, and the third I resin substrate to form a core substrate; 2160-3403-?!-Ptd Page 113 4 ^ 23 Patent application scope | eThe above-mentioned opening for the formation of the interposer window is formed on the aforementioned first resin substrate and the aforementioned third resin substrate by radiation, and Forming an opening for an interposer window in which the aforementioned electric container is placed; and i (1) forming an interposer window in the aforementioned interposer window opening. 53 · A method for manufacturing a printed circuit board, including at least the following steps (a) to (g) ... I (a) The first resin substrate and the third resin-based metal film with a metal film on one side A through-hole is formed thereon; (b) is bonded to the non-formed surface of the metal film of the first resin substrate The capacitor is made of I material; (c) The third resin substrate and the second resin substrate and the first resin substrate having an opening for accommodating the capacitor are housed in the aforementioned electric valley device. In the state of the second resin substrate, the third I resin substrate is plugged into the opening of the second resin substrate. The state 5 is laminated through the bonding board; II (d) the first resin substrate, the The second resin substrate and the third resin substrate are heated and pressurized to form a core substrate. (E) The through holes formed in the first resin substrate and the third resin substrate are irradiated with laser light, and the core substrate is formed in the core substrate. (F) removing the metal film or thinning it; and (g) forming a conductor circuit and a via window on the core substrate. 5 4 · — A printed circuit board with resin insulation and a conductor circuit laminated on a core substrate, wherein a capacitor is built in the core substrate and 2160-3403-Pi-ptd p. 114 2: The valley " relatively large lower interlayer window, on the core substrate and the interlayer resin insulation layer on the surface, a plurality of relatively small upper interlayer windows connected to the aforementioned lower interlayer window are arranged . 1, 5, 5 · The printed circuit board as described in item 54 of the scope of patent application, wherein the lower interlayer window is a filled interlayer with a flat surface filled with electroplating & The printed circuit board according to item 54, wherein the lower interlayer window described in month and month J is a filled interlayer window filled with resin to form a metal film on the surface. ^ 57. The printed circuit board according to item 54 of the scope of patent application, wherein the capacitor 1 is housed in a recess formed in the aforementioned core substrate. ^ 58. The printed circuit board according to item 54 of the scope of patent application, wherein the capacitors described above are housed in a plurality of recesses formed in the aforementioned core substrate. 59. The printed circuit board according to item 54 of the scope of application for a patent, wherein the electrode of the capacitor is formed with a metal film and is connected to the electrode forming the metal film by electroplating. 60. The printed circuit board according to item 59 of the scope of patent application, wherein the metal film formed on the electrode of the aforementioned chip capacitor is a copper-based electroplating _ film 0 61 · As any of the scope of application patents 54 to 58 The printed circuit board according to one item, wherein the coating layer of the electrode of the capacitor is exposed at least in part, and the exposed electrode can be electrically connected from the coating layer. Page 115 499823 62. The printed circuit board according to any one of claims 54 to 58 of the scope of patent application, wherein a chip capacitor having electrodes formed on the inner side of the outer edge is used as the aforementioned capacitor. 63. The printed circuit board according to any one of claims 54 to 58 of the scope of patent application, wherein a chip capacitor having electrodes formed in a matrix shape is used as the aforementioned capacitor. 64. The printed circuit board according to any one of claims 54 to 58 in the scope of the patent application, wherein a plurality of connected chip capacitors are used as the aforementioned capacitors. 65. The printed circuit board according to any one of claims 54 to 58 in the scope of the patent application, wherein the core substrate and the capacitor are filled with a resin having a smaller thermal expansion coefficient than the core substrate. 6 6 · A method for manufacturing a printed circuit board, including at least the following steps (a) to (e): (a) a capacitor is built in the core substrate; (b) a resin insulating layer is formed on the capacitor; (c) ) Forming a relatively large lower interlayer window on the aforementioned resin insulating layer to be in contact with the electrode of the aforementioned capacitor; (d) forming an interlayer resin insulation layer on the core substrate; and (e) disposing a relatively small upper interlayer window on the interlayer resin insulation layer to be connected to one of the aforementioned lower interfaces. Mine f7. The manufacturing method as described in item 66 of the scope of patent application, wherein before the 4 steps, a recess is formed on the core substrate, and in the front i recess, you & a capacitor. Page 116 499823 VI. Application for patent scope Where the manufacturing method described in the aforementioned 66th item of the aforementioned ϋ11㈣㈣ item 66 is one step private, a plurality of the aforementioned capacitors are housed in the recessed portions on the core substrate. ^ 6 9 · The manufacturing method as described in item 66 of the scope of patent application, wherein before the step of month] =), a through hole is formed on the resin plate, and a resin plate is pasted on the resin plate forming the aforementioned through hole, A core substrate having a concave portion is formed. 70. The manufacturing method according to item 66 of the scope of application for a patent, wherein when t is not to escape the lower interlayer window, it is filled with electroplating to form a filled interlayer window with a flat surface. Among them, on the surface, the manufacturing method described in item 66 of the patent application range is used to form the aforementioned lower interlayer window. After filling the inside with resin, the metal film is formed to form a filled interlayer window with a flat surface. 7 2 · The manufacturing method described in item β 8 of the patent application scope. After step (a) above, pressure is applied from above on the plurality of capacitors in the recess to make the heights of the capacitors uniform. 2160-3403-Ff-ptd Page 117