WO2010035865A1 - Package substrate for mounting semiconductor element and method for manufacturing the package substrate - Google Patents

Package substrate for mounting semiconductor element and method for manufacturing the package substrate Download PDF

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Publication number
WO2010035865A1
WO2010035865A1 PCT/JP2009/066917 JP2009066917W WO2010035865A1 WO 2010035865 A1 WO2010035865 A1 WO 2010035865A1 JP 2009066917 W JP2009066917 W JP 2009066917W WO 2010035865 A1 WO2010035865 A1 WO 2010035865A1
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WO
WIPO (PCT)
Prior art keywords
plating
conductive resin
package substrate
cavity
semiconductor element
Prior art date
Application number
PCT/JP2009/066917
Other languages
French (fr)
Japanese (ja)
Inventor
田村　匡史
学 杉林
邦司 鈴木
剛史 正木
Original Assignee
日立化成工業株式会社
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Publication date
Application filed by 日立化成工業株式会社 filed Critical 日立化成工業株式会社
Priority to KR1020117001679A priority Critical patent/KR101168825B1/en
Publication of WO2010035865A1 publication Critical patent/WO2010035865A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

Definitions

  • the present invention relates to a package substrate for mounting a semiconductor element that can be densified and a method for manufacturing the same.
  • PoP Package on Package
  • SiP System in Package
  • the semiconductor package must be coated with a potting resin or the like to protect the semiconductor element. Therefore, in a package in which a plurality of semiconductor elements are stacked on one semiconductor element mounting package substrate, the total height of the package becomes thick and it is difficult to reduce the thickness. Further, when the packages having the increased total thickness are stacked, as shown in FIG. 7, the sealant 3 placed higher than the connection terminal A ⁇ b> 14 inhibits the connection between the bottom package 35 and the top package 34. Therefore, the connection between the top package 34 and the bottom package 35 is performed using a solder ball 38 having a diameter larger than the height of the sealant 3 (for example, ⁇ 0.6 mm or more. In the following, ⁇ represents a diameter). There is a need to do.
  • the sealant 3 is generally raised to a height that is at least half the diameter of the solder ball 38 used for connection (ie, the inter-terminal distance 44). there were. If the diameter of the solder ball 38 is large, the diameter and pitch of the connection terminal A14 connected using the solder ball 38 must be increased accordingly. For this reason, it is difficult to reduce the size and pitch of the connection terminals A14 by increasing the diameter of the solder balls 38 used for connection between these packages.
  • Cited Document 1 since the sealant is in a convex state on the upper side (top package side) of the bottom package, there is a problem that the top packages that can be combined are limited and the degree of freedom is small. Further, in Cited Document 2, an insulating layer is formed to provide a cavity portion, and an interlayer connection with an external connection terminal through the insulating layer is performed by filling a metal layer in a through hole with electroplating. Plating leads for plating are required, and there are restrictions on higher density and design.
  • the lid plating ensures the connection reliability by applying a catalyst, followed by electroless plating as a base, further performing electrolytic copper plating, and thickening to some extent. Furthermore, nickel plating and gold plating are performed to ensure soldering of the connection terminal A14. Thus, since lid plating requires man-hours, there is a problem that leads to an increase in cost and lead time.
  • An object of the present invention is to provide a package substrate for mounting a semiconductor element that can be performed at a low cost by a simple process.
  • the present invention relates to the following.
  • a semiconductor device having a cavity layer having an opening and a through-hole, a base layer laminated on the cavity layer, a cavity portion formed by the opening, and a bottomed via formed by the through-hole.
  • a metal coating is formed on the inner wall of the bottomed via, and the bottomed via is filled with a conductive resin as a base, and the conductive component contained in the conductive resin is exposed in the exposed state.
  • a package substrate for mounting a semiconductor element which is disposed on the entrance side of a bottomed via and has a metal film formed by depositing plating directly on the exposed conductive component.
  • connection pad provided on the cavity layer side on the base layer and a connection provided on the opposite side of the base layer on the cavity layer and connected between the connection pads and the bottomed vias.
  • a semiconductor element having an interlayer connection for connecting to a terminal A, wherein the connection terminal A has a metal film formed by direct deposition on a conductive component contained in a conductive resin filled in the bottomed via.
  • Package substrate for mounting.
  • the plating for forming the metal film includes electroless nickel plating, electroless gold plating, electroless nickel plating and displacement gold plating or electroless gold plating Package substrate for device mounting.
  • the plating for forming the metal film is an electro nickel plating, electro gold plating, electro nickel plating and displacement gold plating, electroless gold plating, electroless gold plating or A package substrate for mounting a semiconductor element having electroplating.
  • a semiconductor device having a cavity layer having an opening and a through-hole, a base layer laminated on the cavity layer, a cavity portion formed by the opening, and a bottomed via formed by the through-hole.
  • a metal coating is formed on the inner wall of the bottomed via, and the bottomed via is filled with a conductive resin as a base, and the surface of the conductive resin is physically polished.
  • the degree of freedom of the package to be combined is large, the restrictions on the pattern design are small, and the connection between the top package and the bottom package can be performed with high density.
  • the package substrate and the manufacturing method thereof can be provided at a low cost with a simple process.
  • the package substrate 1 for mounting a semiconductor element of the present invention is formed by a cavity layer 5 having an opening 25, a base layer 6 laminated on the cavity layer 5, and the opening 25.
  • the semiconductor device mounting package substrate 1 having the cavity portion 9 is connected to the connection pad 11 on the base layer 6 and the connection terminal A14 on the cavity layer 5 through the cavity layer 5.
  • the semiconductor device mounting package substrate 1 in which the interlayer connection 31 is provided and the interlayer connection 31 is formed of the conductive resin 17 is exemplified.
  • the semiconductor package 36 manufactured using the semiconductor package substrate 1 of the present invention includes the semiconductor element mounting package substrate 1 having the cavity portion 9 and the cavity portion 9.
  • An interlayer connection 31 for connecting the connection pad 11 on the layer 6 and the connection terminal A14 on the cavity layer 5 is provided.
  • the semiconductor package 36 formed by 17 and the like.
  • the interlayer connection 31 of the cavity layer 5 is formed by the conductive resin 17, so that the interlayer connection 31 is formed by so-called filled via plating. Therefore, there is no need to provide a plating lead for power supply, so that the degree of freedom in design is large and the density can be increased accordingly.
  • the aspect ratio is larger than that of filled via plating (for example, the diameter of the bottomed via 13 for the interlayer connection 31 is ⁇ 0.2 mm, the depth is 0.2 mm to 0.55 mm)
  • the thickness of the cavity layer 5 can be made thicker (for example, about 0.2 mm to 0.55 mm).
  • the cavity 9 can be formed high, and it becomes easy to stack a plurality of semiconductor packages 36 in the cavity 9 as shown in FIG. Further, since the height of the cavity portion 9 can be formed such that the sealant 3 hardly protrudes, even when the semiconductor package 36 is formed by molding the sealant 3, the surface of the sealant 3 is It can be made flat so that it is not more than the same as the connection terminal A14, that is, hardly protrudes from the connection terminal A14. For example, as shown in FIG. 6, even when the semiconductor element 2 is stacked and mounted in the upper and lower two stages in the cavity portion 9, the surface of the sealing agent 3 is flat so that it hardly protrudes than the connection terminal A14.
  • the solder ball diameter for joining the semiconductor packages does not need to consider the height of the sealant 3 and can be joined even if a solder ball having a diameter of ⁇ 0.3 mm or less is used. . Even when a solder ball having a diameter of 0.3 mm is used, the uppermost portion of the sealant 3 of the bottom package 35 is in a state where the height is 1/3 or less of the solder ball ( ⁇ 0.3 mm) on the connection terminal A14. The top package 34 can be joined. In other words, the uppermost portion of the sealant 3 can protrude by a height of 1/3 or less (0.1 mm or less) of the inter-terminal distance 44 from the connection terminal A14.
  • the PoP when the PoP is configured by using the semiconductor element mounting package substrate 1 and the semiconductor package 36 of the present invention as the bottom substrate 33 or the bottom package 35, a general semiconductor package to be combined can be selected, and the degree of freedom can be selected. Is big. Further, since it is not necessary to increase the diameter of the solder ball for connection in consideration of the pop-out of the sealant 3, the diameter and pitch of the connection terminal A14 are reduced (for example, the terminal diameter is ⁇ 0.25 mm or less, the pitch 0.4 mm or less), and high-density connection is possible.
  • the interlayer connection 31 of the cavity layer 5 includes a connection pad 11 provided on the surface of the base layer 6 on the cavity layer 5 side, a bottomed via 13 formed in the cavity layer 5 with the connection pad 11 as a bottom surface,
  • the conductive resin 17 filled in the bottomed via 13 and the connection terminal A14 provided on the conductive resin 17 can be used.
  • the connection terminal A14 can be formed immediately above the interlayer connection 31, so that the connection terminals A14 can be arranged at high density. it can.
  • the connection terminal A14 on the cavity layer 5 is used as a so-called external connection terminal used for connection to another semiconductor element mounting package substrate 1, the semiconductor package 36, and a wiring board (not shown).
  • connection pad 11 provided on the surface of the base layer 6 on the cavity layer 5 side is a so-called internal connection terminal such as a wire bond terminal 12 or a connection terminal C27 for connecting to the semiconductor element 2, or a cavity of the base layer 6. It is connected to a connection terminal B15 provided on the surface opposite to the layer 5 side. Similarly to the connection terminal A14, the connection terminal B15 is used as a so-called external connection terminal used for connection to another semiconductor element mounting package substrate 1, the semiconductor package 36, and a wiring board (not shown).
  • the interlayer connection 31 of the cavity layer 5 desirably forms a metal coating 18 on the inner wall of the bottomed via 13 of the cavity layer 5. That is, it is desirable to form the metal coating 18 on the inner wall of the bottomed via 13 as the base of the conductive resin 17 filled in the bottomed via 13.
  • the metal coating 18 on the inner wall of the bottomed via 13 for example, it can be formed by electrolytic copper plating or electroless copper plating.
  • the inner wall of the low and low via 13 becomes smooth and the conductive resin 17 easily enters the bottomed via 13, so that the conductive resin 17 is easily filled.
  • the interlayer connection 31 is formed by both the metal coating 18 and the conductive resin 17 by plating, the reliability of the interlayer connection is improved.
  • connection terminal B15 is provided on the surface of the base layer 6 opposite to the cavity layer 5, and the connection terminal A14 can be formed to be smaller in size and pitch than the connection terminal B15.
  • connection terminal A14 is connected to another semiconductor element mounting package substrate 1 or the semiconductor package 36, high-density connection is possible. That is, when used as the PoP bottom substrate 33 or the bottom package 35, high-density connection with the top substrate 32 or the top package 34 is possible.
  • the uppermost part of the sealant 3 is desirably formed at a height equal to or lower than the connection terminal A14 of the package substrate 1 for mounting semiconductor elements.
  • the height equal to or less than that of the connection terminal A14 is assumed when the solder ball 38 provided on the connection terminal A14 has a diameter of 0.3 mm (that is, when the distance 44 between the terminals is 0.3 mm). Up to 1/3 or less of the diameter. That is, the height of the uppermost part of the sealing agent 3 is from the connection terminal A14 to a height of 0.1 mm. Accordingly, when the PoP is configured by using the semiconductor element mounting package substrate 1 and the semiconductor package 36 of the present invention as the bottom substrate 33 or the bottom package 35, the surface of the connection terminal A14 is flat.
  • connection terminal 37 surface of the package 34 As the connection terminal 37 surface of the package 34, a flat general one can be selected, and the degree of freedom is large. Further, since the diameter of the solder ball 38 for connection does not need to be increased in consideration of the pop-out of the sealing agent 3, high-density connection is possible.
  • the cavity portion 9 is a recess having a predetermined depth provided in the semiconductor element mounting package substrate 1 and is used as a space for mounting the semiconductor element 2.
  • the cavity portion 9 is formed by the cavity layer 5 having the opening 25 and the base layer 6.
  • an opening 25 is formed in the cavity layer 5 bonded with the adhesive 8 by router processing, punching, or the like.
  • there is a method in which the cavity layer 5 corresponding to the cavity portion 9 is removed after the cavity layer 5 and the base layer 6 are laminated. In this case, a photosensitive material can be used as the cavity layer 5.
  • the cavity layer 5 is a substrate that is laminated with the base layer 6 to form the cavity portion 9 that accommodates the semiconductor element 2, the connection pad 11 of the base layer 6 on which the semiconductor element 2 is mounted, and other semiconductor element mounting It is a board
  • the cavity layer 5 includes a cavity material 7 having an insulating layer, connection terminals A14 and an inner layer circuit 19 formed on the surface thereof, an adhesive 8 provided on the cavity material 7, and an opening 25 for forming the cavity portion 9. And a through hole A24 for the interlayer connection 31.
  • the inner layer circuit 19 By providing the inner layer circuit 19 on the side of the cavity layer 5 where the adhesive 8 is provided, the inner layer of the metal coating 18 in the through hole A24 is located at a position close to the connection point between the connection pad 11 and the metal coating 18 of the base layer 6.
  • the connection 20 can be formed, and in this case, the lifetime in the thermal cycle test can be improved and the reliability can be improved.
  • the inner layer circuit 19 is more preferably a so-called annular ring that completely surrounds the through hole A24 in terms of reliability. Further, when the cavity layer 5 and the base layer 6 are laminated and bonded by heating and pressing with the adhesive 8 interposed therebetween, even if the adhesive 8 flows, it acts as a dam that completely surrounds the through hole A24.
  • the coefficient of thermal expansion is generally larger than that of an insulating material such as glass epoxy used for the cavity material 7.
  • the metal coating 18, which is through-hole plating causes barrel cracks, or in the bottom of the bottomed via 13, the through-hole plating is performed. There is a concern that peeling may occur.
  • the adhesive 8 in a portion corresponding to the inner layer circuit 19 is formed thinner than the other portions. That is, the thickness of the adhesive in the portion sandwiched between the inner layer circuit 19 on the cavity material 7 and the photosensitive resin 10 in the base layer 6 is thinner than the portion not sandwiched between them. As described above, since the thickness of the adhesive 8 can be reduced around the bottomed via 13, the influence due to the large thermal expansion coefficient of the adhesive 8 can be reduced, and reliability can be ensured. Is possible.
  • the thickness of the adhesive is 10 ⁇ m to 50 ⁇ m and the thickness of the inner layer circuit is 9 ⁇ m to 18 ⁇ m, the portion corresponding to the inner layer circuit 19 (between the inner layer circuit 19 and the photosensitive resin layer 10).
  • the thickness of the adhesive 8 in the (part) is preferably 0.5 ⁇ m to 7 ⁇ m. Therefore, even when an elastomer material having a relatively large thermal expansion coefficient is used as the adhesive 8, the inner layer circuit 19 is a so-called annular ring that completely surrounds the periphery of the through hole A24. Reliability can be ensured.
  • the thickness of the inner layer circuit 19 is preferably 9 to 18 ⁇ m.
  • the cavity material 7 can be a general copper-clad laminate, a build-up material, or a film material used for manufacturing the semiconductor device mounting package substrate 1. Moreover, what was multilayered by combining these copper-clad laminates, build-up materials, and film materials can also be used.
  • the thickness of the cavity material 7 is selected according to the height at which the semiconductor elements 2 housed in the cavity portion 9 are stacked.
  • the pattern for forming the connection terminal A14 and the inner layer circuit 19 can be produced by a subtract method or the like.
  • the opening 25 and the through hole A24 can be formed by router processing, punching, or the like.
  • the adhesive 8 used for laminating the cavity layer 5 and the base layer 6 can be an epoxy or polyimide based adhesive 8 used for manufacturing the package substrate 1 for mounting a semiconductor element, and can be a press or laminate. It is desirable that it can be temporarily attached to the cavity layer 5 or the base layer 6 by, for example.
  • the adhesive 8 may be temporarily attached to either the cavity layer 5 or the base layer 6, or when the cavity layer 5 and the base layer 6 are laminated and bonded without preliminarily attaching, It may be used by being sandwiched between them.
  • a thermosetting resin is impregnated into a reinforcing fiber, heated and dried, and applied to a semi-cured prepreg or a polyethylene terephthalate film.
  • thermosetting resin epoxy resin, phenol resin, polyimide resin, bismaleimide resin or the like can be used, and as the reinforcing fiber, glass cloth, glass paper, amide cloth or amide paper can be used.
  • the adhesive 8 is preferably an elastomer material.
  • the adhesive 8 used as the elastomer material it should be used as long as it has sufficient adhesive strength and can absorb the distortion caused by the difference in dimensional change between the cavity layer 5 and the base layer 6. Can do.
  • the adhesive composition comprising 50 parts by mass to 150 parts by mass of the rubber component and 0.3 part by mass to 2.5 parts by mass of a curing accelerator to a base film and heat-treating the semi-cured state. It can be formed by peeling the curable adhesive sheet from the substrate film and heating and pressing with a vacuum press or the like.
  • the adhesive 8 that can be temporarily bonded to the cavity layer 5 and the base layer 6 by a laminator or the like is desirable from the viewpoint of workability.
  • the adhesive 8 has an elastic modulus of 100 MPa to 500 MPa at 50 ° C. after heating and pressing, and is preferably about 500 MPa.
  • the elastic modulus was measured by a DVE method using a Rhegel E-4000 type viscoelasticity measuring device manufactured by UBM Co., Ltd. under conditions of a tensile mode, a frequency of 10 Hz, and a heating rate of 5 ° C./min.
  • the amount of resin flow (the amount of resin flow from the end after heating and pressurization) can be 50 ⁇ m to 1500 ⁇ m, and is preferably 100 ⁇ m to 500 ⁇ m from the balance between moldability and the amount of exudation into the bottomed via. In particular, about 300 ⁇ m is desirable.
  • the resin flow amount was obtained by punching the adhesive 8 in a sheet state before heating / pressing into a 10 mm diameter circle, and sandwiching it with a PET (polyethylene terephthalate) film, and pressing (100 ° C., 3 Mpa) 5 minutes), the diameters of the samples were measured at three locations and averaged, and the difference from the dimensions before pressing was determined by calculation.
  • Examples of the rubber-modified epoxy resin include CTBN (carboxy group-terminated butadiene nitrile rubber) modified products and those having a modification rate of 30% to 60%.
  • Examples of the rubber component include epoxy group-containing acrylonitrile butadiene rubber having a molecular weight of 50,000 or more.
  • the semi-cured state can be obtained by setting the curing rate to 10% to 60% by heat treatment after being applied to the base film.
  • the adhesive 8 as an elastomer material absorbs distortion caused by the difference in the behavior of dimensional change between the cavity layer 5 and the base layer 6. Warpage of the element mounting package substrate 1 can be suppressed.
  • the adhesive 8 used for lamination.
  • the adhesive 8 include AS2600, AS3000, GF3500, and GF3600 (all are product names manufactured by Hitachi Chemical Co., Ltd.).
  • the thickness of the adhesive 8 can be 10 ⁇ m to 50 ⁇ m, preferably 20 ⁇ m to 50 ⁇ m, and particularly preferably 25 ⁇ m to 40 ⁇ m.
  • the thickness is smaller than this, a step due to the thickness of the inner layer circuit 19 of the cavity layer 5 cannot be filled, and it becomes difficult to absorb strain due to a difference in behavior of dimensional change between the cavity layer 5 and the base layer 6. If it is thicker than this, the movement of the adhesive 8, which is also an elastomer material, increases, and connection reliability may be reduced.
  • the base layer 6 is a substrate on which the semiconductor element 2 is mounted while forming the cavity portion 9 by being laminated with the cavity layer 5.
  • the base layer 6 is electrically connected to the surface of the base material 21 that is an insulating layer on the cavity layer 5 side by a wire bond terminal 12 that is electrically connected to a semiconductor, and the wire bond terminal 12 and a lead wire (not shown).
  • a connection terminal B15 for connecting to another substrate or the like on the surface opposite to the cavity layer 5 of the base material 21, and connected to these connection pads 11.
  • Interlayer connection 42 for electrically connecting terminal B15.
  • the pattern for forming the wire bond terminal 12, the lead wire (not shown), the connection pad 11, and the connection terminal B15 can be produced by a subtracting method or the like.
  • the base material 21 can be produced using a general copper-clad laminate or build-up material used for manufacturing the semiconductor element mounting package substrate 1. Moreover, as shown in FIG. 4, these copper-clad laminates can be used as a base material a28, build-up materials can be used as a base material b29 and a base material c30, and a base material 21 obtained by combining them can be used.
  • the interlayer connection 42 can be manufactured by forming a through hole or a non-through hole using drilling or laser processing and forming plating in these holes. In the above, the case where the electrical connection between the semiconductor element 2 and the connection pad 11 is performed only by the wire bond terminal 12 is described. However, as shown in FIG. The base layer 6 can be formed in the same manner when electrically connected by.
  • connection pad 11 is provided in a region other than the region corresponding to the cavity portion 9 on the surface of the base layer 6 on the cavity layer 5 side, and a bottomed via 13 having the connection pad 11 as a bottom surface is formed in the cavity layer 5.
  • the bottomed via 13 is formed by forming a through hole A24 in the cavity material 7 by drilling, laser processing, punching, router processing, etc., as shown in FIG.
  • the position of this through hole A24 and the connection pad This can be done by stacking the cavity layer 5 and the base layer 6 so that the positions 11 correspond to each other.
  • through-hole A24 is formed in both cavity material 7 and adhesive 8 by drilling, laser processing, punching, router processing, etc., and through-hole A24 of cavity material 7 and adhesive 8 is formed.
  • the adhesive 8 is temporarily attached to the cavity material 7 in alignment, and the cavity layer 5 and the base layer 6 are laminated so that the position of the through hole A24 and the position of the connection pad 11 correspond to each other. Can do.
  • a photosensitive resin layer 10 is formed on the side of the base layer 6 that is laminated with the cavity layer 5.
  • the adhesive for the cavity layer 5 is used.
  • the photosensitive resin layer 10 of the base layer 6 are desirably adhered to each other.
  • the adhesive 8 can be prevented from directly adhering to the connection pad 11 of the base layer 6, and the adhesive 8 spreads on the connection pad 11 during lamination, reducing the connection area and increasing the connection resistance. Or a reduction in connection reliability can be suppressed.
  • the photosensitive resin layer 10 has an effect of preventing the adhesive 8 from flowing onto the connection pad 11 during lamination. Further, the step due to the connection pad 11 etc. on the bonding surface of the base layer 6 to the cavity layer 5 can be flattened, and the adhesive 8 used for bonding to the cavity layer 5 is thin and has low fluidity. However, the follow-up of the adhesive 8 can be ensured.
  • a photosensitive solder resist used for manufacturing a wiring board or a mounting board can be used.
  • the photosensitive solder resist those generally used for semiconductor device mounting package substrates and wiring boards can be used.
  • liquid type PSR4000 (trade name, manufactured by Taiyo Ink Co., Ltd.)
  • dry film type Photec SR3000G (trade name, manufactured by Hitachi Chemical Co., Ltd.) can be used.
  • the bottomed via 13 is filled with a conductive resin 17.
  • Filling the bottomed via 13 with the conductive resin 17 can be performed by applying the conductive resin 17 by printing.
  • the aspect ratio of the bottomed via 13 is large, for example, by using a vacuum printing apparatus, it is possible to suppress the remaining of bubbles in the bottomed via 13 and to secure the filling property.
  • the metal coating 18 can be formed by, for example, electrolytic copper plating or electroless copper plating.
  • the inner wall of the low and low vias becomes smooth and the conductive resin 17 easily enters the bottomed via 13, so that the conductive resin 17 is easily filled.
  • the interlayer connection 31 is formed by both the metal coating 18 and the conductive resin 17 by plating, the interlayer connection reliability is improved.
  • the interlayer connection 31 between the connection pad 11 and the connection terminal A14 is formed by filling the bottomed via 13 with the conductive resin 17, and therefore, compared to filling with plating by so-called filled via plating, Therefore, it is not necessary to provide a plating lead for this purpose, so that the degree of freedom in design is large and the density can be increased accordingly.
  • the aspect ratio is larger than that of filled via plating (for example, the diameter of the bottomed via 13 for the interlayer connection 31 is ⁇ 0.2 mm, the depth is 0.2 mm to 0.55 mm), An interlayer connection 31 with the connection terminal A14 can be formed. For this reason, a plurality of semiconductor elements 2 can be stacked and stored in the cavity portion 9.
  • the uppermost portion of the sealant 3 can be set to a height equal to or lower than that of the connection terminal A14. Therefore, when the semiconductor element mounting package substrate 1 of the present invention is used as the bottom substrate 33 in PoP, or when the semiconductor package 36 of the present invention is used as the bottom package 35 in PoP, it is sealed above the connection terminal A14. Since the stopper 3 does not pop out, there is no need to use a solder ball diameter considering the height of the sealant 3 when connecting to the top substrate 32 or the top package 34, and the solder ball diameter is reduced. Is possible. Accordingly, the diameter (size) and pitch of the connection terminal A14 can be reduced.
  • the connecting terminal A14 connected to the top substrate 32 or the top package 34 has a larger solder ball 38 diameter (for example, ⁇ 0.6 mm). Therefore, the terminal diameter (size) is larger (for example, ⁇ 0.5 mm) and the pitch is larger (for example, 0.8 mm) than the connection terminal B15 on the opposite surface.
  • the connecting terminal A14 connected to the top substrate 32 or the top package 34 has a terminal diameter (size) that is larger than the connecting terminal B15 on the opposite surface. It can be formed small (for example, ⁇ 0.25 mm) and with a small pitch (for example, ⁇ 0.4 mm). Therefore, high-density connection with the top substrate 32 or the top package 34 having a larger number of terminals is possible.
  • connection terminal A14 connection terminal A14
  • the conductive resin 17 a material containing silver, copper, carbon or the like as a conductive component and a thermosetting resin such as an epoxy resin or a phenol resin as a binder can be used. Moreover, the conductive resin 17 after filling is cured. If the conductive resin 17 is not sufficiently cured, the crosslinking density of the conductive resin 17 is increased by subsequent heating, voids, cracks, and interface breakage occur due to volume shrinkage, and connection reliability decreases.
  • the binder of the conductive resin 17 is preferably not re-cured.
  • the rigidity of the bottomed via 13 as a whole is improved.
  • an elastomer material is used as the adhesive 8
  • the adhesive 8 absorbs the distortion and generates warping, twisting, and the like. Suppress.
  • the strain is absorbed, the stress of the strain concentrates on the adhesive 8 and is deformed. For this reason, for example, when the interlayer connection of the bottomed via 13 is formed only by general through-hole plating, it is conceivable that a crack occurs in the portion of the adhesive 8 and a connection failure occurs.
  • the portion where the interlayer connection 31 is formed by the conductive resin 17 is as follows. The deformation of the adhesive 8 is suppressed. Before filling the conductive resin 17, it is more desirable to form the metal coating 18 by plating in the bottomed via 13 in terms of filling property of the conductive resin 17 and interlayer connection reliability. In the portion where the interlayer connection 31 is not formed and the conductive resin 17 is not present, the adhesive 8 is deformed to absorb the distortion.
  • a package substrate for mounting a semiconductor device can be provided.
  • the conductive component is copper powder having an average particle size of 30 ⁇ m or less or a silver-plated copper powder surface (hereinafter referred to as “silver-plated copper powder”) or a gold-plated copper powder surface (hereinafter “gold-plated”). It is desirable to use metal powder containing “copper powder”. Among these, it is desirable that the main conductive component is silver-plated copper powder or gold-plated copper powder in terms of excellent depositability of electroless nickel plating or electroless gold plating. When the average particle size of the metal powder exceeds 30 ⁇ m, the screen is clogged during printing, the paste does not grow well, and the printability is poor.
  • silver plating in silver-plated copper powder and gold plating in gold-plated copper powder may be any of plating methods such as an electrolytic plating method, an electroless plating method, and a displacement plating method, and are not particularly limited.
  • the content of the conductive component in the conductive resin 17 is preferably 65% by mass to 80% by mass, and particularly preferably about 76% by mass. If the amount is less than this, the electroless plating deposition may be reduced, and the conductive resin 17 may not be covered with the metal film 16. If the amount is more than this, the viscosity of the conductive resin 17 in the paste state becomes high, The printability is lowered, and it becomes difficult to fill the bottomed via 13.
  • a catalyst is applied to the conductive resin 17 when the metal film 16 is formed on the conductive resin 17.
  • the metal film 16 can be directly formed by electroless plating or electroplating only by exposing the conductive component without performing the treatment.
  • the main conductive components are silver-plated copper powder and gold-plated copper powder. Desirable in terms. In this case, only by exposing the conductive component in the conductive resin 17, the electroless plating is directly deposited on the conductive component due to the plating catalyst activity of the conductive component contained in the conductive resin 17.
  • the entire conductive resin 17 is completely covered by electroless plating, and as a result, the metal film 16 is formed directly on the conductive resin 17.
  • the electroplating is directly deposited on the conductive component by supplying power from the conductive component only by exposing the conductive component in the conductive resin 17, the conductive resin 17 is formed by forming the electroplating to a predetermined thickness. The entire upper surface is completely covered by electroplating, and as a result, the metal film 16 is formed directly on the conductive resin 17.
  • physical polishing such as buffing is performed to smooth the surface on the entrance side of the bottomed via 13, and the conductive component in the conductive resin 17 is obtained by this physical polishing.
  • the desmear treatment is performed on the conductive resin 17, even the resin component holding the conductive component of the conductive resin 17 is etched, and as a result of the conductive component dropping off, the electroless plating is performed on the conductive resin 17.
  • the deposition property of electroplating is deteriorated and cannot be completely covered with the metal film 16 or that the metal film 16 on the conductive resin 17 is not easily adhered. Since the conductive component in the resin 17 is exposed, there is no such problem, so that the conductive resin 17 can be completely covered with the metal film 17 and the adhesion between the conductive resin 17 and the metal film 16 can be secured. .
  • the unevenness formed on the conductive resin 17 by physical polishing has an effect of improving the adhesion with the metal film 16 by the anchoring effect.
  • the conductive film 17 is electrically polished by physical polishing without performing any treatment for applying a catalyst or desmear treatment on the conductive resin 17.
  • the metal film 16 can be formed directly by electroless plating or electroplating simply by exposing the components. For this reason, a masking process for protection and a process for removing the catalyst are not required for parts other than the part for forming the metal film 16, and the part for forming the metal film 16 other than on the conductive resin 17.
  • both the conductive resin 17 and the portion where the other metal film 16 is to be formed can be simultaneously processed by batch processing. A metal film 16 can be formed. Therefore, the man-hour can be greatly reduced.
  • the electroless plating formed on the conductive resin 17 can be used as long as it deposits due to the plating catalyst activity of the conductive component contained in the conductive resin 17, but it has no depositing property.
  • Electrolytic nickel plating or electroless gold plating is desirable. When electroless nickel plating is performed and further displacement gold plating or electroless gold plating is performed, oxidation of the surface of the connection terminal A14 formed by the metal film 16 is suppressed, so that the contact resistance during connection is increased. It is desirable because it can suppress or maintain wettability.
  • electroless gold plating refers to so-called reduction-type electroless gold plating, which is distinguished from substitution-type gold plating.
  • the thickness of the electroless nickel plating is desirably 4 ⁇ m to 6 ⁇ m.
  • the thickness of the electroless nickel plating is smaller than this, the coating with the metal film 16 on the conductive resin 17 becomes insufficient, and the reliability may be lowered. If the thickness of the electroless nickel plating is thicker than this, it may lead to an increase in cost, and the plating stress may increase to reduce the adhesion of the metal film 16.
  • the hole filling resin does not have catalytic activity for electroless plating, it is necessary to apply a plating catalyst. Since it is necessary to mask an area where no plating is required so that the plating catalyst is not attached, there is a problem that man-hours increase.
  • the conductive resin 17 having catalytic activity for electroless plating is used, and the conductive component in the conductive resin 17 is exposed by physical polishing such as buff polishing. And adhesion can be secured. For this reason, there is no need to perform electroless nickel plating, displacement gold plating, electroless gold plating, etc. after performing electroless copper plating as the base plating as in the past as electroless plating.
  • a connection terminal ensuring solder wettability can be formed immediately above 13.
  • the electroplating formed on the conductive resin 17 can be used as long as it is deposited directly on the conductive component by supplying power using the conductivity of the conductive component contained in the conductive resin 17.
  • electro nickel plating, electro gold plating, and electro copper plating are desirable in terms of good precipitation.
  • the electro-nickel plating is performed directly on the conductive component of the conductive resin 17 as in the latter, it is not necessary to perform the electro-copper plating as the base plating of the electro-nickel plating as in the former, and the bottom is formed with a small number of man-hours.
  • a connection terminal ensuring solder wettability can be formed immediately above the via 13.
  • the thickness of the electro nickel plating is desirably 4 ⁇ m to 16 ⁇ m.
  • the thickness of the electro nickel plating is smaller than this, the coating with the metal film 16 on the conductive resin 17 becomes insufficient, and the reliability may be lowered. If the thickness of the electronickel plating is thicker than this, the cost will increase, and the plating stress may increase and the adhesion of the metal film 16 may decrease.
  • the thickness of electrogold plating is preferably 0.5 ⁇ m to 1.5 ⁇ m. If the thickness of the electrogold plating is thinner than this, the effect of suppressing the oxidation of the surface is lowered. On the other hand, if the thickness of the electrogold plating is thicker than this, the cost is increased.
  • connection terminal A14 is provided on the conductive resin 17, a connection terminal A14 is provided.
  • the connection terminal A14 is for electrically connecting to an external substrate.
  • the semiconductor element mounting package substrate 1 of the present invention is used as the bottom substrate 33 in PoP, or the semiconductor package 36 of the present invention is in PoP.
  • the bottom package 35 it is used as a connection terminal for connection to the top substrate 32 (other semiconductor element mounting package substrate 1) or the top package 34 (other package substrate).
  • polishing performed on the conductive resin 17 that protrudes upward from the bottomed via 13 after the conductive resin 17 is filled and cured for example, buffing, physical polishing using a belt sander, or the like can be used. Among these, mechanical polishing with buffalo is preferable, and the buff count is 600, 800, 1000, or a combination thereof.
  • baffle for example, JP buff monster V3 / V3-D2 (trade name, manufactured by Jablo Kogyo) for hole filling resin polishing can be used. Polishing is performed at a polishing current of about 0.1 A to 2.0 A, and the current value is also adjusted according to the amount of the conductive resin 17 to be cut. Preferably, it is about 1.0A to 1.4A.
  • the metal film 16 is formed on the conductive resin 17 filled in the bottomed via 13. For example, after filling the bottomed via 13 with the conductive resin 17, polishing is performed so that the surface of the conductive resin 17 is flush with the cavity material 7, and the copper foil 40 previously provided on the cavity material 7 is exposed (here, If the metal coating 18 is applied to the bottomed via 13 before the conductive resin 17 is filled, the metal coating 18 is exposed. Then, after forming a plating resist (not shown) on the exposed copper foil 40 (or the metal coating 18) and the conductive resin 17, a metal film 16 is formed by electroless plating or electroplating, and this is used as an etching resist.
  • a plating resist not shown
  • the copper foil 40 of an unnecessary location is removed and the connection terminal A14 is formed.
  • electroless plating electroless copper plating, electroless nickel plating, electroless gold plating, or the like can be used.
  • electroplating electrolytic copper plating, electrolytic nickel plating, electrogold plating, or the like can be used.
  • electroless plating in this case, electroless nickel plating or electroless gold plating is desirable in that the deposition on the conductive resin 17 is good without applying a catalyst.
  • electroplating electronickel plating or electrogold plating is desirable in terms of good precipitation on the conductive resin 17.
  • the metal film 16 can be selectively formed directly only on the conductive resin 17 and the land pattern, so that the conductor thickness of other portions on the cavity material 7 can be reduced, so that terminals with a fine pitch are formed. This makes it possible to increase the density.
  • the semiconductor element 2 is mounted in a region corresponding to the cavity portion 9 on the surface on the cavity layer 5 side.
  • the semiconductor element 2 is bonded onto the base layer 6 with a die bond film, for example, and is electrically connected to the semiconductor element 2 by the wire bond terminal 12 and the bonding wire 4.
  • the semiconductor element 2 can be mounted on the base layer 6 by using a connection terminal C27 (FIG. 6), or flip-chip connection or connection using a conductive adhesive.
  • the semiconductor element 2 is sealed with a sealant 3 in order to protect it from an environment such as moisture.
  • a sealant 3 epoxy resin, polyimide resin, silicon, urethane phenoz resin, polyester resin, acrylic resin, other thermosetting resin, thermoplastic resin, or the like can be used.
  • Example 1 [Cavity layer fabrication] As shown in FIG. 3, the cavity material 7 is MCL-E679F (manufactured by Hitachi Chemical Co., Ltd.), which is a 0.2 mm thick epoxy resin glass cloth copper clad laminate in which a copper foil having a thickness of 12 ⁇ m is laminated on both sides. , Product name). A guide hole (not shown) and a through-hole A24 were drilled by MARK-100 (trade name, manufactured by Hitachi Seiko Co., Ltd.), which is an NC drill machine.
  • MCL-E679F manufactured by Hitachi Chemical Co., Ltd.
  • a UV-curable etching resist dry film H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under conditions of 0.5 m / min, and then a negative mask is laminated thereon, exposed to ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed.
  • the portion without the etching resist on the foil 40 is sprayed and sprayed with a cupric chloride etchant composed of cupric chloride, hydrochloric acid and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa and speed 3.5 m / min. Further, a 3% by mass sodium hydroxide aqueous solution was sprayed to peel off and remove the etching resist to form a copper pattern. Thereby, the inner layer circuit 19 which becomes an annular ring was formed around the through hole A40 on one surface. On the other surface, that is, the surface on which the connection terminal A14 is formed, the copper foil 40 is left almost on the entire surface.
  • an adhesive sheet AS2600 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 25 ⁇ m and having a thickness of 25 ⁇ m is used as the adhesive 8, and the pressure is set to 0.4 MPa at a temperature of 90 ° C. with a laminator.
  • the cavity material 7 was temporarily attached by heating and pressurizing at a feed rate of 0.4 m / min.
  • an opening was formed in the adhesive sheet by a punching die in accordance with the through hole A24 provided in the cavity material 7.
  • an opening 25 having a size of 12 mm ⁇ 12 mm was formed using an NC router.
  • the desmear treatment of the through hole B39 is performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes, and electroless copper plating CUST201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), copper sulfate 10 g / L, EDTA 40 g / L, formalin 10 ml / L, pH 12.2) under conditions of a temperature of 24 ° C. and a time of 30 minutes, a base copper plating of 0.5 ⁇ m was performed on the entire surface of the base material a28 including the inside of the through hole B39. .
  • electroless copper plating CUST201 trade name, manufactured by Hitachi Chemical Co., Ltd.
  • an electrolytic copper plating 41 with a plating thickness of 20 ⁇ m is formed on the entire surface of the base material a28 including the inside of the through hole B39 under the conditions of copper sulfate plating at a temperature of 30 ° C., a current density of 1.5 A / dm 2 , and a time of 60 minutes. did.
  • an ultraviolet curable etching resist dry film H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under the condition of 5 m / min, and then a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed.
  • cupric chloride etching solution comprising a composition of cupric chloride, hydrochloric acid and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa, speed 3.5 m / min, and 3
  • the etching resist was peeled and removed by spraying a mass% sodium hydroxide aqueous solution to form circuits on the front and back of the base material a28.
  • GEA-679NUJY (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an epoxy resin glass cloth cloth prepreg having a thickness of 0.06 mm, was prepared.
  • 3EC-VLP-12 (trade name, manufactured by Mitsui Metal Mining Co., Ltd.), which is a copper foil having a thickness of 12 ⁇ m, was prepared as the copper foil 40.
  • These epoxy resin glass cloth cloth prepregs are superposed on the circuits on both sides of the base material a28 prepared in advance, and a copper foil 40 having a thickness of 12 ⁇ m is superposed thereon, and a pressure of 3 MPa is applied using a vacuum press.
  • the layers were integrated by pressurization under the conditions of a temperature of 175 ° C. and a holding time of 1.5 hours.
  • the base material 21 was produced by laminating and integrating the base material b29 and the copper foil 40 on one surface of the base material a28 and the base material c30 and the copper foil 40 on the other surface.
  • a UV-curable etching resist dry film H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under the condition of 5 m / min, and then a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed.
  • the copper part with no copper is spray-sprayed with a cupric chloride etching solution composed of cupric chloride, hydrochloric acid, and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa, speed 3.5 m / min, and further 3% by mass
  • a conformal mask 22 was formed by spraying an aqueous solution of sodium hydroxide to remove and remove the etching resist.
  • the base material 21 was processed using an NC laser processing machine MARK-20 (trade name, manufactured by Hitachi Seiko Co., Ltd.) under the conditions of an aperture diameter of 0.26, an output of 500 W, a pulse width of 15 ⁇ s, and a shot number of 15.
  • a laser hole 26 is formed, and then desmearing of the laser hole 26 is performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes, and CUST201 (product of Hitachi Chemical Co., Ltd., product) Name), copper sulfate 10 g / L, EDTA 40 g / L, formalin 10 ml / L, pH 12.2) at a temperature of 24 ° C. for 30 minutes, 0.5 ⁇ m on the entire surface of the base material 21 including the inside of the laser hole 26. Underlying copper plating was performed.
  • electrolytic copper having a plating thickness of 20 ⁇ m is formed on the entire surface of the base material b29 and the base material c30 including the inside of the laser hole 26 under conditions of copper sulfate plating at a temperature of 30 ° C., a current density of 1.5 A / dm 2 , and a time of 60 minutes. A plating was formed.
  • a dry film H-W475 (trade name, manufactured by Hitachi Chemical Co., Ltd.) for ultraviolet curable etching resist is applied to the surface of the base material 21 on the electrolytic copper plating with a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under the condition of 5 m / min, and then a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed.
  • a circuit is formed by spray spraying a copper part having no pressure with a cupric chloride etching solution comprising a composition of cupric chloride, hydrochloric acid, and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa and speed 3.5 m / min.
  • Etching resist was removed by spraying with a 3% by mass aqueous sodium hydroxide solution.
  • a circuit including the connection pad 11, the connection terminal B15, and the like was formed.
  • the connection terminal B15 had a diameter of 0.3 mm and a pitch of 0.5 mm.
  • PSR-4000 (trade name, manufactured by Taiyo Ink Mfg. Co., Ltd.), which is a liquid resist, is printed on the surface of the base material 21 on which the circuit has been formed, dried at 80 ° C. for 20 minutes, and then the negative type on the upper surface.
  • a mask is laminated, exposed with ultraviolet light, further developed with a 1.5% by mass aqueous sodium carbonate solution, further cured by irradiation with ultraviolet light 1 J / cm 2 , dried at 150 ° C. for 60 minutes, and then as photosensitive resin layer 10.
  • the solder resist 23 was formed, and the base layer 6 was produced.
  • the solder resist 23 (photosensitive resin layer 10) was formed only on the side of the base material 21 on which the connection pads 11 were formed, and not on the other side.
  • the desmear process in the bottomed via 13 is performed in the same manner as the base material 21, and the entire surface of the package substrate 1 for mounting semiconductor elements including the inside of the bottomed via 13 is zeroed.
  • the base copper plating of 5 ⁇ m was performed.
  • dry film H-W475 (trade name, manufactured by Hitachi Chemical Co., Ltd.) for UV curable etching resist is applied to the surface of the base copper plating with a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1.5 m / min. Then, a negative mask is attached to the upper surface and exposed with ultraviolet rays, and a plating resist 43 is formed on the portion that does not require plating (the surface having the connection terminal B15 of the cavity layer 9 and the base layer 6). did. The cavity portion 9 was completely covered with the plating resist 43 so as not to be electroplated with copper.
  • a metal coating 18 is formed by electrolytic copper plating 41 with a plating thickness of 20 ⁇ m under conditions of copper sulfate plating at a temperature of 30 ° C., a current density of 1.5 A / dm 2 , and a time of 60 minutes, and then 3% by mass of hydroxide
  • the plating resist 43 was removed by spraying with an aqueous sodium solution.
  • a base copper plating (not shown) deposited in the cavity portion 9 is applied at a temperature of 50 ° C. and a spray pressure. Etching was performed under the conditions of 0.2 MPa and a speed of 1.0 m / min, and then the catalyst was removed under the conditions of a sodium permanganate aqueous solution at a temperature of 85 ° C. for 15 minutes.
  • AE1244 (trade name, manufactured by Tatsuta Electric Co., Ltd.) is formed as the conductive resin 17 in the bottomed via 13 (hole diameter ⁇ : about 0.2 mm, depth: about 0.25 mm) of the package substrate 1 for mounting the semiconductor element. Filled by screen printing. For screen printing, a vacuum printing apparatus VE500 (trade name, manufactured by Toray Engineering Co., Ltd.) was used in order to eliminate bubbles remaining in the bottomed via 13. In order to completely cure the filled conductive resin 17, the entire semiconductor device mounting package substrate 1 was heated at 110 ° C. for 15 minutes, and further heated at 170 ° C. for 60 minutes. At this time, the conductive resin 17 protruded from the land pattern at the entrance of the bottomed via 13.
  • the surface of the electrolytic copper plating 41 at the entrance of the low via 13 was exposed and polished until the conductive resin 17 and the electrolytic copper plating 41 became smooth.
  • the number of bafrole used was a combination of 600, 800 and 1000.
  • JP buff monster V3 / V3-D2 (trade name, manufactured by Jablo Industries) for hole filling resin polishing was used.
  • the polishing current was 1.2A.
  • a dry film H-W475 (trade name, manufactured by Hitachi Chemical Co., Ltd.) for ultraviolet curable etching resist is applied to the surface of the electrolytic copper plating 41 with a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1.5 m / Then, a negative mask was attached to the upper surface and exposed with ultraviolet rays, and a plating resist 43 was formed on a portion that does not require plating. Note that the wire bond terminal 12 and the connection terminal B15 in the cavity portion 9 were not covered with the plating resist 43 in order to be plated.
  • the metal film 16 was formed by direct electroless plating without applying a catalyst or performing desmearing on the polished conductive resin 17 (the portions other than the conductive resin 17 are not shown). . Specifically, after degreasing, soft etching, and acid cleaning that are generally performed in the pretreatment of electroless plating, an electroless nickel plating solution NiPS100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is used. Then, immersion treatment was performed at a liquid temperature of 85 ° C. under conditions of 17 minutes, 21 minutes, and 25 minutes to deposit nickel plating of 4 ⁇ m, 5 ⁇ m, and 6 ⁇ m, respectively.
  • NiPS100 trade name, manufactured by Hitachi Chemical Co., Ltd.
  • substitution gold plating solution HGS-500 (Hitachi) HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced electroless gold plating solution that is immersed in a chemical temperature of 80 ° C. for 10 minutes at a liquid temperature.
  • gold plating was deposited to a thickness of 0.5 ⁇ m at a liquid temperature of 65 ° C. for 20 minutes.
  • a UV-curable etching resist dry film H-W475 (manufactured by Hitachi Chemical Co., Ltd., trade name) is temporarily bonded with a laminator under conditions of a pressure of 0.2 MPa, a temperature of 110 ° C., and a speed of 1.5 m / min. Then, a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, an etching resist is formed, and the copper portion without the etching resist is sprayed by spray spraying.
  • a circuit was formed with a cupric chloride etching solution having a composition of cupric, hydrochloric acid, and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa, speed 3.5 m / min, and then sprayed with a 3 mass% sodium hydroxide aqueous solution. Then, the etching resist was removed. Thereby, a circuit including the connection terminal A14 was formed.
  • the diameter of the connection terminal A14 of the cavity layer 5 is 0.25 mm and the pitch is 0.4 mm, which is smaller than the diameter of the connection terminal B15 of the base layer 6 of 0.3 mm and the pitch of 0.5 mm.
  • PSR-4000 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.), which is a liquid resist, is printed on both surfaces of the package substrate 1 for mounting semiconductor elements, dried at 80 ° C. for 20 minutes, and then a negative mask is formed on the upper surface.
  • a solder resist 23 Were exposed to ultraviolet light, developed with a 1.5% by weight aqueous sodium carbonate solution, further cured by irradiation with ultraviolet light 1 J / cm 2 , and dried at 150 ° C. for 60 minutes to form a solder resist 23.
  • the solder resist 23 has a height equivalent to that of the connection terminal A14 on the surface side (upper surface side) of the cavity layer 5, and a height equivalent to that of the connection terminal B15 on the surface side (lower surface side) of the base layer 6. Met.
  • the semiconductor element 2 is fixed in the cavity portion 9 of the semiconductor element mounting package substrate 1 using a die bonding film (not shown), and then the semiconductor element 2 is placed on the semiconductor element 2.
  • another semiconductor element 2 was fixed using a die bond film.
  • the upper and lower semiconductor elements 2 were connected to the wire bond terminals 12 of the semiconductor element mounting package substrate 1 by bonding wires 4.
  • the uppermost portion of the upper semiconductor element 2 including the bonding wires 4 had a height equal to or lower than the connection terminal A14 of the semiconductor element mounting package substrate 1.
  • the sealing agent 3 was filled in the cavity portion 9 and formed by transfer molding to produce a semiconductor package 36.
  • the uppermost part of the sealing agent 3 had a height equal to or lower than that of the connection terminal A14 of the semiconductor element mounting package substrate 1 (about to protrude about 0.1 mm above the connection terminal A14).
  • solder paste is printed on the connection terminal A14.
  • the semiconductor package 36 of the above embodiment is used as the bottom package 35.
  • the semiconductor is reflowed.
  • the packages were joined together.
  • the solder ball diameter for joining the semiconductor packages is set to 3. There is no need to consider the height. For this reason, it was possible to join the solder balls with a diameter of ⁇ 0.3 mm or less.
  • the uppermost portion of the sealant 3 of the bottom package 35 is in a state where the height is 1/3 or less of the solder ball ( ⁇ 0.3 mm) provided on the connection terminal A14 (that is, the inter-terminal distance of 44). It was possible to join the top package 34 with a height of 1/3 or less (0.1 mm or less).
  • Example 2 [Cavity layer fabrication] A cavity material was produced in the same manner as in Example 1.
  • Example 3 [Cavity layer fabrication] A cavity material was produced in the same manner as in Example 1.
  • connection terminal A14 provided on one surface of the package substrate 1 for mounting a semiconductor element
  • connection terminal B15 provided on the other surface
  • wire bond terminal 12 in the cavity portion 9 (in the case of having the connection terminal C27).
  • a nickel / gold plating layer for solder ball connection or wire bond connection was formed on the surface of the connection terminal C27). Except for this, a semiconductor element mounting package substrate and a semiconductor element mounting package were produced in the same manner as in Example 1.
  • Example 4 [Cavity layer fabrication] A cavity material was produced in the same manner as in Example 1.
  • Example 1 [Production of semiconductor device mounting package substrate and semiconductor device mounting package] Example 1 except that the conductive resin 17 is filled and cured in the bottomed via 13 and buffed, and the conductive resin 17 is further desmeared and then the metal film 16 is formed by electroless plating. It is the same.
  • the desmear treatment was performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes.
  • the resin component around the conductive component of the conductive resin 17 was attacked on the conductive resin 17 and the conductive component was dropped. Further, it was found that the adhesive 8 and the photosensitive resin layer 10 between the cavity layer 5 and the base layer 6 were attacked to be depressed or lost gloss.
  • electroless nickel plating was performed on the conductive resin 17 without subjecting it to a catalyst with a target thickness of 5 ⁇ m. As a result, spots where no precipitation occurred were observed, and the coating with the metal film 16 was not sufficient.
  • Example 1 [Production of semiconductor device mounting package substrate and semiconductor device mounting package] Example 1 except that the conductive resin 17 was filled and cured in the bottomed via 13 and buffed, and the conductive resin 17 was further desmeared and then the metal film 16 was formed by electro nickel plating. It is the same.
  • the desmear treatment was performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes.
  • the resin component around the conductive component of the conductive resin 17 was attacked on the conductive resin 17 and the conductive component was dropped. Further, it was found that the adhesive 8 and the photosensitive resin layer 10 between the cavity layer 5 and the base layer 6 were attacked to be depressed or lost gloss.
  • electro nickel plating was performed on the conductive resin 17 under the condition of a target thickness of 10 ⁇ m, portions where no precipitation occurred were observed, and the coating with the metal film 16 was not sufficient.
  • the filling property of the conductive resin 17 into the low and low vias 13 the determination of the electroless plating deposition property and the electroplating deposition property on the conductive resin 17, and the connection reliability test are as follows. Went to.
  • connection reliability test Using the conductive element mounting package substrate 1 produced in each example, reference example, and each comparative example, a thermal cycle test (15 minutes each) of ⁇ 55 to 125 ° C. was performed, and a bottomed via 13 was formed every 100 cycles. The connection resistance through the interlayer connection 31 was measured, and the presence or absence of connection failure after 1000 cycles was confirmed. A case where the connection resistance increased by 10% or more compared to the initial value was regarded as rejected (x).
  • Table 1 shows the results. In Examples 1, 2, 3, and 4, there was no damage to the package substrate 1 for mounting a semiconductor element, and both the plating deposition property and the connection reliability were good. In Reference Examples 1 and 2 in which the thickness of the nickel plating was reduced, the coating of the metal film 16 on the conductive resin 17 was not sufficient. In Comparative Examples 1 and 3 in which desmear was performed in addition to buffing, the conductive resin 17 was attacked, and the metal component 16 was not sufficiently covered by the removal of the conductive component or nickel plating. Further, damage was observed on the adhesive 8 and the photosensitive resin layer 10 of the substrate. In Comparative Examples 2 and 4 in which only desmear was performed without buffing, electroless plating did not deposit on the conductive resin 17 without catalyst treatment, and the connection reliability was NG.
  • SYMBOLS 1 Semiconductor device mounting package substrate, 2 ... Semiconductor device, 3 ... Sealant, 4 ... Bonding wire, 5 ... Cavity layer, 6 ... Base layer, 7 ... Cavity material, 8 ... Adhesive, 9 ... Cavity part, DESCRIPTION OF SYMBOLS 10 ... Photosensitive resin layer, 11 ... Connection pad, 12 ... Wire bond terminal, 13 ... Bottomed via, 14 ... Connection terminal A, 15 ... Connection terminal B, 16 ... Metal film, 17 ... Conductive resin, 18 ... Metal coating , 19 ... inner layer circuit, 20 ... inner layer connection, 21 ... base material, 22 ... conformal mask, 23 ... solder resist, 24 ...
  • connection terminal C 28 ... Base material a, 29 ... Base material b, 30 ... Base material c, 31 ... Interlayer connection, 32 ... Top substrate, 33 ... Bottom substrate, 34 ... Top package, 35 ... Bottom package, 36 ... Semiconductor package , 37 ... connection terminals, 38 ... solder balls, 39 ... through holes B, 40 ... copper foil, 41 ... plating, 42 ... interlayer connection, 43 ... plating resist, 44 ... distance between terminals

Abstract

A package substrate for mounting a semiconductor element, which has a high degree of freedom in combining packages and a small limitation in pattern design and makes it possible to connect together a top package and a bottom package at a high density in the case of constituting a PoP, and a method for manufacturing such package substrate are provided by simple processes at low cost.  The package substrate for mounting a semiconductor element is provided with a cavity layer having an opening and a through hole, a base layer laminated on the cavity layer, a cavity section formed by the opening, and a bottomed via hole formed by the through hole.  The package substrate for mounting a semiconductor element has a metal film which is formed by forming a metal film on the inner wall of the bottomed via hole, filling the bottomed via hole with a conductive resin by using the metal film as a base, arranging a conductive component contained in the conductive resin in an exposed state on the entering side of the bottomed via hole, and directly depositing plating on the exposed conductive component.  The method for manufacturing such package substrate is also provided.

Description

半導体素子搭載用パッケージ基板及びその製造方法Package board for mounting semiconductor device and manufacturing method thereof
　本発明は、高密度化が可能な半導体素子搭載用パッケージ基板及びその製造方法に関する。 The present invention relates to a package substrate for mounting a semiconductor element that can be densified and a method for manufacturing the same.
　電子部品の小型化や高密度化に伴い、システム化された半導体素子搭載用パッケージ基板が求められている。ＳｉＰ（Ｓｙｓｔｅｍ　ｉｎ　Ｐａｃｋａｇｅ）に代表されるＰｏＰ（Ｐａｃｋａｇｅ　ｏｎ　Ｐａｃｋａｇｅ）では、一つの半導体素子搭載用パッケージ基板に一つの半導体素子を実装する方法が一般的であった。近年、一つの半導体素子搭載用パッケージ基板に半導体素子を複数積み重ねたパッケージが主流となっている。 With the miniaturization and high density of electronic components, a systemized package board for mounting semiconductor elements is required. In PoP (Package on Package) typified by SiP (System in Package), a method of mounting one semiconductor element on one semiconductor element mounting package substrate has been common. In recent years, packages in which a plurality of semiconductor elements are stacked on one semiconductor element mounting package substrate have become mainstream.
　しかしながら、半導体パッケージでは、半導体素子の保護のためポッティングレジン等でコーティングする必要がある。そのため、一つの半導体素子搭載用パッケージ基板に半導体素子を複数積み重ねたパッケージでは、パッケージのトータル高さが厚くなり薄型化対応が困難であった。また、このトータル厚さが厚くなったパッケージ同士を積み重ねる際は、図７に示すように、接続端子Ａ１４より高く盛られた封止剤３が、ボトムパッケージ３５とトップパッケージ３４との接続を阻害するため、封止剤３の高さより径の大きいはんだボール３８（例えばφ０．６ｍｍ以上。なお、以下においてφは直径を表す。）を用いて、トップパッケージ３４とボトムパッケージ３５との間の接続を行う必要性がある。このようにしてパッケージ同士を接続した場合、接続に使用するはんだボール３８の径（即ち端子間距離４４）の半分以上の高さに、封止剤３が盛り上がった状態となるのが一般的であった。はんだボール３８の径が大きいと、このはんだボール３８を用いて接続する接続端子Ａ１４の径やピッチも、それに合わせて拡大せざるを得ない。このため、これらのパッケージ間の接続に用いるはんだボール３８の径が大きくなることで、接続端子Ａ１４のサイズやピッチを微細化することが困難であった。 However, the semiconductor package must be coated with a potting resin or the like to protect the semiconductor element. Therefore, in a package in which a plurality of semiconductor elements are stacked on one semiconductor element mounting package substrate, the total height of the package becomes thick and it is difficult to reduce the thickness. Further, when the packages having the increased total thickness are stacked, as shown in FIG. 7, the sealant 3 placed higher than the connection terminal A <b> 14 inhibits the connection between the bottom package 35 and the top package 34. Therefore, the connection between the top package 34 and the bottom package 35 is performed using a solder ball 38 having a diameter larger than the height of the sealant 3 (for example, φ0.6 mm or more. In the following, φ represents a diameter). There is a need to do. When the packages are connected in this way, the sealant 3 is generally raised to a height that is at least half the diameter of the solder ball 38 used for connection (ie, the inter-terminal distance 44). there were. If the diameter of the solder ball 38 is large, the diameter and pitch of the connection terminal A14 connected using the solder ball 38 must be increased accordingly. For this reason, it is difficult to reduce the size and pitch of the connection terminals A14 by increasing the diameter of the solder balls 38 used for connection between these packages.
　そこで、ＰｏＰ用の半導体素子搭載用パッケージ基板においては、上方となるトップパッケージ用の基板に設けたキャビティ部に、下方となるボトムパッケージの半導体素子の一部が収容されるようにしたもの（引用文献１）、ボトムパッケージ用の基板にキャビティ部を設け、複数積み重ねた半導体素子を収容するもの（引用文献２）が知られている。 Therefore, in the semiconductor substrate mounting package substrate for PoP, a part of the semiconductor device of the lower bottom package is accommodated in the cavity portion provided in the upper substrate for the top package (quote) Document 1), which has a cavity portion on a substrate for a bottom package and accommodates a plurality of stacked semiconductor elements (cited document 2) is known.
特開２００７－２２１１１８号公報JP 2007-221118 A 特開２００８－０１６８１９号公報JP 2008-016819 A
　しかしながら、引用文献１では、ボトムパッケージの上方側（トップパッケージ側）は封止剤が凸状態となっているため、組み合わせることができるトップパッケージが限られ、自由度が小さい問題がある。また、引用文献２では、キャビティ部を設けるために絶縁層が形成され、この絶縁層を通した外部接続端子との層間接続を、貫通孔に金属層を電気めっきで充填して行うため、電気めっきのためのめっきリードが必要となり、高密度化や設計上の制約がある。 However, in Cited Document 1, since the sealant is in a convex state on the upper side (top package side) of the bottom package, there is a problem that the top packages that can be combined are limited and the degree of freedom is small. Further, in Cited Document 2, an insulating layer is formed to provide a cavity portion, and an interlayer connection with an external connection terminal through the insulating layer is performed by filling a metal layer in a through hole with electroplating. Plating leads for plating are required, and there are restrictions on higher density and design.
　この問題を解決する方法として、図６に示すように、キャビティ部９を設けるための絶縁層（キャビティ層５）の層間接続３１を、導電樹脂１７を用いて行う方法が考えられる。 As a method for solving this problem, as shown in FIG. 6, a method in which the interlayer connection 31 of the insulating layer (cavity layer 5) for providing the cavity portion 9 is performed using the conductive resin 17 is conceivable.
　しかしながら、導電樹脂１７を用いた場合は、引用文献２のように、いわゆるフィルドビアめっきのような電気めっきで層間接続３１を形成した場合と違って、直上に接続端子Ａ１４を設けるためには、導電樹脂１７上にいわゆる蓋めっきを行う必要がある。この蓋めっきは、一般に、触媒を付与した後、下地となる無電解めっきを行い、さらに電気銅めっきを行って、ある程度厚付けすることで、接続信頼性を確保している。またさらに、接続端子Ａ１４のはんだ付けを確保するため、ニッケルめっきと金めっきを行っている。このように、蓋めっきは、工数がかかるため、コストアップやリードタイムの増加に繋がる問題があった。 However, when the conductive resin 17 is used, unlike the case where the interlayer connection 31 is formed by electroplating such as so-called filled via plating as in the cited document 2, in order to provide the connection terminal A14 directly above, It is necessary to perform so-called lid plating on the resin 17. In general, the lid plating ensures the connection reliability by applying a catalyst, followed by electroless plating as a base, further performing electrolytic copper plating, and thickening to some extent. Furthermore, nickel plating and gold plating are performed to ensure soldering of the connection terminal A14. Thus, since lid plating requires man-hours, there is a problem that leads to an increase in cost and lead time.
　本発明は、上記問題点に鑑みなされたものであり、ＰｏＰを構成する場合において、組み合わせるパッケージの自由度が大きく、パターン設計上の制約も小さく、トップパッケージとボトムパッケージ間の接続を高密度で行うことが可能な半導体素子搭載用パッケージ基板を簡易なプロセスで安価に提供することを目的とする。 The present invention has been made in view of the above problems, and in the case of configuring PoP, the degree of freedom of the package to be combined is large, the restrictions on the pattern design are small, and the connection between the top package and the bottom package is high density. An object of the present invention is to provide a package substrate for mounting a semiconductor element that can be performed at a low cost by a simple process.
　本発明は、以下のものに関する。 The present invention relates to the following.
（１）　開口及び貫通孔を有するキャビティ層と、このキャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板において、前記有底ビアの内壁に金属被覆が形成され、これを下地として前記有底ビアに導電樹脂が充填され、この導電樹脂中に含まれる導電成分が、露出した状態で前記有底ビアの入り口側に配置され、この露出した導電成分上に、めっきが直接析出することにより形成された金属皮膜を有する半導体素子搭載用パッケージ基板。 (1) A semiconductor device having a cavity layer having an opening and a through-hole, a base layer laminated on the cavity layer, a cavity portion formed by the opening, and a bottomed via formed by the through-hole. In the mounting package substrate, a metal coating is formed on the inner wall of the bottomed via, and the bottomed via is filled with a conductive resin as a base, and the conductive component contained in the conductive resin is exposed in the exposed state. A package substrate for mounting a semiconductor element, which is disposed on the entrance side of a bottomed via and has a metal film formed by depositing plating directly on the exposed conductive component.
（２）　上記（１）において、ベース層上のキャビティ層側に設けられる接続パッドと、前記キャビティ層上のベース層と反対側に設けられ、前記接続パッドと有底ビアによって層間接続される接続端子Ａとを接続する層間接続を有し、前記接続端子Ａが、前記有底ビアに充填された導電樹脂中に含まれる導電成分に、直接析出しためっきにより形成される金属皮膜を有する半導体素子搭載用パッケージ基板。 (2) In the above (1), a connection pad provided on the cavity layer side on the base layer and a connection provided on the opposite side of the base layer on the cavity layer and connected between the connection pads and the bottomed vias. A semiconductor element having an interlayer connection for connecting to a terminal A, wherein the connection terminal A has a metal film formed by direct deposition on a conductive component contained in a conductive resin filled in the bottomed via. Package substrate for mounting.
（３）　上記（１）または（２）において、金属皮膜を形成するめっきが、物理的研磨によって有底ビアの入り口側に露出した導電樹脂の導電成分上に、直接析出した半導体素子搭載用パッケージ基板。 (3) The package for mounting a semiconductor element according to the above (1) or (2), wherein the plating for forming the metal film is directly deposited on the conductive component of the conductive resin exposed on the entrance side of the bottomed via by physical polishing. substrate.
（４）　上記（１）から（３）の何れかにおいて、金属皮膜を形成するめっきが、無電解ニッケルめっきまたは無電解金めっきまたは無電解ニッケルめっきと置換金めっきもしくは無電解金めっきを有する半導体素子搭載用パッケージ基板。 (4) In any of the above (1) to (3), the plating for forming the metal film includes electroless nickel plating, electroless gold plating, electroless nickel plating and displacement gold plating or electroless gold plating Package substrate for device mounting.
（５）　上記（１）から（３）の何れかにおいて、金属皮膜を形成するめっきが、電気ニッケルめっきまたは電気金めっきまたは電気ニッケルめっきと置換金めっきもしくは無電解金めっきもしくは無電解金めっきもしくは電気金めっきを有する半導体素子搭載用パッケージ基板。 (5) In any one of the above (1) to (3), the plating for forming the metal film is an electro nickel plating, electro gold plating, electro nickel plating and displacement gold plating, electroless gold plating, electroless gold plating or A package substrate for mounting a semiconductor element having electroplating.
（６）　上記（１）から（５）の何れかにおいて、導電樹脂中に含まれる導電成分が、銀めっき銅粉または金めっき銅粉である半導体素子搭載用パッケージ基板。 (6) The package substrate for mounting a semiconductor element according to any one of (1) to (5) above, wherein the conductive component contained in the conductive resin is silver-plated copper powder or gold-plated copper powder.
（７）　開口及び貫通孔を有するキャビティ層と、このキャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板の製造方法において、前記有底ビアの内壁に金属被覆が形成され、これを下地として前記有底ビアに導電樹脂が充填される工程と、この導電樹脂表面を物理的に研磨して前記導電樹脂中の導電成分を露出させる工程と、この導電成分上に無電解めっきまたは電気めっきを直接析出させる工程と、を有する半導体素子搭載用パッケージ基板の製造方法。 (7) A semiconductor device having a cavity layer having an opening and a through-hole, a base layer laminated on the cavity layer, a cavity portion formed by the opening, and a bottomed via formed by the through-hole. In the mounting package substrate manufacturing method, a metal coating is formed on the inner wall of the bottomed via, and the bottomed via is filled with a conductive resin as a base, and the surface of the conductive resin is physically polished. And a step of exposing the conductive component in the conductive resin and a step of directly depositing electroless plating or electroplating on the conductive component.
　本発明によれば、ＰｏＰを構成する場合において、組み合わせるパッケージの自由度が大きく、パターン設計上の制約も小さく、トップパッケージとボトムパッケージ間の接続を高密度で行うことが可能な半導体素子搭載用パッケージ基板とその製造方法を簡易なプロセスで安価に提供することができる。 According to the present invention, when a PoP is configured, the degree of freedom of the package to be combined is large, the restrictions on the pattern design are small, and the connection between the top package and the bottom package can be performed with high density. The package substrate and the manufacturing method thereof can be provided at a low cost with a simple process.
本発明の実施例の半導体素子搭載用パッケージ基板及び半導体パッケージの断面図である。It is sectional drawing of the semiconductor device mounting package board | substrate and semiconductor package of the Example of this invention. 本発明の実施例の半導体素子搭載用パッケージ基板及び半導体パッケージの一部を拡大した断面図である。It is sectional drawing to which a semiconductor element mounting package board | substrate of the Example of this invention and a part of semiconductor package were expanded. 本発明の実施例のキャビティ層の製造工程を表すフロー図である。It is a flowchart showing the manufacturing process of the cavity layer of the Example of this invention. 本発明の実施例のベース層の製造工程を表すフロー図である。It is a flowchart showing the manufacturing process of the base layer of the Example of this invention. 本発明の実施例のキャビティ部を有する半導体搭載用パッケージ基板の製造工程を表すフロー図である。It is a flowchart showing the manufacturing process of the package substrate for semiconductor mounting which has a cavity part of the Example of this invention. 本発明の半導体素子搭載用パッケージ基板及び半導体パッケージを用いたＰｏＰの概略の断面図である。1 is a schematic cross-sectional view of a PoP using a semiconductor element mounting package substrate and a semiconductor package according to the present invention. 従来の半導体素子搭載用パッケージ基板及び半導体パッケージを用いたＰｏＰの概略の断面図である。It is general | schematic sectional drawing of PoP using the conventional semiconductor device mounting package board | substrate and a semiconductor package.
　本発明の半導体素子搭載用パッケージ基板１としては、図１、図２に示すように、開口２５を有するキャビティ層５と、このキャビティ層５に積層されたベース層６と、前記開口２５によって形成されたキャビティ部９を有する半導体素子搭載用パッケージ基板１であって、前記キャビティ層５を貫通して、前記ベース層６上の接続パッド１１と前記キャビティ層５上の接続端子Ａ１４とを接続する層間接続３１が設けられ、この層間接続３１が導電樹脂１７により形成される半導体素子搭載用パッケージ基板１が挙げられる。 As shown in FIGS. 1 and 2, the package substrate 1 for mounting a semiconductor element of the present invention is formed by a cavity layer 5 having an opening 25, a base layer 6 laminated on the cavity layer 5, and the opening 25. The semiconductor device mounting package substrate 1 having the cavity portion 9 is connected to the connection pad 11 on the base layer 6 and the connection terminal A14 on the cavity layer 5 through the cavity layer 5. The semiconductor device mounting package substrate 1 in which the interlayer connection 31 is provided and the interlayer connection 31 is formed of the conductive resin 17 is exemplified.
　また、本発明の半導体パッケージ基板１を用いて作製した半導体パッケージ３６としては、図１、図２に示すように、キャビティ部９を有する半導体素子搭載用パッケージ基板１と、前記キャビティ部９内に搭載された半導体素子２と、この半導体素子２を封止する封止剤３と、前記半導体素子搭載用パッケージ基板１の一方の面に形成された接続端子Ａ１４と、他方の面に形成された接続端子Ｂ１５を有する半導体パッケージ３６であって、前記キャビティ部９が、開口２５を有するキャビティ層５と、このキャビティ層５に積層されたベース層６とによって形成され、前記キャビティ層５に前記ベース層６上の接続パッド１１と前記キャビティ層５上の接続端子Ａ１４とを接続する層間接続３１が設けられ、この層間接続３１が導電樹脂１７により形成される半導体パッケージ３６が挙げられる。 Further, as shown in FIGS. 1 and 2, the semiconductor package 36 manufactured using the semiconductor package substrate 1 of the present invention includes the semiconductor element mounting package substrate 1 having the cavity portion 9 and the cavity portion 9. The mounted semiconductor element 2, the sealing agent 3 for sealing the semiconductor element 2, the connection terminal A14 formed on one surface of the semiconductor element mounting package substrate 1, and the other surface formed A semiconductor package having a connection terminal B15, wherein the cavity portion 9 is formed by a cavity layer 5 having an opening 25 and a base layer 6 laminated on the cavity layer 5, and the base layer 6 is formed on the cavity layer 5. An interlayer connection 31 for connecting the connection pad 11 on the layer 6 and the connection terminal A14 on the cavity layer 5 is provided. The semiconductor package 36 formed by 17 and the like.
　このように、本発明の半導体素子搭載用パッケージ基板１及び半導体パッケージ３６では、導電樹脂１７により、キャビティ層５の層間接続３１を形成するため、いわゆるフィルドビアめっきによって層間接続３１を形成する場合と異なって、給電のためのめっきリードを設ける必要がないため、設計の自由度が大きく、またその分高密度化を図ることができる。また、フィルドビアめっきに比べて、よりアスペクト比が大きい場合（例えば、層間接続３１のための有底ビア１３の径がφ０．２ｍｍ、深さ０．２ｍｍ～０．５５ｍｍ）でも、接続パッド１１と接続端子Ａ１４との層間接続３１を形成できるので、キャビティ層５の厚みを、従来よりも厚く（例えば０．２ｍｍ～０．５５ｍｍ程度）することができる。その結果、キャビティ部９を高く形成することができ、図１に示すように、複数の半導体パッケージ３６を重ねてキャビティ部９内に収納することが容易になる。また、キャビティ部９の高さを、封止剤３がほとんど飛び出さない高さに形成できるため、封止剤３をモールドして半導体パッケージ３６を形成した場合でも、封止剤３の表面が、接続端子Ａ１４と同等以下、即ち接続端子Ａ１４からほとんど出っ張らない程度に平坦とすることができる。例えば、図６に示すように、キャビティ部９内に半導体素子２を上下２段に積み重ねて搭載した場合でも、封止剤３の表面が、接続端子Ａ１４よりもほとんど出っ張らない程度に平坦なので、半導体パッケージ同士の接合のためのはんだボール径は、封止剤３の高さを考慮する必要がなく、はんだボールとして、径がφ０．３ｍｍ以下の微小なものを用いても接合が可能となる。そして、φ０．３ｍｍのはんだボールを用いた場合でも、ボトムパッケージ３５の封止剤３の最上部が、接続端子Ａ１４上のはんだボール（φ０．３ｍｍ）の１／３以下の高さとなる状態で、トップパッケージ３４と接合することが可能である。即ち、封止剤３の最上部が、接続端子Ａ１４よりも、端子間距離４４の１／３以下（０．１ｍｍ以下）の高さだけ出っ張るようにすることができる。したがって、本発明の半導体素子搭載用パッケージ基板１及び半導体パッケージ３６を、ボトム基板３３やボトムパッケージ３５として用いてＰｏＰを構成する場合、組み合わせる相手の半導体パッケージは一般的なものを選択でき、自由度が大きい。また、接続のためのはんだボールの径は、封止剤３の飛び出しを考慮して大きくする必要がないため、接続端子Ａ１４の径やピッチを小さく（例えば、端子径がφ０．２５ｍｍ以下、ピッチが０．４ｍｍ以下。）することができ、高密度な接続が可能となる。 As described above, in the semiconductor element mounting package substrate 1 and the semiconductor package 36 of the present invention, the interlayer connection 31 of the cavity layer 5 is formed by the conductive resin 17, so that the interlayer connection 31 is formed by so-called filled via plating. Therefore, there is no need to provide a plating lead for power supply, so that the degree of freedom in design is large and the density can be increased accordingly. Even when the aspect ratio is larger than that of filled via plating (for example, the diameter of the bottomed via 13 for the interlayer connection 31 is φ0.2 mm, the depth is 0.2 mm to 0.55 mm), Since the interlayer connection 31 with the connection terminal A14 can be formed, the thickness of the cavity layer 5 can be made thicker (for example, about 0.2 mm to 0.55 mm). As a result, the cavity 9 can be formed high, and it becomes easy to stack a plurality of semiconductor packages 36 in the cavity 9 as shown in FIG. Further, since the height of the cavity portion 9 can be formed such that the sealant 3 hardly protrudes, even when the semiconductor package 36 is formed by molding the sealant 3, the surface of the sealant 3 is It can be made flat so that it is not more than the same as the connection terminal A14, that is, hardly protrudes from the connection terminal A14. For example, as shown in FIG. 6, even when the semiconductor element 2 is stacked and mounted in the upper and lower two stages in the cavity portion 9, the surface of the sealing agent 3 is flat so that it hardly protrudes than the connection terminal A14. The solder ball diameter for joining the semiconductor packages does not need to consider the height of the sealant 3 and can be joined even if a solder ball having a diameter of φ0.3 mm or less is used. . Even when a solder ball having a diameter of 0.3 mm is used, the uppermost portion of the sealant 3 of the bottom package 35 is in a state where the height is 1/3 or less of the solder ball (φ0.3 mm) on the connection terminal A14. The top package 34 can be joined. In other words, the uppermost portion of the sealant 3 can protrude by a height of 1/3 or less (0.1 mm or less) of the inter-terminal distance 44 from the connection terminal A14. Therefore, when the PoP is configured by using the semiconductor element mounting package substrate 1 and the semiconductor package 36 of the present invention as the bottom substrate 33 or the bottom package 35, a general semiconductor package to be combined can be selected, and the degree of freedom can be selected. Is big. Further, since it is not necessary to increase the diameter of the solder ball for connection in consideration of the pop-out of the sealant 3, the diameter and pitch of the connection terminal A14 are reduced (for example, the terminal diameter is φ0.25 mm or less, the pitch 0.4 mm or less), and high-density connection is possible.
　キャビティ層５の層間接続３１は、ベース層６のキャビティ層５側の面に設けられた接続パッド１１と、この接続パッド１１を底面として前記キャビティ層５に形成された有底ビア１３と、この有底ビア１３内に充填された導電樹脂１７と、この導電樹脂１７上に設けられた接続端子Ａ１４により形成することができる。このように、導電樹脂１７を充填し、その上に接続端子Ａ１４を設けることにより、層間接続３１の直上に接続端子Ａ１４を形成することができるため、接続端子Ａ１４を高密度に配置することができる。このキャビティ層５上の接続端子Ａ１４は、他の半導体素子搭載用パッケージ基板１や半導体パッケージ３６、配線板（図示しない。）との接続に用いるいわゆる外部接続端子として用いられる。このため、図６に示すように、本発明をＰｏＰのボトム基板３３やボトムパッケージ３５として使用した場合、トップ基板３２やトップパッケージ３４との間の接続を高密度で行うことが可能となる。また、ベース層６のキャビティ層５側の面に設けられた接続パッド１１は、半導体素子２との接続を行うワイヤボンド端子１２や接続端子Ｃ２７等のいわゆる内部接続端子や、ベース層６のキャビティ層５側とは反対側の面に設けられた接続端子Ｂ１５に接続される。接続端子Ｂ１５は、接続端子Ａ１４と同様に、他の半導体素子搭載用パッケージ基板１や半導体パッケージ３６、配線板（図示しない。）との接続に用いるいわゆる外部接続端子として用いられる。 The interlayer connection 31 of the cavity layer 5 includes a connection pad 11 provided on the surface of the base layer 6 on the cavity layer 5 side, a bottomed via 13 formed in the cavity layer 5 with the connection pad 11 as a bottom surface, The conductive resin 17 filled in the bottomed via 13 and the connection terminal A14 provided on the conductive resin 17 can be used. In this way, by filling the conductive resin 17 and providing the connection terminal A14 thereon, the connection terminal A14 can be formed immediately above the interlayer connection 31, so that the connection terminals A14 can be arranged at high density. it can. The connection terminal A14 on the cavity layer 5 is used as a so-called external connection terminal used for connection to another semiconductor element mounting package substrate 1, the semiconductor package 36, and a wiring board (not shown). Therefore, as shown in FIG. 6, when the present invention is used as the PoP bottom substrate 33 or the bottom package 35, the connection between the top substrate 32 and the top package 34 can be performed with high density. Further, the connection pad 11 provided on the surface of the base layer 6 on the cavity layer 5 side is a so-called internal connection terminal such as a wire bond terminal 12 or a connection terminal C27 for connecting to the semiconductor element 2, or a cavity of the base layer 6. It is connected to a connection terminal B15 provided on the surface opposite to the layer 5 side. Similarly to the connection terminal A14, the connection terminal B15 is used as a so-called external connection terminal used for connection to another semiconductor element mounting package substrate 1, the semiconductor package 36, and a wiring board (not shown).
　図２に示すように、キャビティ層５の層間接続３１は、キャビティ層５の有底ビア１３の内壁に金属被覆１８を形成するのが望ましい。つまり、有底ビア１３内に充填する導電樹脂１７の下地として、有底ビア１３の内壁に金属被覆１８を形成するのが望ましい。有底ビア１３の内壁に金属被覆１８を形成する方法としては、例えば、電気銅めっきや無電解銅めっきにより形成することができる。これにより、有低ビア１３の内壁が滑らかになり、導電樹脂１７が有底ビア１３内に入り易くなるため、導電樹脂１７が充填し易くなる。また、めっきによる金属被覆１８と導電樹脂１７の両者で層間接続３１を形成するため、層間接続の信頼性が向上する。 As shown in FIG. 2, the interlayer connection 31 of the cavity layer 5 desirably forms a metal coating 18 on the inner wall of the bottomed via 13 of the cavity layer 5. That is, it is desirable to form the metal coating 18 on the inner wall of the bottomed via 13 as the base of the conductive resin 17 filled in the bottomed via 13. As a method of forming the metal coating 18 on the inner wall of the bottomed via 13, for example, it can be formed by electrolytic copper plating or electroless copper plating. As a result, the inner wall of the low and low via 13 becomes smooth and the conductive resin 17 easily enters the bottomed via 13, so that the conductive resin 17 is easily filled. Moreover, since the interlayer connection 31 is formed by both the metal coating 18 and the conductive resin 17 by plating, the reliability of the interlayer connection is improved.
　図６に示すように、ベース層６のキャビティ層５と反対側の面に接続端子Ｂ１５が設けられ、接続端子Ａ１４は接続端子Ｂ１５よりもサイズ及びピッチが小さくなるように形成することができる。これにより、接続端子Ａ１４を、他の半導体素子搭載用パッケージ基板１や半導体パッケージ３６と接続する際、高密度な接続が可能となる。つまり、ＰｏＰのボトム基板３３やボトムパッケージ３５として使用する場合、トップ基板３２やトップパッケージ３４との高密度接続が可能となる。 As shown in FIG. 6, a connection terminal B15 is provided on the surface of the base layer 6 opposite to the cavity layer 5, and the connection terminal A14 can be formed to be smaller in size and pitch than the connection terminal B15. As a result, when the connection terminal A14 is connected to another semiconductor element mounting package substrate 1 or the semiconductor package 36, high-density connection is possible. That is, when used as the PoP bottom substrate 33 or the bottom package 35, high-density connection with the top substrate 32 or the top package 34 is possible.
　封止剤３の最上部は、半導体素子搭載用パッケージ基板１の接続端子Ａ１４と同等以下の高さに形成するのが望ましい。ここで、接続端子Ａ１４と同等以下の高さとは、接続端子Ａ１４上に設けられるはんだボール３８がφ０．３ｍｍの場合（即ち、端子間距離４４が０．３ｍｍの場合）を想定しており、その径の１／３以下の高さまでをいう。つまり、封止剤３の最上部の高さが、接続端子Ａ１４から０．１ｍｍの高さまでであることをいう。これにより、本発明の半導体素子搭載用パッケージ基板１及び半導体パッケージ３６を、ボトム基板３３やボトムパッケージ３５として用いてＰｏＰを構成する場合、接続端子Ａ１４の面が平坦なので、組み合わせるトップ基板３２やトップパッケージ３４の接続端子３７面は、フラットな一般的なものを選択でき、自由度が大きい。また、接続のためのはんだボール３８の径は、封止剤３の飛び出しを考慮して大きくする必要がないため、高密度な接続が可能となる。 The uppermost part of the sealant 3 is desirably formed at a height equal to or lower than the connection terminal A14 of the package substrate 1 for mounting semiconductor elements. Here, the height equal to or less than that of the connection terminal A14 is assumed when the solder ball 38 provided on the connection terminal A14 has a diameter of 0.3 mm (that is, when the distance 44 between the terminals is 0.3 mm). Up to 1/3 or less of the diameter. That is, the height of the uppermost part of the sealing agent 3 is from the connection terminal A14 to a height of 0.1 mm. Accordingly, when the PoP is configured by using the semiconductor element mounting package substrate 1 and the semiconductor package 36 of the present invention as the bottom substrate 33 or the bottom package 35, the surface of the connection terminal A14 is flat. As the connection terminal 37 surface of the package 34, a flat general one can be selected, and the degree of freedom is large. Further, since the diameter of the solder ball 38 for connection does not need to be increased in consideration of the pop-out of the sealing agent 3, high-density connection is possible.
　キャビティ部９は、半導体素子搭載用パッケージ基板１に設けられた所定の深さの窪みであり、半導体素子２を搭載するためのスペースとして使用される。また、キャビティ部９は、開口２５を有するキャビティ層５とベース層６により形成される。キャビティ部９を形成する方法として、一例としては、図３、図５に示すように、接着剤８を張り合わせたキャビティ層５に、ルータ加工やパンチ加工等で開口２５を形成した後、この開口２５をベース層６で塞ぐように、ベース層６を積層する方法がある。また、他の例としては、キャビティ層５とベース層６とを積層した後で、キャビティ部９に対応する部分のキャビティ層５を除去する方法がある。この場合は、キャビティ層５として感光性の材料を使用することができる。 The cavity portion 9 is a recess having a predetermined depth provided in the semiconductor element mounting package substrate 1 and is used as a space for mounting the semiconductor element 2. The cavity portion 9 is formed by the cavity layer 5 having the opening 25 and the base layer 6. As an example of a method for forming the cavity portion 9, as shown in FIGS. 3 and 5, an opening 25 is formed in the cavity layer 5 bonded with the adhesive 8 by router processing, punching, or the like. There is a method of laminating the base layer 6 so that 25 is covered with the base layer 6. As another example, there is a method in which the cavity layer 5 corresponding to the cavity portion 9 is removed after the cavity layer 5 and the base layer 6 are laminated. In this case, a photosensitive material can be used as the cavity layer 5.
　キャビティ層５は、ベース層６と積層されて半導体素子２を収納するキャビティ部９を形成する基板であるとともに、半導体素子２が搭載されるベース層６の接続パッド１１と、他の半導体素子搭載用パッケージ用基板と接続される接続端子Ａ１４との電気的接続を行う基板である。キャビティ層５は、絶縁層を有するキャビティ材７と、その表面に形成される接続端子Ａ１４及び内層回路１９と、キャビティ材７上に設けられる接着剤８と、キャビティ部９形成のための開口２５と、層間接続３１のための貫通孔Ａ２４とを有する。キャビティ層５の接着剤８を設ける側に内層回路１９を設けることにより、ベース層６の接続パッド１１と金属被覆１８との接続箇所に近い位置に、貫通孔Ａ２４内の金属被覆１８との内層接続２０を形成することができ、この場合は、熱サイクル試験における寿命が改善され、信頼性を向上することができる。内層回路１９は、貫通孔Ａ２４の周囲を完全に取り囲んでいるいわゆるアニュラリングとするのが、信頼性の点でより望ましい。また、キャビティ層５とベース層６とを接着剤８を挟んで加熱・加圧して積層接着する際に、接着剤８が流動しても、貫通孔Ａ２４の周囲を完全に取り囲んだダムとして作用するので、貫通孔Ａ内に流動した接着剤８が入り込んで、信頼性が低下するのを抑制することができる。また、例えば、接着剤８としてエラストマー材を使用する場合、キャビティ材７に使用するガラスエポキシ等の絶縁材に比べて、一般に熱膨張係数が大きい。このため、有底ビア１３の内壁のなかで接着剤８が内壁となる部分では、スルーホールめっきである金属被覆１８が、バレルクラックを生じることや、有底ビア１３の底部では、スルーホールめっき剥がれを生じることが懸念される。しかしながら、図２の拡大図からわかるように、内層回路１９が厚みを有するため、内層回路１９に対応する部分の接着剤８は、それ以外の部分に比べて、厚みが薄く形成される。つまり、キャビティ材７上の内層回路１９とベース層６の感光性樹脂１０との間に挟まれる部分の接着剤の厚みは、これらに挟まれていない部分に比べて薄くなる。このように、有底ビア１３の周囲では、接着剤８の厚みを小さくすることができるので、接着剤８の熱膨張係数が大きいことによる影響を小さくすることができ、信頼性を確保することが可能になる。このような作用を生じるためには、接着剤の厚みが１０μｍ～５０μｍで内層回路の厚みが９μｍ～１８μｍの場合、内層回路１９に対応する部分（内層回路１９と感光性樹脂層１０に挟まれた部分）の接着剤８の厚みは、０．５μｍ～７μｍであるのが望ましい。したがって、内層回路１９が、貫通孔Ａ２４の周囲を完全に取り囲んでいるいわゆるアニュラリングとすることにより、熱膨張係数が比較的大きいエラストマー材を接着剤８として用いる場合でも、有底ビア１３の接続信頼性を確保することが可能になる。内層回路１９の厚みは、９～１８μｍであるのが望ましい。これにより、めっきで形成される金属被覆１８との接続面積をかせぐことができ、また、貫通孔Ａ２４の周囲を完全に取り囲んだダムとしての効果も大きくなるので、接続信頼性が向上する。図３に示すように、キャビティ材７は、半導体素子搭載用パッケージ基板１の製造に用いられる一般的な銅張り積層板やビルドアップ材、フィルム材を用いることができる。また、これらの銅張り積層板やビルドアップ材、フィルム材を組み合わせて多層化したものも使用できる。キャビティ材７の厚みは、キャビティ部９に収納する半導体素子２を積み重ねる高さに応じて選択される。接続端子Ａ１４や内層回路１９を形成するパターンは、サブトラクト法等により作製することができる。開口２５や貫通孔Ａ２４は、ルータ加工やパンチ加工等で形成することができる。 The cavity layer 5 is a substrate that is laminated with the base layer 6 to form the cavity portion 9 that accommodates the semiconductor element 2, the connection pad 11 of the base layer 6 on which the semiconductor element 2 is mounted, and other semiconductor element mounting It is a board | substrate which performs electrical connection with connection terminal A14 connected with the board | substrate for package. The cavity layer 5 includes a cavity material 7 having an insulating layer, connection terminals A14 and an inner layer circuit 19 formed on the surface thereof, an adhesive 8 provided on the cavity material 7, and an opening 25 for forming the cavity portion 9. And a through hole A24 for the interlayer connection 31. By providing the inner layer circuit 19 on the side of the cavity layer 5 where the adhesive 8 is provided, the inner layer of the metal coating 18 in the through hole A24 is located at a position close to the connection point between the connection pad 11 and the metal coating 18 of the base layer 6. The connection 20 can be formed, and in this case, the lifetime in the thermal cycle test can be improved and the reliability can be improved. The inner layer circuit 19 is more preferably a so-called annular ring that completely surrounds the through hole A24 in terms of reliability. Further, when the cavity layer 5 and the base layer 6 are laminated and bonded by heating and pressing with the adhesive 8 interposed therebetween, even if the adhesive 8 flows, it acts as a dam that completely surrounds the through hole A24. Therefore, it can suppress that the adhesive agent 8 which flowed in the through-hole A enters, and reliability falls. For example, when an elastomer material is used as the adhesive 8, the coefficient of thermal expansion is generally larger than that of an insulating material such as glass epoxy used for the cavity material 7. For this reason, in the part where the adhesive 8 becomes the inner wall in the inner wall of the bottomed via 13, the metal coating 18, which is through-hole plating, causes barrel cracks, or in the bottom of the bottomed via 13, the through-hole plating is performed. There is a concern that peeling may occur. However, as can be seen from the enlarged view of FIG. 2, since the inner layer circuit 19 has a thickness, the adhesive 8 in a portion corresponding to the inner layer circuit 19 is formed thinner than the other portions. That is, the thickness of the adhesive in the portion sandwiched between the inner layer circuit 19 on the cavity material 7 and the photosensitive resin 10 in the base layer 6 is thinner than the portion not sandwiched between them. As described above, since the thickness of the adhesive 8 can be reduced around the bottomed via 13, the influence due to the large thermal expansion coefficient of the adhesive 8 can be reduced, and reliability can be ensured. Is possible. In order to produce such an effect, when the thickness of the adhesive is 10 μm to 50 μm and the thickness of the inner layer circuit is 9 μm to 18 μm, the portion corresponding to the inner layer circuit 19 (between the inner layer circuit 19 and the photosensitive resin layer 10). The thickness of the adhesive 8 in the (part) is preferably 0.5 μm to 7 μm. Therefore, even when an elastomer material having a relatively large thermal expansion coefficient is used as the adhesive 8, the inner layer circuit 19 is a so-called annular ring that completely surrounds the periphery of the through hole A24. Reliability can be ensured. The thickness of the inner layer circuit 19 is preferably 9 to 18 μm. As a result, the area of connection with the metal coating 18 formed by plating can be increased, and the effect as a dam that completely surrounds the periphery of the through hole A24 is increased, so that connection reliability is improved. As shown in FIG. 3, the cavity material 7 can be a general copper-clad laminate, a build-up material, or a film material used for manufacturing the semiconductor device mounting package substrate 1. Moreover, what was multilayered by combining these copper-clad laminates, build-up materials, and film materials can also be used. The thickness of the cavity material 7 is selected according to the height at which the semiconductor elements 2 housed in the cavity portion 9 are stacked. The pattern for forming the connection terminal A14 and the inner layer circuit 19 can be produced by a subtract method or the like. The opening 25 and the through hole A24 can be formed by router processing, punching, or the like.
　キャビティ層５とベース層６の積層に用いる接着剤８は、半導体素子搭載用パッケージ基板１の製造に用いられるエポキシやポリイミド系の多層化接着用の接着剤８を用いることができ、プレスやラミネート等によりキャビティ層５やベース層６に仮付けすることができるのが望ましい。接着剤８は、キャビティ層５とベース層６の何れかに仮付けしてもよいし、予め仮付けはせずに、キャビティ層５とベース層６を積層して接着する際に、両者の間に挟みこんで使用してもよい。このような接着剤８として、例えば、強化繊維に熱硬化性樹脂を含浸し、加熱・乾燥して、半硬化状にしたプリプレグや、ポリエチレンテレフタレートフィルム上に熱硬化性樹脂を塗布し、加熱・乾燥してドライフィルム状にした接着シートを使用することができる。熱硬化樹脂としては、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ビスマレイミド樹脂等が使用でき、強化繊維としては、ガラス布、ガラス紙、アミド布、アミド紙が使用できる。 The adhesive 8 used for laminating the cavity layer 5 and the base layer 6 can be an epoxy or polyimide based adhesive 8 used for manufacturing the package substrate 1 for mounting a semiconductor element, and can be a press or laminate. It is desirable that it can be temporarily attached to the cavity layer 5 or the base layer 6 by, for example. The adhesive 8 may be temporarily attached to either the cavity layer 5 or the base layer 6, or when the cavity layer 5 and the base layer 6 are laminated and bonded without preliminarily attaching, It may be used by being sandwiched between them. As such an adhesive 8, for example, a thermosetting resin is impregnated into a reinforcing fiber, heated and dried, and applied to a semi-cured prepreg or a polyethylene terephthalate film. An adhesive sheet that has been dried to form a dry film can be used. As the thermosetting resin, epoxy resin, phenol resin, polyimide resin, bismaleimide resin or the like can be used, and as the reinforcing fiber, glass cloth, glass paper, amide cloth or amide paper can be used.
　また、接着剤８は、エラストマー材であるのが好ましい。エラストマー材として使用する接着剤８としては、十分な接着強度を有し、かつキャビティ層５とベース層６の寸法変化の挙動の差によって生じる歪みを吸収することができるものであれば使用することができる。例えば、エポキシ樹脂及び硬化剤成分１００質量部に対し、ゴム変成のエポキシ樹脂２０質量部～５０質量部、分子量が１万以上のエポキシ骨格の高分子成分１０質量部～４０質量部、分子量５万以上のゴム成分５０質量部～１５０質量部、硬化促進剤０．３質量部～２．５質量部からなる接着剤組成物を、基材フィルムに塗布し、半硬化状態に熱処理してなる熱硬化性接着シートを、基材フィルムから剥がして、真空プレス等で加熱・加圧することで形成できる。接着剤８は、キャビティ層５やベース層６にラミネータ等で仮接着可能なものが、作業性の点から望ましい。加熱・加圧後の接着剤８の弾性率は、５０℃で１００ＭＰａ～５００ＭＰａのものを使用でき、特には５００Ｍｐａ程度が望ましい。なお、弾性率は、株式会社ユービーエム製、Ｒｈｅｏｇｅｌ　Ｅ－４０００型粘弾性測定装置を用い、ＤＶＥ法にて、引張モード、周波数１０Ｈｚ、昇温速度５℃／分の条件で測定した。樹脂フロー量（加熱・加圧後の端部からの樹脂流れ量）は、５０μｍ～１５００μｍのものを使用でき、成形性と有底ビア内への染み出し量のバランスから１００μｍ～５００μｍが望ましく、特には３００μｍ程度のものが望ましい。なお、樹脂フロー量は、加熱・加圧前のシート状態の接着剤８を直径１０ｍｍの円形に打抜いたものをサンプルとして、これをＰＥＴ（ポリエチレンテレフタレート）フィルムで挟み込み、プレス（１００℃、３Ｍｐａ、５分）を行なった後、サンプルの直径を３箇所測定して平均し、プレス前の寸法との差を計算により求めることで測定した。ゴム変成のエポキシ樹脂としては、ＣＴＢＮ（カルボキシ基末端ブタジエンニトリルゴム）変成品であり、かつ変成率が３０％～６０％のものが挙げられる。ゴム成分としては、分子量５万以上のエポキシ基含有アクリルニトリルブタジエンゴムが挙げられる。半硬化状態は、基材フィルムに塗布した後の熱処理により、１０％～６０％の硬化率とすることにより得ることができる。このようなエラストマーとしての作用を有する接着剤８を使用することにより、エラストマー材としての接着剤８が、キャビティ層５とベース層６の寸法変化の挙動の差によって生じる歪みを吸収するので、半導体素子搭載用パッケージ基板１の反りを抑制することができる。特に、キャビティ層５とベース層６に使用される材料や層構成が異なったり、キャビティ部９用の開口２５を有するために開口率が異なる場合は、製造時や使用時のキャビティ層５とベース層６の寸法変化の挙動が異なるため、積層に用いる接着剤８としてエラストマー材を使用するのが有効である。このような接着剤８としては、例えば、ＡＳ２６００、ＡＳ３０００、ＧＦ３５００、ＧＦ３６００（何れも日立化成工業株式会社製　製品名）を挙げることができる。接着剤８の厚みとしては、１０μｍ～５０μｍを使用することができ、２０μｍ～５０μｍが望ましく、特には、２５μｍ～４０μｍが望ましい。これより薄い場合は、キャビティ層５の内層回路１９の厚みによる段差等を埋めることができず、またキャビティ層５とベース層６の寸法変化の挙動の違い等による歪みを吸収しにくくなる。これより厚い場合は、エラストマー材でもある接着剤８の動きが大きくなり、接続信頼性が低下する可能性がある。 The adhesive 8 is preferably an elastomer material. As the adhesive 8 used as the elastomer material, it should be used as long as it has sufficient adhesive strength and can absorb the distortion caused by the difference in dimensional change between the cavity layer 5 and the base layer 6. Can do. For example, with respect to 100 parts by mass of the epoxy resin and the curing agent component, 20 to 50 parts by mass of a rubber-modified epoxy resin, 10 to 40 parts by mass of a polymer component of an epoxy skeleton having a molecular weight of 10,000 or more, and a molecular weight of 50,000 Heat obtained by applying the adhesive composition comprising 50 parts by mass to 150 parts by mass of the rubber component and 0.3 part by mass to 2.5 parts by mass of a curing accelerator to a base film and heat-treating the semi-cured state. It can be formed by peeling the curable adhesive sheet from the substrate film and heating and pressing with a vacuum press or the like. An adhesive 8 that can be temporarily bonded to the cavity layer 5 and the base layer 6 by a laminator or the like is desirable from the viewpoint of workability. The adhesive 8 has an elastic modulus of 100 MPa to 500 MPa at 50 ° C. after heating and pressing, and is preferably about 500 MPa. The elastic modulus was measured by a DVE method using a Rhegel E-4000 type viscoelasticity measuring device manufactured by UBM Co., Ltd. under conditions of a tensile mode, a frequency of 10 Hz, and a heating rate of 5 ° C./min. The amount of resin flow (the amount of resin flow from the end after heating and pressurization) can be 50 μm to 1500 μm, and is preferably 100 μm to 500 μm from the balance between moldability and the amount of exudation into the bottomed via. In particular, about 300 μm is desirable. Note that the resin flow amount was obtained by punching the adhesive 8 in a sheet state before heating / pressing into a 10 mm diameter circle, and sandwiching it with a PET (polyethylene terephthalate) film, and pressing (100 ° C., 3 Mpa) 5 minutes), the diameters of the samples were measured at three locations and averaged, and the difference from the dimensions before pressing was determined by calculation. Examples of the rubber-modified epoxy resin include CTBN (carboxy group-terminated butadiene nitrile rubber) modified products and those having a modification rate of 30% to 60%. Examples of the rubber component include epoxy group-containing acrylonitrile butadiene rubber having a molecular weight of 50,000 or more. The semi-cured state can be obtained by setting the curing rate to 10% to 60% by heat treatment after being applied to the base film. By using such an adhesive 8 having an action as an elastomer, the adhesive 8 as an elastomer material absorbs distortion caused by the difference in the behavior of dimensional change between the cavity layer 5 and the base layer 6. Warpage of the element mounting package substrate 1 can be suppressed. In particular, when the materials and layer configurations used for the cavity layer 5 and the base layer 6 are different, or when the aperture ratio is different due to the opening 25 for the cavity portion 9, the cavity layer 5 and the base at the time of manufacture or use are different. Since the behavior of the dimensional change of the layer 6 is different, it is effective to use an elastomer material as the adhesive 8 used for lamination. Examples of the adhesive 8 include AS2600, AS3000, GF3500, and GF3600 (all are product names manufactured by Hitachi Chemical Co., Ltd.). The thickness of the adhesive 8 can be 10 μm to 50 μm, preferably 20 μm to 50 μm, and particularly preferably 25 μm to 40 μm. If the thickness is smaller than this, a step due to the thickness of the inner layer circuit 19 of the cavity layer 5 cannot be filled, and it becomes difficult to absorb strain due to a difference in behavior of dimensional change between the cavity layer 5 and the base layer 6. If it is thicker than this, the movement of the adhesive 8, which is also an elastomer material, increases, and connection reliability may be reduced.
　ベース層６は、キャビティ層５と積層されてキャビティ部９を形成するとともに、半導体素子２を搭載するための基板である。ベース層６は、絶縁層であるベース材２１のキャビティ層５側の面に、半導体と電気的に接続されるワイヤボンド端子１２と、このワイヤボンド端子１２と引き出し線（図示しない。）により電気的に接続される接続パッド１１とを有し、ベース材２１のキャビティ層５と反対側の面に、他の基板等と接続するための接続端子Ｂ１５を有し、これらの接続パッド１１と接続端子Ｂ１５とを電気的に接続する層間接続４２とを有する。ワイヤボンド端子１２、引き出し線（図示しない。）、接続パッド１１及び接続端子Ｂ１５を形成するパターンは、サブトラクト法等により作製することができる。ベース材２１は、半導体素子搭載用パッケージ基板１の製造に用いられる一般的な銅張り積層板やビルドアップ材を用いて作製できる。また、図４に示すように、これらの銅張り積層板をベース材ａ２８とし、ビルドアップ材をベース材ｂ２９及びベース材ｃ３０とし、これらを組み合わせて多層化したベース材２１も使用できる。層間接続４２は、ドリル加工やレーザ加工を用いて貫通孔や非貫通孔を形成し、これらの孔内にめっきを形成すること等により作製できる。なお、上記は、半導体素子２と接続パッド１１との電気的接続が、ワイヤボンド端子１２のみで行われる場合について述べたが、図６に示すように、ワイヤボンド端子１２に加えて接続端子Ｃ２７によって電気的に接続される場合も同様にして、ベース層６を形成できる。 The base layer 6 is a substrate on which the semiconductor element 2 is mounted while forming the cavity portion 9 by being laminated with the cavity layer 5. The base layer 6 is electrically connected to the surface of the base material 21 that is an insulating layer on the cavity layer 5 side by a wire bond terminal 12 that is electrically connected to a semiconductor, and the wire bond terminal 12 and a lead wire (not shown). Are connected to each other, and have a connection terminal B15 for connecting to another substrate or the like on the surface opposite to the cavity layer 5 of the base material 21, and connected to these connection pads 11. Interlayer connection 42 for electrically connecting terminal B15. The pattern for forming the wire bond terminal 12, the lead wire (not shown), the connection pad 11, and the connection terminal B15 can be produced by a subtracting method or the like. The base material 21 can be produced using a general copper-clad laminate or build-up material used for manufacturing the semiconductor element mounting package substrate 1. Moreover, as shown in FIG. 4, these copper-clad laminates can be used as a base material a28, build-up materials can be used as a base material b29 and a base material c30, and a base material 21 obtained by combining them can be used. The interlayer connection 42 can be manufactured by forming a through hole or a non-through hole using drilling or laser processing and forming plating in these holes. In the above, the case where the electrical connection between the semiconductor element 2 and the connection pad 11 is performed only by the wire bond terminal 12 is described. However, as shown in FIG. The base layer 6 can be formed in the same manner when electrically connected by.
　接続パッド１１は、ベース層６のキャビティ層５側の面のキャビティ部９に対応する領域以外の領域に設けられ、この接続パッド１１を底面とした有底ビア１３がキャビティ層５に形成される。この有底ビア１３の形成は、一例としては、図３に示すように、キャビティ材７にドリル加工、レーザ加工、パンチ加工、ルータ加工等で貫通孔Ａ２４を形成しておき、接着剤８を仮付けし、貫通孔Ａ２４に対応する部分の接着剤８をドリル加工、レーザ加工、パンチ加工、ルータ加工等で除去した後、図５に示すように、この貫通孔Ａ２４の位置と、接続パッド１１の位置が対応するように、キャビティ層５とベース層６とを積層することでなすことができる。他の例としては、キャビティ材７と接着剤８の両者にドリル加工、レーザ加工、パンチ加工、ルータ加工等で貫通孔Ａ２４を形成しておき、キャビティ材７と接着剤８の貫通孔Ａ２４の位置を合せてキャビティ材７に接着剤８を仮付けし、この貫通孔Ａ２４の位置と、接続パッド１１の位置が対応するように、キャビティ層５とベース層６とを積層することでなすことができる。さらに他の例としては、キャビティ層５とベース層６とを積層した後で、接続パッド１１に対応する部分のキャビティ層５を除去する方法がある。この場合は、除去をザグリ加工やレーザ加工で行う方法、あるいはキャビティ層５として感光性の材料を使用する方法を用いることができる。 The connection pad 11 is provided in a region other than the region corresponding to the cavity portion 9 on the surface of the base layer 6 on the cavity layer 5 side, and a bottomed via 13 having the connection pad 11 as a bottom surface is formed in the cavity layer 5. . As an example, the bottomed via 13 is formed by forming a through hole A24 in the cavity material 7 by drilling, laser processing, punching, router processing, etc., as shown in FIG. After temporarily attaching and removing the adhesive 8 corresponding to the through hole A24 by drilling, laser processing, punching, router processing, etc., as shown in FIG. 5, the position of this through hole A24 and the connection pad This can be done by stacking the cavity layer 5 and the base layer 6 so that the positions 11 correspond to each other. As another example, through-hole A24 is formed in both cavity material 7 and adhesive 8 by drilling, laser processing, punching, router processing, etc., and through-hole A24 of cavity material 7 and adhesive 8 is formed. The adhesive 8 is temporarily attached to the cavity material 7 in alignment, and the cavity layer 5 and the base layer 6 are laminated so that the position of the through hole A24 and the position of the connection pad 11 correspond to each other. Can do. As another example, there is a method in which the cavity layer 5 in a portion corresponding to the connection pad 11 is removed after the cavity layer 5 and the base layer 6 are laminated. In this case, it is possible to use a method in which removal is performed by counterbore processing or laser processing, or a method in which a photosensitive material is used as the cavity layer 5.
　図２に示すように、ベース層６のキャビティ層５と積層される側に、感光性樹脂層１０が形成されるのが望ましい。そして、有底ビア１３による層間接続３１を形成する目的で、接続パッド１１は少なくとも一部が露出した状態とされ、キャビティ層５とベース層６とを積層する際は、キャビティ層５の接着剤８とベース層６の感光性樹脂層１０が接着するようにするのが望ましい。これにより、接着剤８がベース層６の接続パッド１１に直接接着しないようにすることができ、積層時に接着剤８が接続パッド１１上に広がって、接続面積を縮小させ、接続抵抗が大きくなったり、接続信頼性が低下するのを抑制することができる。つまり、感光性樹脂層１０が、接続パッド１１と接着剤８との間に配置されることにより、積層時に接着剤８が接続パッド１１上に流動するのを妨げる作用を有する。また、ベース層６のキャビティ層５との接着面にある接続パッド１１等による段差を平坦にすることができ、キャビティ層５との接着に用いる接着剤８が薄く、流動性が低いものを用いても、接着剤８の追従を確保することができる。 As shown in FIG. 2, it is desirable that a photosensitive resin layer 10 is formed on the side of the base layer 6 that is laminated with the cavity layer 5. For the purpose of forming the interlayer connection 31 by the bottomed via 13, at least a part of the connection pad 11 is exposed, and when the cavity layer 5 and the base layer 6 are laminated, the adhesive for the cavity layer 5 is used. 8 and the photosensitive resin layer 10 of the base layer 6 are desirably adhered to each other. As a result, the adhesive 8 can be prevented from directly adhering to the connection pad 11 of the base layer 6, and the adhesive 8 spreads on the connection pad 11 during lamination, reducing the connection area and increasing the connection resistance. Or a reduction in connection reliability can be suppressed. That is, by disposing the photosensitive resin layer 10 between the connection pad 11 and the adhesive 8, the photosensitive resin layer 10 has an effect of preventing the adhesive 8 from flowing onto the connection pad 11 during lamination. Further, the step due to the connection pad 11 etc. on the bonding surface of the base layer 6 to the cavity layer 5 can be flattened, and the adhesive 8 used for bonding to the cavity layer 5 is thin and has low fluidity. However, the follow-up of the adhesive 8 can be ensured.
　感光性樹脂層１０としては、配線板や実装基板の製造に用いられる感光性のソルダーレジストを用いることができる。感光性のソルダーレジストとしては、半導体素子搭載用パッケージ基板や配線板で一般的に使用されるものを用いることができる。このようなものとしては、液状タイプのＰＳＲ４０００（太陽インキ株式会社製　商品名）や、ドライフィルムタイプのフォテックＳＲ３０００Ｇ（日立化成工業株式会社製、商品名）が使用できる。 As the photosensitive resin layer 10, a photosensitive solder resist used for manufacturing a wiring board or a mounting board can be used. As the photosensitive solder resist, those generally used for semiconductor device mounting package substrates and wiring boards can be used. As such, liquid type PSR4000 (trade name, manufactured by Taiyo Ink Co., Ltd.) and dry film type Photec SR3000G (trade name, manufactured by Hitachi Chemical Co., Ltd.) can be used.
　図５に示すように、有底ビア１３内には導電樹脂１７が充填される。導電樹脂１７の有底ビア１３への充填は、導電樹脂１７を印刷で塗布することにより行うことができる。有底ビア１３のアスペクト比が大きい場合は、例えば、真空印刷装置を用いることで、有底ビア１３内への気泡の残留を抑制することができ、充填性を確保できる。また、導電樹脂１７を充填する前に、有底ビア１３内に、金属被覆１８を形成するが望ましい。金属被覆１８は、例えば、電気銅めっきや無電解銅めっきにより形成することができる。これにより、有低ビアの内壁が滑らかになり、導電樹脂１７が有底ビア１３内に入り易くなるため、導電樹脂１７が充填し易くなる。また、めっきによる金属被覆１８と導電樹脂１７の両者で層間接続３１を形成するため、層間接続信頼性が向上する。 As shown in FIG. 5, the bottomed via 13 is filled with a conductive resin 17. Filling the bottomed via 13 with the conductive resin 17 can be performed by applying the conductive resin 17 by printing. When the aspect ratio of the bottomed via 13 is large, for example, by using a vacuum printing apparatus, it is possible to suppress the remaining of bubbles in the bottomed via 13 and to secure the filling property. Further, it is desirable to form a metal coating 18 in the bottomed via 13 before filling the conductive resin 17. The metal coating 18 can be formed by, for example, electrolytic copper plating or electroless copper plating. As a result, the inner wall of the low and low vias becomes smooth and the conductive resin 17 easily enters the bottomed via 13, so that the conductive resin 17 is easily filled. Further, since the interlayer connection 31 is formed by both the metal coating 18 and the conductive resin 17 by plating, the interlayer connection reliability is improved.
　このように、接続パッド１１と接続端子Ａ１４との層間接続３１が、有底ビア１３内に導電樹脂１７を充填することによって形成されるので、いわゆるフィルドビアめっきによるめっきの充填に比べて、給電のためのめっきリードを設ける必要がないため、設計の自由度が大きく、またその分、高密度化を図ることができる。また、フィルドビアめっきに比べて、よりアスペクト比が大きい場合（例えば、層間接続３１のための有底ビア１３の径がφ０．２ｍｍ、深さ０．２ｍｍ～０．５５ｍｍ）でも、接続パッド１１と接続端子Ａ１４との層間接続３１を形成できる。このため、キャビティ部９内に複数の半導体素子２を重ねて収納することが可能となる。また、このため、複数の半導体素子２を重ねて収納した場合でも、封止剤３の最上部が、接続端子Ａ１４と同等以下の高さとなるようにすることが可能である。したがって、本発明の半導体素子搭載用パッケージ基板１がＰｏＰにおけるボトム基板３３として用いられる場合、又は本発明の半導体パッケージ３６がＰｏＰにおけるボトムパッケージ３５として用いられる場合は、接続端子Ａ１４よりも上方に封止剤３が飛び出すことがないので、トップ基板３２又はトップパッケージ３４との接続の際に、封止剤３の高さを考慮した半田ボール径を用いる必要性がなく、半田ボール径の小径化が可能となる。また、これに伴い、接続端子Ａ１４の径（サイズ）やピッチの微細化が可能となる。 As described above, the interlayer connection 31 between the connection pad 11 and the connection terminal A14 is formed by filling the bottomed via 13 with the conductive resin 17, and therefore, compared to filling with plating by so-called filled via plating, Therefore, it is not necessary to provide a plating lead for this purpose, so that the degree of freedom in design is large and the density can be increased accordingly. Even when the aspect ratio is larger than that of filled via plating (for example, the diameter of the bottomed via 13 for the interlayer connection 31 is φ0.2 mm, the depth is 0.2 mm to 0.55 mm), An interlayer connection 31 with the connection terminal A14 can be formed. For this reason, a plurality of semiconductor elements 2 can be stacked and stored in the cavity portion 9. For this reason, even when a plurality of semiconductor elements 2 are stacked and stored, the uppermost portion of the sealant 3 can be set to a height equal to or lower than that of the connection terminal A14. Therefore, when the semiconductor element mounting package substrate 1 of the present invention is used as the bottom substrate 33 in PoP, or when the semiconductor package 36 of the present invention is used as the bottom package 35 in PoP, it is sealed above the connection terminal A14. Since the stopper 3 does not pop out, there is no need to use a solder ball diameter considering the height of the sealant 3 when connecting to the top substrate 32 or the top package 34, and the solder ball diameter is reduced. Is possible. Accordingly, the diameter (size) and pitch of the connection terminal A14 can be reduced.
　図７に示すように、一般に、ＰｏＰ用のボトム基板３３やボトムパッケージ３５では、トップ基板３２又はトップパッケージ３４と接続される接続端子Ａ１４の方がはんだボール３８径が大きい（例えば、φ０．６ｍｍ）ので、反対側の面の接続端子Ｂ１５よりも、端子の径（サイズ）が大きく（例えば、φ０．５ｍｍ）、ピッチも大きく（例えば、０．８ｍｍ）形成されている。しかしながら、図６に示すように、本発明においては、トップ基板３２又はトップパッケージ３４と接続される接続端子Ａ１４の方が、反対側の面の接続端子Ｂ１５よりも、端子の径（サイズ）が小さく（例えば、φ０．２５ｍｍ）、ピッチも小さく（例えば、φ０．４ｍｍ）形成することが可能となる。このため、より端子数の多いトップ基板３２又はトップパッケージ３４との高密度な接続が可能となる。 As shown in FIG. 7, generally, in the PoP bottom substrate 33 and the bottom package 35, the connecting terminal A14 connected to the top substrate 32 or the top package 34 has a larger solder ball 38 diameter (for example, φ0.6 mm). Therefore, the terminal diameter (size) is larger (for example, φ0.5 mm) and the pitch is larger (for example, 0.8 mm) than the connection terminal B15 on the opposite surface. However, as shown in FIG. 6, in the present invention, the connecting terminal A14 connected to the top substrate 32 or the top package 34 has a terminal diameter (size) that is larger than the connecting terminal B15 on the opposite surface. It can be formed small (for example, φ0.25 mm) and with a small pitch (for example, φ0.4 mm). Therefore, high-density connection with the top substrate 32 or the top package 34 having a larger number of terminals is possible.
　また、従来のスルーホールめっきによる層間接続３１の形成では、有底ビア１３の直上に接続端子を設けることができないが、本発明によれば、有底ビア１３上に金属被覆１８を施すことも可能なので、有底ビア１３の直上に外部接続端子（接続端子Ａ１４）を設けることができ、高密度化を図ることができる。 Further, in the formation of the interlayer connection 31 by the conventional through-hole plating, the connection terminal cannot be provided immediately above the bottomed via 13. However, according to the present invention, the metal coating 18 may be provided on the bottomed via 13. Since it is possible, an external connection terminal (connection terminal A14) can be provided immediately above the bottomed via 13, and high density can be achieved.
　導電樹脂１７は、導電成分として銀、銅、カーボン等を、バインダーとしてエポキシ樹脂、フェノール樹脂等の熱硬化性樹脂を含むものを用いることができる。また、充填後の導電樹脂１７を硬化させる。導電樹脂１７が十分硬化していないと、後の加熱で導電樹脂１７の架橋密度が増し、体積収縮によるボイドやクラック、界面破壊が発生し、接続信頼性が低下する。導電樹脂１７のバインダーは再硬化しないものが好ましい。 As the conductive resin 17, a material containing silver, copper, carbon or the like as a conductive component and a thermosetting resin such as an epoxy resin or a phenol resin as a binder can be used. Moreover, the conductive resin 17 after filling is cured. If the conductive resin 17 is not sufficiently cured, the crosslinking density of the conductive resin 17 is increased by subsequent heating, voids, cracks, and interface breakage occur due to volume shrinkage, and connection reliability decreases. The binder of the conductive resin 17 is preferably not re-cured.
　有底ビア１３内に導電樹脂１７が充填され、硬化されることで、有底ビア１３全体の剛性が向上する。上述したように、接着剤８としてエラストマー材を使用した場合、キャビティ層５とベース層６の寸法変化の挙動が異なる場合でも、接着剤８がその歪みを吸収し、反りやねじれ等の発生を抑制する。一方で、この歪みを吸収する際に、接着剤８に歪の応力が集中し変形する。このため、例えば、一般的なスルーホールめっきのみで有底ビア１３の層間接続を形成した場合、接着剤８の部分でクラックが発生し、接続不良が生じることが考えられる。しかしながら、有底ビア１３内には、導電樹脂１７が充填され、硬化されているので、有底ビア１３全体の剛性が向上しているため、導電樹脂１７により層間接続３１が形成された箇所は、接着剤８の変形が抑えられる。導電樹脂１７を充填する前に、有底ビア１３内に、めっきにより金属被覆１８を形成するのが、導電樹脂１７の充填性や層間接続信頼性の点でより望ましい。層間接続３１が形成されておらず、導電樹脂１７のない部分では、接着剤８が変形して歪みを吸収する。このようにして、接着剤８としてエラストマー材を用いた場合でも、有底ビア１３内に導電樹脂１７が充填され、硬化されることで、接続信頼性を確保しつつ、反りや変形を抑制可能な半導体素子搭載用パッケージ基板を提供できる。 When the bottomed via 13 is filled with the conductive resin 17 and cured, the rigidity of the bottomed via 13 as a whole is improved. As described above, when an elastomer material is used as the adhesive 8, even when the dimensional change behaviors of the cavity layer 5 and the base layer 6 are different, the adhesive 8 absorbs the distortion and generates warping, twisting, and the like. Suppress. On the other hand, when the strain is absorbed, the stress of the strain concentrates on the adhesive 8 and is deformed. For this reason, for example, when the interlayer connection of the bottomed via 13 is formed only by general through-hole plating, it is conceivable that a crack occurs in the portion of the adhesive 8 and a connection failure occurs. However, since the bottomed via 13 is filled with the conductive resin 17 and hardened, the rigidity of the bottomed via 13 as a whole is improved. Therefore, the portion where the interlayer connection 31 is formed by the conductive resin 17 is as follows. The deformation of the adhesive 8 is suppressed. Before filling the conductive resin 17, it is more desirable to form the metal coating 18 by plating in the bottomed via 13 in terms of filling property of the conductive resin 17 and interlayer connection reliability. In the portion where the interlayer connection 31 is not formed and the conductive resin 17 is not present, the adhesive 8 is deformed to absorb the distortion. In this way, even when an elastomer material is used as the adhesive 8, the conductive resin 17 is filled in the bottomed via 13 and cured, so that warpage and deformation can be suppressed while ensuring connection reliability. A package substrate for mounting a semiconductor device can be provided.
　導電成分は、平均粒径３０μｍ以下の銅粉または銅粉の表面に銀めっきしたもの（以下、「銀めっき銅粉」という。）または銅粉の表面に金めっきしたもの（以下、「金めっき銅粉」という。）を含む金属粉を用いるのが望ましい。これらの中でも、無電解ニッケルめっきや無電解金めっきの析出性が優れる点で、主な導電成分が、銀めっき銅粉や金めっき銅粉であるのが望ましい。金属粉の平均粒径が３０μｍを越えると、印刷時にスクリーンが目詰まりしたり、ペーストの伸びが悪くなり、印刷性が劣る。金属粉の形状は、フレーク状又は樹枝状であると、金属粉同士の接触が良くなり、導電性が向上するので好ましい。また他の形状の金属粉をスタンピング等の処理をしてフレーク状にして用いてもよい。銀めっき銅粉における銀めっきや金めっき銅粉における金めっきは、電解めっき法、無電解めっき法、置換めっき法等の何れの方法でめっきしたものでもよく特に制限はない。導電樹脂１７中の導電成分の含有量としては、６５質量％～８０質量％が望ましく、特には７６質量％程度が望ましい。これより少ない場合は、無電解めっきの析出性が低下し、導電樹脂１７上が金属皮膜１６によって被覆されない場合があり、これよりも多い場合は、導電樹脂１７のペースト状態における粘度が高くなり、印刷性が低下して、有底ビア１３への充填が困難になる。 The conductive component is copper powder having an average particle size of 30 μm or less or a silver-plated copper powder surface (hereinafter referred to as “silver-plated copper powder”) or a gold-plated copper powder surface (hereinafter “gold-plated”). It is desirable to use metal powder containing “copper powder”. Among these, it is desirable that the main conductive component is silver-plated copper powder or gold-plated copper powder in terms of excellent depositability of electroless nickel plating or electroless gold plating. When the average particle size of the metal powder exceeds 30 μm, the screen is clogged during printing, the paste does not grow well, and the printability is poor. When the shape of the metal powder is flaky or dendritic, contact between the metal powders is improved and conductivity is improved, which is preferable. Moreover, you may use the metal powder of another shape by processing, such as stamping, and making it into flakes. Silver plating in silver-plated copper powder and gold plating in gold-plated copper powder may be any of plating methods such as an electrolytic plating method, an electroless plating method, and a displacement plating method, and are not particularly limited. The content of the conductive component in the conductive resin 17 is preferably 65% by mass to 80% by mass, and particularly preferably about 76% by mass. If the amount is less than this, the electroless plating deposition may be reduced, and the conductive resin 17 may not be covered with the metal film 16. If the amount is more than this, the viscosity of the conductive resin 17 in the paste state becomes high, The printability is lowered, and it becomes difficult to fill the bottomed via 13.
　このように、導電成分として、銅粉、銀めっき銅粉、金めっき銅粉を含むものを用いると、導電樹脂１７上に金属皮膜１６を形成する際には、導電樹脂１７上に触媒を付与する処理を行うことなく、導電成分を露出させるだけで、無電解めっきまたは電気めっきによって直接金属皮膜１６を形成することができる点で望ましい。これらの中でも、主な導電成分が、銀めっき銅粉、金めっき銅粉であるのが、無電解ニッケルめっきや無電解金めっきまたは電気ニッケルめっきや電気金めっき、電気銅めっきの析出性が優れる点で望ましい。この場合は、導電樹脂１７中の導電成分を露出させるだけで、無電解めっきが、導電樹脂１７中に含まれる導電成分のめっき触媒活性によって、直接導電成分上に析出するので、無電解めっきを所定の厚みまで形成することにより、導電樹脂１７上全体が無電解めっきにより完全に被覆され、結果的に導電樹脂１７上に直接金属皮膜１６が形成される。また、導電樹脂１７中の導電成分を露出させるだけで、この導電成分からの給電により、電気めっきが直接導電成分上に析出するので、電気めっきを所定の厚みまで形成することにより、導電樹脂１７上全体が電気めっきにより完全に被覆され、結果的に導電樹脂１７上に直接金属皮膜１６が形成される。また、導電樹脂１７を充填した後には、有底ビア１３の入り口側の表面を平滑化するためにバフ研磨等の物理的研磨を行うが、この物理的研磨によって、導電樹脂１７中の導電成分が露出した状態で有底ビア１３の入り口側に配置されるので、過マンガン酸や硫酸を用いたデスミア処理を用いて導電樹脂１７をエッチングし導電成分を露出させることを必要とせずに、無電解めっきまたは電気めっきによって、導電成分上に金属皮膜１６を直接形成することができる点で望ましい。また、デスミア処理を必要としないため、導電樹脂１７以外の部分（例えば、接着剤８や感光性樹脂層１０等）にデスミア処理による影響がないように、マスキングしたりする工程が不要となる点で望ましい。また、導電樹脂１７に対してデスミア処理を行った場合は、導電樹脂１７の導電成分を保持する樹脂成分までもがエッチングされてしまい、導電成分が脱落する結果、導電樹脂１７上に無電解めっきまたは電気めっきの析出性が低下し、完全に金属皮膜１６で被覆できない問題や、導電樹脂１７上の金属皮膜１６の密着が得られ難い問題があるが、本発明では、物理的研磨のみによって導電樹脂１７中の導電成分を露出させるので、このような問題がないため、導電樹脂１７上を金属皮膜１７で完全に被覆することができ、また導電樹脂１７と金属皮膜１６との密着を確保できる。さらに、物理的研磨によって導電樹脂１７上に形成された凹凸が、投錨効果によって金属皮膜１６との密着を向上させる効果を有する。また、このように、本発明では、導電樹脂１７上に金属皮膜１６を形成する際には、導電樹脂１７上に触媒を付与する処理やデスミア処理を何れも行うことなく、物理的研磨で導電成分を露出させるだけで、無電解めっきまたは電気めっきによって直接金属皮膜１６を形成することができる。このため、金属皮膜１６を形成する部分以外に対して、保護のためのマスキングを行なう工程や触媒を除去する工程が不要であり、また、導電樹脂１７上以外に、金属皮膜１６を形成する部分がある場合（例えば、キャビティ部９内に露出したベース層６上のワイヤボンド端子１２等）でも、導電樹脂１７上とこれ以外の金属皮膜１６を形成したい部分の両者を、一括処理によって、同時に金属皮膜１６を形成することができる。したがって、大幅に工数低減を図ることができる。 As described above, when a conductive component containing copper powder, silver-plated copper powder, or gold-plated copper powder is used, a catalyst is applied to the conductive resin 17 when the metal film 16 is formed on the conductive resin 17. This is desirable in that the metal film 16 can be directly formed by electroless plating or electroplating only by exposing the conductive component without performing the treatment. Of these, the main conductive components are silver-plated copper powder and gold-plated copper powder. Desirable in terms. In this case, only by exposing the conductive component in the conductive resin 17, the electroless plating is directly deposited on the conductive component due to the plating catalyst activity of the conductive component contained in the conductive resin 17. By forming to a predetermined thickness, the entire conductive resin 17 is completely covered by electroless plating, and as a result, the metal film 16 is formed directly on the conductive resin 17. Moreover, since the electroplating is directly deposited on the conductive component by supplying power from the conductive component only by exposing the conductive component in the conductive resin 17, the conductive resin 17 is formed by forming the electroplating to a predetermined thickness. The entire upper surface is completely covered by electroplating, and as a result, the metal film 16 is formed directly on the conductive resin 17. In addition, after the conductive resin 17 is filled, physical polishing such as buffing is performed to smooth the surface on the entrance side of the bottomed via 13, and the conductive component in the conductive resin 17 is obtained by this physical polishing. Is disposed at the entrance side of the bottomed via 13 without exposing the conductive component 17 by using a desmear process using permanganic acid or sulfuric acid to expose the conductive component. It is desirable in that the metal film 16 can be directly formed on the conductive component by electrolytic plating or electroplating. Further, since the desmear process is not required, a step of masking or the like is unnecessary so that portions other than the conductive resin 17 (for example, the adhesive 8 and the photosensitive resin layer 10) are not affected by the desmear process. Is desirable. Further, when the desmear treatment is performed on the conductive resin 17, even the resin component holding the conductive component of the conductive resin 17 is etched, and as a result of the conductive component dropping off, the electroless plating is performed on the conductive resin 17. Alternatively, there is a problem that the deposition property of electroplating is deteriorated and cannot be completely covered with the metal film 16 or that the metal film 16 on the conductive resin 17 is not easily adhered. Since the conductive component in the resin 17 is exposed, there is no such problem, so that the conductive resin 17 can be completely covered with the metal film 17 and the adhesion between the conductive resin 17 and the metal film 16 can be secured. . Furthermore, the unevenness formed on the conductive resin 17 by physical polishing has an effect of improving the adhesion with the metal film 16 by the anchoring effect. As described above, according to the present invention, when the metal film 16 is formed on the conductive resin 17, the conductive film 17 is electrically polished by physical polishing without performing any treatment for applying a catalyst or desmear treatment on the conductive resin 17. The metal film 16 can be formed directly by electroless plating or electroplating simply by exposing the components. For this reason, a masking process for protection and a process for removing the catalyst are not required for parts other than the part for forming the metal film 16, and the part for forming the metal film 16 other than on the conductive resin 17. Even if there is (for example, the wire bond terminal 12 on the base layer 6 exposed in the cavity portion 9), both the conductive resin 17 and the portion where the other metal film 16 is to be formed can be simultaneously processed by batch processing. A metal film 16 can be formed. Therefore, the man-hour can be greatly reduced.
　導電樹脂１７上に形成する無電解めっきとしては、導電樹脂１７中に含まれる導電成分のめっき触媒活性によって析出するものであれば、使用することが可能であるが、析出性がよい点で無電解ニッケルめっきや無電解金めっきが望ましい。無電解ニッケルめっきを行った上にさらに置換金めっきや無電解金めっきを行うと、この金属皮膜１６によって形成される接続端子Ａ１４表面の酸化が抑制されるため、接続時の接触抵抗の上昇を抑え、またはんだ濡れ性を維持できる点で望ましい。なお、本発明において、無電解金めっきとは、いわゆる還元型の無電解金めっきをいい、置換型の金めっきとは区別されるものをいう。無電解ニッケルめっきの厚みは、４μｍ～６μｍが望ましい。無電解ニッケルめっきの厚みがこれより薄いと導電樹脂１７上の金属皮膜１６による被覆が不十分となり信頼性低下の可能性がある。無電解ニッケルめっきの厚みがこれより厚いと、コストアップに繋がり、まためっき応力が大きくなって金属皮膜１６の密着が低下する可能性がある。なお、従来のスルーホールめっきと穴埋め樹脂の充填による層間接続３１の形成では、穴埋め樹脂が無電解めっきに対して触媒活性を有しないので、めっき触媒の付与が必要であり、この場合は、めっきが不要な領域には、めっき触媒が付かないようにマスクする必要があるため、工数が多くなる問題があった。本発明によれば、無電解めっきに対して触媒活性を有する導電樹脂１７を使用し、導電樹脂１７中の導電成分の露出をバフ研磨等の物理的研磨で行うので、無電解めっきの析出性や密着性が確保できる。このため、無電解めっきとして、従来のように下地めっきとして無電解銅めっきを行ってから無電解ニッケルめっきと置換金めっきや無電解金めっき等を行う必要がなく、少ない工数で、有底ビア１３の直上に、はんだ濡れ性を確保した接続端子を形成することができる。 The electroless plating formed on the conductive resin 17 can be used as long as it deposits due to the plating catalyst activity of the conductive component contained in the conductive resin 17, but it has no depositing property. Electrolytic nickel plating or electroless gold plating is desirable. When electroless nickel plating is performed and further displacement gold plating or electroless gold plating is performed, oxidation of the surface of the connection terminal A14 formed by the metal film 16 is suppressed, so that the contact resistance during connection is increased. It is desirable because it can suppress or maintain wettability. In the present invention, electroless gold plating refers to so-called reduction-type electroless gold plating, which is distinguished from substitution-type gold plating. The thickness of the electroless nickel plating is desirably 4 μm to 6 μm. If the thickness of the electroless nickel plating is smaller than this, the coating with the metal film 16 on the conductive resin 17 becomes insufficient, and the reliability may be lowered. If the thickness of the electroless nickel plating is thicker than this, it may lead to an increase in cost, and the plating stress may increase to reduce the adhesion of the metal film 16. In addition, in formation of the interlayer connection 31 by the conventional through-hole plating and filling of hole filling resin, since the hole filling resin does not have catalytic activity for electroless plating, it is necessary to apply a plating catalyst. Since it is necessary to mask an area where no plating is required so that the plating catalyst is not attached, there is a problem that man-hours increase. According to the present invention, the conductive resin 17 having catalytic activity for electroless plating is used, and the conductive component in the conductive resin 17 is exposed by physical polishing such as buff polishing. And adhesion can be secured. For this reason, there is no need to perform electroless nickel plating, displacement gold plating, electroless gold plating, etc. after performing electroless copper plating as the base plating as in the past as electroless plating. A connection terminal ensuring solder wettability can be formed immediately above 13.
　導電樹脂１７上に形成する電気めっきとしては、導電樹脂１７中に含まれる導電成分の導電性を利用して給電することによって、直接導電成分上に析出するものであれば、使用することが可能であるが、析出性がよい点で電気ニッケルめっきや電気金めっき、電気銅めっきが望ましい。導電樹脂１７の導電成分上に直接電気銅めっきを行なった上に無電解ニッケルめっきもしくは電気ニッケルめっきを行い、さらに置換金めっきもしくは無電解金めっきもしくは電気金めっきを行う場合、または導電樹脂１７の導電成分上に直接電気ニッケルめっきを行った上に、さらに置換金めっきもしくは無電解金めっきもしくは電気めっきを行う場合は、この金属皮膜１６によって形成される接続端子Ａ１４表面の酸化が抑制されるため、接続時の接触抵抗の上昇を抑え、またはんだ濡れ性を維持できる点で望ましい。特に、後者のように、導電樹脂１７の導電成分上に直接電気ニッケルめっきを行なうと、前者のように、電気ニッケルめっきの下地めっきとして電気銅めっきを行う必要がなく、少ない工数で、有底ビア１３の直上に、はんだ濡れ性を確保した接続端子を形成することができる。このように、導電樹脂１７の導電成分上に直接電気ニッケルめっきを行なう場合、電気ニッケルめっきの厚みは、４μｍ～１６μｍが望ましい。電気ニッケルめっきの厚みがこれより薄いと導電樹脂１７上の金属皮膜１６による被覆が不十分となり信頼性低下の可能性がある。電気ニッケルめっきの厚みがこれより厚いと、コストアップに繋がり、まためっき応力が大きくなって金属皮膜１６の密着が低下する可能性がある。なお、電気ニッケルめっきの上に電気金めっきを行う場合、電気金めっきの厚みは、０．５μｍ～１．５μｍが望ましい。電気金めっきの厚みがこれより薄いと、表面の酸化を抑制する効果が低下し、一方、電気金めっきの厚みがこれより厚いと、コストアップに繋がる。 The electroplating formed on the conductive resin 17 can be used as long as it is deposited directly on the conductive component by supplying power using the conductivity of the conductive component contained in the conductive resin 17. However, electro nickel plating, electro gold plating, and electro copper plating are desirable in terms of good precipitation. When performing electro copper plating directly on the conductive component of the conductive resin 17 and performing electroless nickel plating or electro nickel plating, and further performing displacement gold plating, electroless gold plating or electro gold plating, or In the case of performing electroplating directly on the conductive component and further performing displacement gold plating, electroless gold plating or electroplating, oxidation of the surface of the connection terminal A14 formed by the metal film 16 is suppressed. It is desirable in that the increase in contact resistance at the time of connection can be suppressed or the wettability can be maintained. In particular, when the electro-nickel plating is performed directly on the conductive component of the conductive resin 17 as in the latter, it is not necessary to perform the electro-copper plating as the base plating of the electro-nickel plating as in the former, and the bottom is formed with a small number of man-hours. A connection terminal ensuring solder wettability can be formed immediately above the via 13. As described above, when the electro nickel plating is directly performed on the conductive component of the conductive resin 17, the thickness of the electro nickel plating is desirably 4 μm to 16 μm. If the thickness of the electro nickel plating is smaller than this, the coating with the metal film 16 on the conductive resin 17 becomes insufficient, and the reliability may be lowered. If the thickness of the electronickel plating is thicker than this, the cost will increase, and the plating stress may increase and the adhesion of the metal film 16 may decrease. When electrogold plating is performed on electronickel plating, the thickness of electrogold plating is preferably 0.5 μm to 1.5 μm. If the thickness of the electrogold plating is thinner than this, the effect of suppressing the oxidation of the surface is lowered. On the other hand, if the thickness of the electrogold plating is thicker than this, the cost is increased.
　導電樹脂１７上には、接続端子Ａ１４が設けられる。接続端子Ａ１４は、外部基板と電気的に接続するためのものであり、本発明の半導体素子搭載用パッケージ基板１がＰｏＰにおけるボトム基板３３として用いられる場合、又は本発明の半導体パッケージ３６がＰｏＰにおけるボトムパッケージ３５として用いられる場合は、トップ基板３２（他の半導体素子搭載用パッケージ基板１）又はトップパッケージ３４（他のパッケージ基板）との接続のための接続端子として用いられる。 On the conductive resin 17, a connection terminal A14 is provided. The connection terminal A14 is for electrically connecting to an external substrate. When the semiconductor element mounting package substrate 1 of the present invention is used as the bottom substrate 33 in PoP, or the semiconductor package 36 of the present invention is in PoP. When used as the bottom package 35, it is used as a connection terminal for connection to the top substrate 32 (other semiconductor element mounting package substrate 1) or the top package 34 (other package substrate).
　導電樹脂１７を充填し硬化した後に、有底ビア１３よりも上方に飛び出した導電樹脂１７に対して行う研磨としては、例えばバフ研磨やベルトサンダー等を用いる物理的研磨を使用することができる。中でもバフロールによる機械研磨が好ましく、バフの番手は、６００番、８００番、１０００番、あるいはそれらを組み合わせて使用する。バフロールとしては、例えば、穴埋め樹脂研磨用のＪＰバフモンスターＶ３／Ｖ３－Ｄ２（ジャブロ工業製　商品名）を使用することができる。また、研磨電流は０．１Ａ～２．０Ａ程度で研磨を行うが、削る導電樹脂１７の量によって電流値も調整する。好ましくは１．０Ａ～１．４Ａ程度である。 As the polishing performed on the conductive resin 17 that protrudes upward from the bottomed via 13 after the conductive resin 17 is filled and cured, for example, buffing, physical polishing using a belt sander, or the like can be used. Among these, mechanical polishing with buffalo is preferable, and the buff count is 600, 800, 1000, or a combination thereof. As the baffle, for example, JP buff monster V3 / V3-D2 (trade name, manufactured by Jablo Kogyo) for hole filling resin polishing can be used. Polishing is performed at a polishing current of about 0.1 A to 2.0 A, and the current value is also adjusted according to the amount of the conductive resin 17 to be cut. Preferably, it is about 1.0A to 1.4A.
　接続端子Ａ１４の形成の一例としては、まず有底ビア１３内に充填した導電樹脂１７の上に、金属皮膜１６を形成することで行われる。例えば、有底ビア１３内に導電樹脂１７を充填後、研磨して、導電樹脂１７表面をキャビティ材７と面一とするとともに、予めキャビティ材７上に備える銅箔４０を露出させる（ここで、導電樹脂１７を充填する前に有底ビア１３内に金属被覆１８を行った場合は、金属被覆１８を露出させる。）。そして、露出した銅箔４０（または金属被覆１８）と導電樹脂１７上にめっきレジスト(図示しない。）を形成後、無電解めっきまたは電気めっきで金属皮膜１６を形成し、これをエッチングレジストとしてエッチングすることにより、不要な箇所の銅箔４０を除去して接続端子Ａ１４を形成する。無電解めっきは、無電解銅めっき、無電解ニッケルめっき、無電解金めっき等を用いることができ、電気めっきは、電気銅めっき、電気ニッケルめっき、電気金めっき等を用いることができる。この場合の無電解めっきとしては、触媒付与を行わなくても導電樹脂１７上への析出性がよい点で、無電解ニッケルめっきや無電解金めっきが望ましい。電気めっきとしては、導電樹脂１７上への析出性がよい点で、電気ニッケルめっきや電気金めっきが望ましい。このように、導電樹脂１７とランドパターンのみに選択的に直接金属皮膜１６を形成することができることにより、キャビティ材７上の他の部分の導体厚を薄くできるので、微細なピッチの端子が形成し易く、高密度化を図ることが可能になる。 As an example of formation of the connection terminal A14, first, the metal film 16 is formed on the conductive resin 17 filled in the bottomed via 13. For example, after filling the bottomed via 13 with the conductive resin 17, polishing is performed so that the surface of the conductive resin 17 is flush with the cavity material 7, and the copper foil 40 previously provided on the cavity material 7 is exposed (here, If the metal coating 18 is applied to the bottomed via 13 before the conductive resin 17 is filled, the metal coating 18 is exposed. Then, after forming a plating resist (not shown) on the exposed copper foil 40 (or the metal coating 18) and the conductive resin 17, a metal film 16 is formed by electroless plating or electroplating, and this is used as an etching resist. By doing so, the copper foil 40 of an unnecessary location is removed and the connection terminal A14 is formed. For electroless plating, electroless copper plating, electroless nickel plating, electroless gold plating, or the like can be used. For electroplating, electrolytic copper plating, electrolytic nickel plating, electrogold plating, or the like can be used. As the electroless plating in this case, electroless nickel plating or electroless gold plating is desirable in that the deposition on the conductive resin 17 is good without applying a catalyst. As the electroplating, electronickel plating or electrogold plating is desirable in terms of good precipitation on the conductive resin 17. As described above, the metal film 16 can be selectively formed directly only on the conductive resin 17 and the land pattern, so that the conductor thickness of other portions on the cavity material 7 can be reduced, so that terminals with a fine pitch are formed. This makes it possible to increase the density.
　半導体素子２は、キャビティ層５側の面のキャビティ部９に対応する領域に搭載される。半導体素子２の搭載は、例えばダイボンドフィルムでベース層６上に接着され、ワイヤボンド端子１２とボンディングワイヤ４によって半導体素子２と電気的に接続される。この半導体素子２のベース層６への搭載は、接続端子Ｃ２７（図６）を用いて、フリップチップ接続や導電性接着剤による接続を用いることもできる。 The semiconductor element 2 is mounted in a region corresponding to the cavity portion 9 on the surface on the cavity layer 5 side. For mounting the semiconductor element 2, the semiconductor element 2 is bonded onto the base layer 6 with a die bond film, for example, and is electrically connected to the semiconductor element 2 by the wire bond terminal 12 and the bonding wire 4. The semiconductor element 2 can be mounted on the base layer 6 by using a connection terminal C27 (FIG. 6), or flip-chip connection or connection using a conductive adhesive.
　半導体素子２は、湿気等の環境から保護するために、封止剤３により封止される。このような封止剤３として、エポキシ樹脂、ポリイミド樹脂、シリコン、ウレタンフェノーツ系樹脂、ポリエステル系樹脂、アクリル系樹脂他熱硬化性樹脂、熱可塑性樹脂等を用いることができる。 The semiconductor element 2 is sealed with a sealant 3 in order to protect it from an environment such as moisture. As such an encapsulant 3, epoxy resin, polyimide resin, silicon, urethane phenoz resin, polyester resin, acrylic resin, other thermosetting resin, thermoplastic resin, or the like can be used.
　以下に、本発明の実施例を説明するが、本発明は本実施例に限定されない。 Examples of the present invention will be described below, but the present invention is not limited to the examples.
（実施例１）
［キャビティ層の作製］
　図３に示すように、キャビティ材７として、両面に厚さ１２μｍの銅箔を張合わせた厚さ０．２ｍｍのエポキシ樹脂ガラス布銅張積層板であるＭＣＬ－Ｅ６７９Ｆ（日立化成工業株式会社製、商品名）を準備した。ＮＣドリルマシンであるＭＡＲＫ－１００（日立精工株式会社製、商品名）によって、ガイド孔（図示しない。）と貫通孔Ａ２４を孔明けした。 Example 1
[Cavity layer fabrication]
As shown in FIG. 3, the cavity material 7 is MCL-E679F (manufactured by Hitachi Chemical Co., Ltd.), which is a 0.2 mm thick epoxy resin glass cloth copper clad laminate in which a copper foil having a thickness of 12 μm is laminated on both sides. , Product name). A guide hole (not shown) and a through-hole A24 were drilled by MARK-100 (trade name, manufactured by Hitachi Seiko Co., Ltd.), which is an NC drill machine.
　次に、キャビティ材７の銅箔の表面に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４２５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついで、その上にネガ型マスクを張り合わせ、紫外線で露光し、回路を焼付け、１質量％の炭酸ナトリウム水溶液で現像し、エッチングレジストを形成した後、銅箔４０上のエッチングレジストのない部分をスプレー噴霧によって、塩化第二銅、塩酸、硫酸過水の組成からなる塩化第二銅エッチング液で圧力０．２ＭＰａ、速度３．５ｍ／分の条件で行い、さらに３質量％水酸化ナトリウム水溶液を噴霧してエッチングレジストを剥離除去し、銅のパターンを形成した。これにより、一方の面については、貫通孔Ａ４０の周りにアニュラリングとなる内層回路１９を形成した。他方の面、即ち接続端子Ａ１４を形成する面については、ほぼ全面に銅箔４０を残した。 Next, on the surface of the copper foil of the cavity material 7, a UV-curable etching resist dry film H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under conditions of 0.5 m / min, and then a negative mask is laminated thereon, exposed to ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed. The portion without the etching resist on the foil 40 is sprayed and sprayed with a cupric chloride etchant composed of cupric chloride, hydrochloric acid and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa and speed 3.5 m / min. Further, a 3% by mass sodium hydroxide aqueous solution was sprayed to peel off and remove the etching resist to form a copper pattern. Thereby, the inner layer circuit 19 which becomes an annular ring was formed around the through hole A40 on one surface. On the other surface, that is, the surface on which the connection terminal A14 is formed, the copper foil 40 is left almost on the entire surface.
　次に、接着剤８として、厚さ２５μｍのエポキシ系ドライフィルム状の接着シートＡＳ２６００（日立化成工業株式会社製、商品名）を用い、ラミネータにより、９０℃の温度で、圧力を０．４ＭＰａとし、送り速度０．４ｍ／分で、加熱・加圧して、キャビティ材７に仮付けした。次に、接着シートには、キャビティ材７に設けた貫通孔Ａ２４に合わせて、開口部を打ち抜き金型で形成した。次に、ＮＣルータ機を用いて、１２ｍｍ×１２ｍｍの大きさの開口２５を形成した。 Next, an adhesive sheet AS2600 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 25 μm and having a thickness of 25 μm is used as the adhesive 8, and the pressure is set to 0.4 MPa at a temperature of 90 ° C. with a laminator. The cavity material 7 was temporarily attached by heating and pressurizing at a feed rate of 0.4 m / min. Next, an opening was formed in the adhesive sheet by a punching die in accordance with the through hole A24 provided in the cavity material 7. Next, an opening 25 having a size of 12 mm × 12 mm was formed using an NC router.
［ベース層の作製］
　図４に示すように、ベース材ａ２８として、両面に厚さ１２μｍの銅箔を張合わせた厚さ０．０６ｍｍのエポキシ樹脂ガラス布銅張積層板であるＭＣＬ－Ｅ６７９Ｆ（日立化成工業株式会社製、商品名）にＮＣドリルマシンであるＭＡＲＫ－１００（日立精工株式会社製、商品名）によって、貫通孔Ｂ３９を明けた。 [Preparation of base layer]
As shown in FIG. 4, as the base material a28, MCL-E679F (manufactured by Hitachi Chemical Co., Ltd.), which is a 0.06 mm thick epoxy resin glass cloth copper clad laminate in which a copper foil of 12 μm thickness is laminated on both sides. Through-hole B39 was opened with MARK-100 (trade name, manufactured by Hitachi Seiko Co., Ltd.), which is an NC drill machine.
　次に、この貫通孔Ｂ３９のデスミア処理を過マンガン酸ナトリウム水溶液に温度８５℃で６分間の条件で行い、無電解銅めっきであるＣＵＳＴ２０１（日立化成工業株式会社製、商品名）、硫酸銅１０ｇ／Ｌ、ＥＤＴＡ４０ｇ／Ｌ、ホルマリン１０ｍｌ／Ｌ、ｐＨ１２．２）に温度２４℃、時間３０分の条件で、貫通孔Ｂ３９内を含むベース材ａ２８の全面に０．５μｍの下地銅めっきを行った。次に、硫酸銅めっきで温度３０℃、電流密度１．５Ａ／ｄｍ２、時間６０分の条件で、貫通孔Ｂ３９内を含むベース材ａ２８の全面に、めっき厚２０μｍの電気銅めっき４１を形成した。 Next, the desmear treatment of the through hole B39 is performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes, and electroless copper plating CUST201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), copper sulfate 10 g / L, EDTA 40 g / L, formalin 10 ml / L, pH 12.2) under conditions of a temperature of 24 ° C. and a time of 30 minutes, a base copper plating of 0.5 μm was performed on the entire surface of the base material a28 including the inside of the through hole B39. . Next, an electrolytic copper plating 41 with a plating thickness of 20 μm is formed on the entire surface of the base material a28 including the inside of the through hole B39 under the conditions of copper sulfate plating at a temperature of 30 ° C., a current density of 1.5 A / dm 2 , and a time of 60 minutes. did.
　次に、ベース材ａ２８の銅箔４０表面に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４２５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついでその上面にネガ型マスクを張り合わせ、紫外線で露光し、回路を焼付け、１質量％の炭酸ナトリウム水溶液で現像し、エッチングレジストを形成し、そのエッチングレジストのない銅箔４０部分をスプレー噴霧によって、塩化第二銅、塩酸、硫酸過水の組成からなる塩化第二銅エッチング液で圧力０．２ＭＰａ、速度３．５ｍ／分の条件で行い、さらに３質量％水酸化ナトリウム水溶液を噴霧してエッチングレジストを剥離除去して、ベース材ａ２８の表裏に回路を形成した。 Next, on the surface of the copper foil 40 of the base material a28, an ultraviolet curable etching resist dry film H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under the condition of 5 m / min, and then a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed. 40 parts of the copper foil without slag were sprayed and sprayed with a cupric chloride etching solution comprising a composition of cupric chloride, hydrochloric acid and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa, speed 3.5 m / min, and 3 The etching resist was peeled and removed by spraying a mass% sodium hydroxide aqueous solution to form circuits on the front and back of the base material a28.
　次にベース材ｂ２９、ベース材ｃ３０として、厚さ０．０６ｍｍのエポキシ樹脂ガラスクロス布プリプレグであるＧＥＡ－６７９ＮＵＪＹ（日立化成工業株式会社製、商品名）を準備した。また、銅箔４０として、厚さ１２μｍの銅箔である３ＥＣ－ＶＬＰ－１２（三井金属鉱業株式会社製、商品名）を準備した。これらのエポキシ樹脂ガラスクロス布プリプレグを、先に準備したベース材ａ２８の両面の回路上に重ね合わせ、さらに、厚さ１２μｍの銅箔４０をその上に重ね合わせ、真空プレスを用いて、圧力３ＭＰａ、温度１７５℃、保持時間１．５時間の条件で加圧加熱して積層一体化した。このように、ベース材ａ２８の一方の面にベース材ｂ２９と銅箔４０を、他方の面にベース材ｃ３０と銅箔４０を積層一体化することにより、ベース材２１を作製した。 Next, as the base material b29 and the base material c30, GEA-679NUJY (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an epoxy resin glass cloth cloth prepreg having a thickness of 0.06 mm, was prepared. Further, 3EC-VLP-12 (trade name, manufactured by Mitsui Metal Mining Co., Ltd.), which is a copper foil having a thickness of 12 μm, was prepared as the copper foil 40. These epoxy resin glass cloth cloth prepregs are superposed on the circuits on both sides of the base material a28 prepared in advance, and a copper foil 40 having a thickness of 12 μm is superposed thereon, and a pressure of 3 MPa is applied using a vacuum press. The layers were integrated by pressurization under the conditions of a temperature of 175 ° C. and a holding time of 1.5 hours. Thus, the base material 21 was produced by laminating and integrating the base material b29 and the copper foil 40 on one surface of the base material a28 and the base material c30 and the copper foil 40 on the other surface.
　次に、ベース材２１の銅箔４０表面に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４２５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついでその上面にネガ型マスクを張り合わせ、紫外線で露光し、回路を焼付け、１質量％の炭酸ナトリウム水溶液で現像し、エッチングレジストを形成し、そのエッチングレジストのない銅部分をスプレー噴霧によって、塩化第二銅、塩酸、硫酸過水の組成からなる塩化第二銅エッチング液で圧力０．２ＭＰａ、速度３．５ｍ／分の条件で行い、さらに３質量％水酸化ナトリウム水溶液を噴霧してエッチングレジスト剥離除去して、コンフォーマルマスク２２を形成した。 Next, on the surface of the copper foil 40 of the base material 21, a UV-curable etching resist dry film H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under the condition of 5 m / min, and then a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed. The copper part with no copper is spray-sprayed with a cupric chloride etching solution composed of cupric chloride, hydrochloric acid, and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa, speed 3.5 m / min, and further 3% by mass A conformal mask 22 was formed by spraying an aqueous solution of sodium hydroxide to remove and remove the etching resist.
　次に、ベース材２１に、ＮＣレーザ加工機ＭＡＲＫ－２０（日立精工株式会社製、商品名）を用いて、アパチャー径φ０．２６、出力５００Ｗ、パルス幅１５μｓ、ショット数１５の条件で加工しレーザ孔２６を形成し、ついで、このレーザ孔２６のデスミア処理を過マンガン酸ナトリウム水溶液に温度８５℃で６分間の条件で行い、無電解銅めっきであるＣＵＳＴ２０１（日立化成工業株式会社製、商品名）、硫酸銅１０ｇ／Ｌ、ＥＤＴＡ４０ｇ／Ｌ、ホルマリン１０ｍｌ／Ｌ、ｐＨ１２．２）に温度２４℃、時間３０分の条件で、レーザ孔２６内を含むベース材２１の全面に０．５μｍの下地銅めっきを行った。 Next, the base material 21 was processed using an NC laser processing machine MARK-20 (trade name, manufactured by Hitachi Seiko Co., Ltd.) under the conditions of an aperture diameter of 0.26, an output of 500 W, a pulse width of 15 μs, and a shot number of 15. A laser hole 26 is formed, and then desmearing of the laser hole 26 is performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes, and CUST201 (product of Hitachi Chemical Co., Ltd., product) Name), copper sulfate 10 g / L, EDTA 40 g / L, formalin 10 ml / L, pH 12.2) at a temperature of 24 ° C. for 30 minutes, 0.5 μm on the entire surface of the base material 21 including the inside of the laser hole 26. Underlying copper plating was performed.
　次に、硫酸銅めっきで温度３０℃、電流密度１．５Ａ／ｄｍ２、時間６０分の条件で、レーザ孔２６内を含むベース材ｂ２９、ベース材ｃ３０の全面に、めっき厚２０μｍの電気銅めっきを形成した。 Next, electrolytic copper having a plating thickness of 20 μm is formed on the entire surface of the base material b29 and the base material c30 including the inside of the laser hole 26 under conditions of copper sulfate plating at a temperature of 30 ° C., a current density of 1.5 A / dm 2 , and a time of 60 minutes. A plating was formed.
　次に、ベース材２１の電気銅めっき表面に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４７５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついでその上面にネガ型マスクを張り合わせ、紫外線で露光し、回路を焼付け、１質量％の炭酸ナトリウム水溶液で現像し、エッチングレジストを形成し、そのエッチングレジストのない銅部分をスプレー噴霧によって、塩化第二銅、塩酸、硫酸過水の組成からなる塩化第二銅エッチング液で圧力０．２ＭＰａ、速度３．５ｍ／分の条件で、回路形成し、ついで３質量％水酸化ナトリウム水溶液を噴霧してエッチングレジスト剥離除去を行った。これにより、接続パッド１１、接続端子Ｂ１５等を含む回路を形成した。このときの接続端子Ｂ１５の径はφ０．３ｍｍ、ピッチは０．５ｍｍであった。 Next, a dry film H-W475 (trade name, manufactured by Hitachi Chemical Co., Ltd.) for ultraviolet curable etching resist is applied to the surface of the base material 21 on the electrolytic copper plating with a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1 Temporarily press-bonded under the condition of 5 m / min, and then a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, and an etching resist is formed. A circuit is formed by spray spraying a copper part having no pressure with a cupric chloride etching solution comprising a composition of cupric chloride, hydrochloric acid, and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa and speed 3.5 m / min. Etching resist was removed by spraying with a 3% by mass aqueous sodium hydroxide solution. Thereby, a circuit including the connection pad 11, the connection terminal B15, and the like was formed. At this time, the connection terminal B15 had a diameter of 0.3 mm and a pitch of 0.5 mm.
　次に、回路形成を行ったベース材２１の表面に、液状レジストであるＰＳＲ－４０００（太陽インキ製造株式会社製、商品名）を印刷し、８０℃、２０分間乾燥後、その上面にネガ型マスクを張合わせ、紫外線で露光し、さらに１．５質量％炭酸ナトリウム水溶液で現像し、紫外線１Ｊ／ｃｍ２の照射によりさらなる硬化を行い、１５０℃で６０分乾燥後、感光性樹脂層１０としてのソルダーレジスト２３を形成し、ベース層６を作製した。なお、このソルダーレジスト２３（感光性樹脂層１０）の形成は、ベース材２１の接続パッド１１を形成した面側のみに形成し、他方の面には形成しなかった。 Next, PSR-4000 (trade name, manufactured by Taiyo Ink Mfg. Co., Ltd.), which is a liquid resist, is printed on the surface of the base material 21 on which the circuit has been formed, dried at 80 ° C. for 20 minutes, and then the negative type on the upper surface. A mask is laminated, exposed with ultraviolet light, further developed with a 1.5% by mass aqueous sodium carbonate solution, further cured by irradiation with ultraviolet light 1 J / cm 2 , dried at 150 ° C. for 60 minutes, and then as photosensitive resin layer 10. The solder resist 23 was formed, and the base layer 6 was produced. The solder resist 23 (photosensitive resin layer 10) was formed only on the side of the base material 21 on which the connection pads 11 were formed, and not on the other side.
［半導体素子搭載用パッケージ基板の作製］
　次に、図５に示すように、キャビティ層５の接着剤８を仮付けした面と、ベース層６の感光性樹脂層１０（ソルダーレジスト２３）を形成した面が向き合うように重ね合わせ、真空プレスを用いて、圧力３ＭＰａ、温度１７５℃、保持時間１．５時間の条件で加圧加熱して積層一体化し、半導体素子搭載用パッケージ基板１とした。このとき、キャビティ層５に設けられた貫通孔Ａ２４が、ベース層６に設けられた接続パッド１１によって塞がれるように積層され、接続パッド１１を底面とした有底ビア１３が、キャビティ層５に形成される。 [Fabrication of package substrate for mounting semiconductor elements]
Next, as shown in FIG. 5, the surface of the cavity layer 5 on which the adhesive 8 is temporarily attached and the surface of the base layer 6 on which the photosensitive resin layer 10 (solder resist 23) is formed face each other, and the vacuum is applied. Using a press, pressure was heated under the conditions of 3 MPa, temperature of 175 ° C., and holding time of 1.5 hours to laminate and integrate to obtain a package substrate 1 for mounting a semiconductor element. At this time, the through-hole A24 provided in the cavity layer 5 is laminated so as to be blocked by the connection pad 11 provided in the base layer 6, and the bottomed via 13 having the connection pad 11 as a bottom surface is formed in the cavity layer 5. Formed.
　次に、この有底ビア１３内に、ベース材２１のときと同様にして、有底ビア１３内のデスミア処理を行い、有底ビア１３内を含む半導体素子搭載用パッケージ基板１の全面に０．５μｍの下地銅めっきを行った。 Next, in the bottomed via 13, the desmear process in the bottomed via 13 is performed in the same manner as the base material 21, and the entire surface of the package substrate 1 for mounting semiconductor elements including the inside of the bottomed via 13 is zeroed. The base copper plating of 5 μm was performed.
　次に、下地銅めっき表面に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４７５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついで、その上面にネガ型マスクを張り合わせ、紫外線で露光し、めっき不要の部分（キャビティ部９内及びベース層６の接続端子Ｂ１５を有する面）にめっきレジスト４３を形成した。なお、キャビティ部９は、電気銅めっきされないように、めっきレジスト４３で完全に被覆した。次に、硫酸銅めっきで温度３０℃、電流密度１．５Ａ／ｄｍ２、時間６０分の条件で、めっき厚２０μｍの電気銅めっき４１により金属被覆１８を形成し、ついで、３質量％水酸化ナトリウム水溶液を噴霧してめっきレジスト４３の剥離除去を行った。 Next, dry film H-W475 (trade name, manufactured by Hitachi Chemical Co., Ltd.) for UV curable etching resist is applied to the surface of the base copper plating with a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1.5 m / min. Then, a negative mask is attached to the upper surface and exposed with ultraviolet rays, and a plating resist 43 is formed on the portion that does not require plating (the surface having the connection terminal B15 of the cavity layer 9 and the base layer 6). did. The cavity portion 9 was completely covered with the plating resist 43 so as not to be electroplated with copper. Next, a metal coating 18 is formed by electrolytic copper plating 41 with a plating thickness of 20 μm under conditions of copper sulfate plating at a temperature of 30 ° C., a current density of 1.5 A / dm 2 , and a time of 60 minutes, and then 3% by mass of hydroxide The plating resist 43 was removed by spraying with an aqueous sodium solution.
　次に、硫酸過水エッチング組成からなるコブラエッチ（荏原ユージライト株式会社製、商品名）を用いて、キャビティ部９内に析出した下地銅めっき（図示しない。）を、温度５０℃、スプレー圧力０．２ＭＰａ、速度１．０ｍ／分の条件でエッチングし、ついで、過マンガン酸ナトリウム水溶液、温度８５℃で１５分間の条件で触媒の除去を行った。 Next, using a Cobra etch (trade name, manufactured by Sugawara Eugene Corporation) having a sulfuric acid / hydrogen peroxide etching composition, a base copper plating (not shown) deposited in the cavity portion 9 is applied at a temperature of 50 ° C. and a spray pressure. Etching was performed under the conditions of 0.2 MPa and a speed of 1.0 m / min, and then the catalyst was removed under the conditions of a sodium permanganate aqueous solution at a temperature of 85 ° C. for 15 minutes.
　次に、半導体素子搭載用パッケージ基板１の有底ビア１３（穴径φ約０．２ｍｍ、深さ約０．２５ｍｍ）内に、導電樹脂１７としてＡＥ１２４４（タツタ電線株式会社製、商品名）をスクリーン印刷法で充填した。スクリーン印刷には、有底ビア１３内への気泡の残留をなくすため、真空印刷装置ＶＥ５００（東レエンジアリング株式会社製　商品名）を用いた。充填した導電樹脂１７を完全硬化するため、半導体素子搭載用パッケージ基板１全体を１１０℃で１５分加熱し、さらに１７０℃で６０分加熱した。このとき、導電樹脂１７は、有底ビア１３の入り口のランドパターンよりも飛び出した状態であった。 Next, AE1244 (trade name, manufactured by Tatsuta Electric Co., Ltd.) is formed as the conductive resin 17 in the bottomed via 13 (hole diameter φ: about 0.2 mm, depth: about 0.25 mm) of the package substrate 1 for mounting the semiconductor element. Filled by screen printing. For screen printing, a vacuum printing apparatus VE500 (trade name, manufactured by Toray Engineering Co., Ltd.) was used in order to eliminate bubbles remaining in the bottomed via 13. In order to completely cure the filled conductive resin 17, the entire semiconductor device mounting package substrate 1 was heated at 110 ° C. for 15 minutes, and further heated at 170 ° C. for 60 minutes. At this time, the conductive resin 17 protruded from the land pattern at the entrance of the bottomed via 13.
　次に、バフ研磨機（株式会社石井表記製）を使用し、有低ビア１３の入り口の電気銅めっき４１の表面が露出し、導電樹脂１７と電気銅めっき４１が平滑になるまで研磨した。使用したバフロールの番手は、６００番、８００番、１０００番を組み合わせて使用した。バフロールとしては、穴埋め樹脂研磨用のＪＰバフモンスターＶ３／Ｖ３－Ｄ２（ジャブロ工業製　商品名）を使用した。また、研磨電流は１．２Ａであった。 Next, using a buffing machine (manufactured by Ishii Co., Ltd.), the surface of the electrolytic copper plating 41 at the entrance of the low via 13 was exposed and polished until the conductive resin 17 and the electrolytic copper plating 41 became smooth. The number of bafrole used was a combination of 600, 800 and 1000. As the baffle, JP buff monster V3 / V3-D2 (trade name, manufactured by Jablo Industries) for hole filling resin polishing was used. The polishing current was 1.2A.
　次に、電気銅めっき４１表面に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４７５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついで、その上面にネガ型マスクを張り合わせ、紫外線で露光し、めっき不要の部分にめっきレジスト４３を形成した。なお、キャビティ部９内のワイヤボンド端子１２や接続端子Ｂ１５は、めっきされるようにするため、めっきレジスト４３では被覆しなかった。 Next, a dry film H-W475 (trade name, manufactured by Hitachi Chemical Co., Ltd.) for ultraviolet curable etching resist is applied to the surface of the electrolytic copper plating 41 with a laminator, pressure 0.2 MPa, temperature 110 ° C., speed 1.5 m / Then, a negative mask was attached to the upper surface and exposed with ultraviolet rays, and a plating resist 43 was formed on a portion that does not require plating. Note that the wire bond terminal 12 and the connection terminal B15 in the cavity portion 9 were not covered with the plating resist 43 in order to be plated.
　次に、研磨後の導電樹脂１７上に触媒を付与したり、デスミア処理を行うことなく、直接無電解めっきによって金属皮膜１６を形成した（導電樹脂１７以外の部分は、図示を省略した。）。具体的には、一般的に無電解めっきの前処理で行われる脱脂やソフトエッチグ、酸洗浄を行った後、無電解ニッケルめっき液ＮｉＰＳ１００（日立化成工業株式会社製、商品名）を用いて、液温度８５℃で、時間１７分、２１分、２５分の各条件で、浸漬処理を行って、それぞれニッケルめっきを４μｍ、５μｍ、６μｍ析出させ、さらに、置換金めっき液ＨＧＳ－５００（日立化成工業株式会社製、商品名）に液温８０℃で、時間１０分の条件で浸漬処理し、還元型の無電解金めっき液であるＨＧＳ－２０００（日立化成工業株式会社製、商品名）に、液温６５℃で、時間２０分の条件で、金めっきを０．５μｍの厚みに析出させた。これにより、半導体素子搭載用パッケージ基板１の一方の面に設けられた接続端子Ａ１４、他方の面に設けられた接続端子Ｂ１５及びキャビティ部９内のワイヤボンド端子１２（接続端子Ｃ２７を有する場合は接続端子Ｃ２７を含む。）の表面に、はんだボール接続やワイヤボンド接続のためのニッケル・金めっき層を形成した。なお、このように導電樹脂１７上に金属皮膜１６を形成するのと同時に、キャビティ部９内に露出したベース層６上のワイヤボンド端子１２となる電気銅めっき４１上、および接続端子Ｂ１５上にも、導電樹脂１７上と同様に、ニッケルめっきと金めっきを行なった（図示しない。）。 Next, the metal film 16 was formed by direct electroless plating without applying a catalyst or performing desmearing on the polished conductive resin 17 (the portions other than the conductive resin 17 are not shown). . Specifically, after degreasing, soft etching, and acid cleaning that are generally performed in the pretreatment of electroless plating, an electroless nickel plating solution NiPS100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is used. Then, immersion treatment was performed at a liquid temperature of 85 ° C. under conditions of 17 minutes, 21 minutes, and 25 minutes to deposit nickel plating of 4 μm, 5 μm, and 6 μm, respectively. Further, substitution gold plating solution HGS-500 (Hitachi) HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced electroless gold plating solution that is immersed in a chemical temperature of 80 ° C. for 10 minutes at a liquid temperature. In addition, gold plating was deposited to a thickness of 0.5 μm at a liquid temperature of 65 ° C. for 20 minutes. Thereby, the connection terminal A14 provided on one surface of the package substrate 1 for mounting a semiconductor element, the connection terminal B15 provided on the other surface, and the wire bond terminal 12 in the cavity portion 9 (in the case of having the connection terminal C27). A nickel / gold plating layer for solder ball connection or wire bond connection was formed on the surface of the connection terminal C27). In addition, at the same time when the metal film 16 is formed on the conductive resin 17 in this way, on the copper electroplating 41 that becomes the wire bond terminal 12 on the base layer 6 exposed in the cavity portion 9 and on the connection terminal B15. As with the conductive resin 17, nickel plating and gold plating were performed (not shown).
　次に、紫外線硬化型エッチングレジスト用ドライフィルムＨ－Ｗ４７５（日立化成工業株式会社製、商品名）をラミネータで、圧力０．２ＭＰａ、温度１１０℃、速度１．５ｍ／分の条件で仮圧着し、ついでその上面にネガ型マスクを張り合わせ、紫外線で露光し、回路を焼付け、１質量％の炭酸ナトリウム水溶液で現像し、エッチングレジストを形成し、そのエッチングレジストのない銅部分をスプレー噴霧によって、塩化第二銅、塩酸、硫酸過水の組成からなる塩化第二銅エッチング液で圧力０．２ＭＰａ、速度３．５ｍ／分の条件で、回路形成し、ついで３質量％水酸化ナトリウム水溶液を噴霧してエッチングレジスト剥離除去を行った。これにより、接続端子Ａ１４を含む回路を形成した。このキャビティ層５の接続端子Ａ１４の径は０．２５ｍｍ、ピッチは０．４ｍｍであり、ベース層６の接続端子Ｂ１５の径０．３ｍｍ、ピッチ０．５ｍｍよりも小さい。 Next, a UV-curable etching resist dry film H-W475 (manufactured by Hitachi Chemical Co., Ltd., trade name) is temporarily bonded with a laminator under conditions of a pressure of 0.2 MPa, a temperature of 110 ° C., and a speed of 1.5 m / min. Then, a negative mask is laminated on the upper surface, exposed with ultraviolet rays, the circuit is baked, developed with a 1% by mass sodium carbonate aqueous solution, an etching resist is formed, and the copper portion without the etching resist is sprayed by spray spraying. A circuit was formed with a cupric chloride etching solution having a composition of cupric, hydrochloric acid, and sulfuric acid / hydrogen peroxide under the conditions of pressure 0.2 MPa, speed 3.5 m / min, and then sprayed with a 3 mass% sodium hydroxide aqueous solution. Then, the etching resist was removed. Thereby, a circuit including the connection terminal A14 was formed. The diameter of the connection terminal A14 of the cavity layer 5 is 0.25 mm and the pitch is 0.4 mm, which is smaller than the diameter of the connection terminal B15 of the base layer 6 of 0.3 mm and the pitch of 0.5 mm.
　次に、半導体素子搭載用パッケージ基板１の両面に、液状レジストであるＰＳＲ－４０００（太陽インキ製造株式会社製、商品名）を印刷し、８０℃、２０分間乾燥後、その上面にネガ型マスクを張合わせ、紫外線で露光し、さらに１．５質量％炭酸ナトリウム水溶液で現像し、紫外線１Ｊ／ｃｍ２の照射によりさらなる硬化を行い、１５０℃で６０分乾燥してソルダーレジスト２３を形成した。このソルダーレジスト２３は、キャビティ層５表面側（上面側）においては、接続端子Ａ１４と同等の高さであり、ベース層６の表面側（下面側）においては、接続端子Ｂ１５と同等の高さであった。 Next, PSR-4000 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.), which is a liquid resist, is printed on both surfaces of the package substrate 1 for mounting semiconductor elements, dried at 80 ° C. for 20 minutes, and then a negative mask is formed on the upper surface. Were exposed to ultraviolet light, developed with a 1.5% by weight aqueous sodium carbonate solution, further cured by irradiation with ultraviolet light 1 J / cm 2 , and dried at 150 ° C. for 60 minutes to form a solder resist 23. The solder resist 23 has a height equivalent to that of the connection terminal A14 on the surface side (upper surface side) of the cavity layer 5, and a height equivalent to that of the connection terminal B15 on the surface side (lower surface side) of the base layer 6. Met.
［半導体パッケージの作製］
　次に、図５に示すように、半導体素子２を、半導体素子搭載用パッケージ基板１のキャビティ部９内に、ダイボンディングフィルム(図示しない。）を用いて固定した後、この半導体素子２の上に、もう一つの半導体素子２をダイボンドフィルムを用いて固定した。その後、上段及び下段の半導体素子２と半導体素子搭載用パッケージ基板１のワイヤボンド端子１２とをボンディングワイヤ４で接続した。このとき、ボンディングワイヤ４を含む上段の半導体素子２の最上部は、半導体素子搭載用パッケージ基板１の接続端子Ａ１４と同等以下の高さであった。 [Fabrication of semiconductor packages]
Next, as shown in FIG. 5, the semiconductor element 2 is fixed in the cavity portion 9 of the semiconductor element mounting package substrate 1 using a die bonding film (not shown), and then the semiconductor element 2 is placed on the semiconductor element 2. In addition, another semiconductor element 2 was fixed using a die bond film. Thereafter, the upper and lower semiconductor elements 2 were connected to the wire bond terminals 12 of the semiconductor element mounting package substrate 1 by bonding wires 4. At this time, the uppermost portion of the upper semiconductor element 2 including the bonding wires 4 had a height equal to or lower than the connection terminal A14 of the semiconductor element mounting package substrate 1.
　次に、トランスファーモールドにより、キャビティ部９内に封止剤３を充填して成形し、半導体パッケージ３６を作製した。このとき、封止剤３の最上部は、半導体素子搭載用パッケージ基板１の接続端子Ａ１４と同等以下の高さ（接続端子Ａ１４よりも約０．１ｍｍ上方に飛び出す程度）であった。 Next, the sealing agent 3 was filled in the cavity portion 9 and formed by transfer molding to produce a semiconductor package 36. At this time, the uppermost part of the sealing agent 3 had a height equal to or lower than that of the connection terminal A14 of the semiconductor element mounting package substrate 1 (about to protrude about 0.1 mm above the connection terminal A14).
［ＰｏＰの作製］
　次に、接続端子Ａ１４にはんだペーストを印刷し、図６に示すように、上記実施例の半導体パッケージ３６をボトムパッケージ３５として使用し、トップパッケージ３４の接続端子と位置合わせした後、リフローによって半導体パッケージ同士を接合した。このとき、半導体素子搭載用パッケージ基板１のキャビティ部９内に封止剤３のほぼ全体が収納され、ほとんど飛び出していないので、半導体パッケージ同士の接合のためのはんだボール径は、封止剤３の高さを考慮する必要がない。このため、はんだボール径はφ０．３ｍｍ以下で接合が可能であった。この結果、ボトムパッケージ３５の封止剤３の最上部が、接続端子Ａ１４の上に設けられたはんだボール（φ０．３ｍｍ）の１／３以下の高さとなる状態で（即ち端子間距離４４の１／３以下の高さである０．１ｍｍ以下で）、トップパッケージ３４と接合することが可能であった。 [Production of PoP]
Next, a solder paste is printed on the connection terminal A14. As shown in FIG. 6, the semiconductor package 36 of the above embodiment is used as the bottom package 35. After aligning with the connection terminal of the top package 34, the semiconductor is reflowed. The packages were joined together. At this time, since almost all of the sealing agent 3 is accommodated in the cavity portion 9 of the semiconductor device mounting package substrate 1 and hardly protrudes, the solder ball diameter for joining the semiconductor packages is set to 3. There is no need to consider the height. For this reason, it was possible to join the solder balls with a diameter of φ0.3 mm or less. As a result, the uppermost portion of the sealant 3 of the bottom package 35 is in a state where the height is 1/3 or less of the solder ball (φ0.3 mm) provided on the connection terminal A14 (that is, the inter-terminal distance of 44). It was possible to join the top package 34 with a height of 1/3 or less (0.1 mm or less).
（実施例２）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作製した。 (Example 2)
[Cavity layer fabrication]
A cavity material was produced in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　導電樹脂１７を有底ビア１３内に充填・硬化した後、６００番の研磨布を装着したベルトサンダー研磨機（株式会社菊川鉄工所製　商品名Ｔ２６ＭＷ型）により、有低ビア１３の入り口の電気銅めっき４１の表面が露出し、導電樹脂１７と銅めっき４１が平滑になるまで研磨した。これ以外は、実施例１と同様にして作製した。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
After the conductive resin 17 is filled and cured in the bottomed via 13, the electric power at the entrance of the low via 13 is obtained by a belt sander polishing machine (product name: T26MW type manufactured by Kikukawa Iron Works Co., Ltd.) equipped with a 600th polishing cloth. Polishing was performed until the surface of the copper plating 41 was exposed and the conductive resin 17 and the copper plating 41 became smooth. Except this, it was produced in the same manner as in Example 1.
（実施例３）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作製した。 (Example 3)
[Cavity layer fabrication]
A cavity material was produced in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　実施例１と同様にして、導電樹脂１７を有底ビア１３内に充填・硬化し、バフ研磨機（株式会社石井表記製）を使用して、有低ビア１３の入り口の電気銅めっき４１の表面が露出し、導電樹脂１７と銅めっき４１が平滑になるまで研磨した。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
In the same manner as in Example 1, the conductive resin 17 is filled and cured in the bottomed via 13, and the electrolytic copper plating 41 at the entrance of the low via 13 is used by using a buffing machine (made by Ishii Corporation). Polishing was performed until the surface was exposed and the conductive resin 17 and the copper plating 41 became smooth.
　その後、研磨後の導電樹脂１７上に、デスミアを行なったり、触媒を付与して下地めっきを行なったりすることなく、導電樹脂１７中に含まれる導電成分の導電性を利用して給電することによって、電気ニッケルめっきを行ない、直接、導電成分上に金属皮膜１５を形成した。具体的には、電気ニッケルめっき液を用いて、電気ニッケルめっきを４μｍ、１０μｍ、１６μｍのそれぞれの厚みに析出させ、さらに、電気金めっきを用いて、金めっきを０．５μｍの厚みに析出させた。これにより、半導体素子搭載用パッケージ基板１の一方の面に設けられた接続端子Ａ１４、他方の面に設けられた接続端子Ｂ１５及びキャビティ部９内のワイヤボンド端子１２（接続端子Ｃ２７を有する場合は接続端子Ｃ２７を含む。）の表面に、はんだボール接続やワイヤボンド接続のためのニッケル・金めっき層を形成した。これ以外は、実施例１と同様にして、半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージを作製した。 Thereafter, power is supplied to the ground conductive resin 17 by utilizing the conductivity of the conductive component contained in the conductive resin 17 without performing desmearing or applying a catalyst to perform base plating. Then, nickel electroplating was performed to form a metal film 15 directly on the conductive component. Specifically, using an electro nickel plating solution, electro nickel plating is deposited to a thickness of 4 μm, 10 μm, and 16 μm, and using gold electro plating, a gold plating is deposited to a thickness of 0.5 μm. It was. Thereby, the connection terminal A14 provided on one surface of the package substrate 1 for mounting a semiconductor element, the connection terminal B15 provided on the other surface, and the wire bond terminal 12 in the cavity portion 9 (in the case of having the connection terminal C27). A nickel / gold plating layer for solder ball connection or wire bond connection was formed on the surface of the connection terminal C27). Except for this, a semiconductor element mounting package substrate and a semiconductor element mounting package were produced in the same manner as in Example 1.
（実施例４）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作製した。 Example 4
[Cavity layer fabrication]
A cavity material was produced in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　導電樹脂１７を有底ビア１３内に充填・硬化した後、６００番の研磨布を装着したベルトサンダー研磨機（株式会社菊川鉄工所製　商品名Ｔ２６ＭＷ型）により、有低ビア１３の入り口の電気銅めっき４１の表面が露出し、導電樹脂１７と銅めっき４１が平滑になるまで研磨した。これ以外は、実施例３と同様にして作製した。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
After the conductive resin 17 is filled and cured in the bottomed via 13, the electric power at the entrance of the low via 13 is obtained by a belt sander polishing machine (product name: T26MW type manufactured by Kikukawa Iron Works Co., Ltd.) equipped with a 600th polishing cloth. Polishing was performed until the surface of the copper plating 41 was exposed and the conductive resin 17 and the copper plating 41 became smooth. Except this, it was produced in the same manner as in Example 3.
（参考例１）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作成した。 (Reference Example 1)
[Cavity layer fabrication]
A cavity material was prepared in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　ニッケルめっきを、時間４.２分、８．４分、１２．７分の各条件で、浸漬処理を行って、それぞれニッケルめっき１μｍ、２μｍ、３μｍ析出させたこと以外は、実施例１と同様にして作製した。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
Except that nickel plating was performed under conditions of time 4.2 minutes, 8.4 minutes, and 12.7 minutes to deposit nickel plating 1 μm, 2 μm, and 3 μm, respectively, the same as in Example 1. It was made.
（参考例２）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作成した。 (Reference Example 2)
[Cavity layer fabrication]
A cavity material was prepared in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　研磨後の導電樹脂１７上に、デスミアを行なったり、触媒を付与して下地めっきを行なったりすることなく、導電樹脂１７中に含まれる導電成分の導電性を利用して給電することによって、電気ニッケルめっきを行ない、直接、導電成分上に金属皮膜１５を形成した。具体的には、電気ニッケルめっきを１μｍ、２μｍ、３μｍのそれぞれの厚みに析出させ、さらに、電気金めっきを用いて、金めっきを０．５μｍの厚みに析出させた。これ以外は、実施例１と同様にして作製した。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
By supplying power using the conductivity of the conductive component contained in the conductive resin 17 without performing desmearing or applying a catalyst to the ground conductive resin 17 without applying a catalyst, Nickel plating was performed to form a metal film 15 directly on the conductive component. Specifically, electro nickel plating was deposited to a thickness of 1 μm, 2 μm, and 3 μm, and gold plating was further deposited to a thickness of 0.5 μm using electro gold plating. Except this, it was produced in the same manner as in Example 1.
（比較例１）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作成した。 (Comparative Example 1)
[Cavity layer fabrication]
A cavity material was prepared in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　導電樹脂１７を有底ビア１３内に充填・硬化し、バフ研磨した後の導電樹脂１７に、さらにデスミア処理を行ってから、無電解めっきによって金属皮膜１６を形成したこと以外は、実施例１と同様である。デスミア処理は、過マンガン酸ナトリウム水溶液に温度８５℃で６分間の条件で行った。デスミア後の半導体素子搭載用パッケージ基板を、光学顕微鏡で観察したところ、導電樹脂１７上では、導電樹脂１７の導電成分の周囲の樹脂成分がアタックされ、導電成分の脱落が見られた。また、キャビティ層５とベース層６の間の接着剤８や感光性樹脂層１０がアタックされ、窪んだり、光沢がなくなっているのがわかった。この後、導電樹脂１７上に触媒処理しないで無電解ニッケルめっきを目標厚み５μｍの条件で行ったところ、所々析出しない箇所が観察され、金属皮膜１６による被覆は十分ではなかった。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
Example 1 except that the conductive resin 17 is filled and cured in the bottomed via 13 and buffed, and the conductive resin 17 is further desmeared and then the metal film 16 is formed by electroless plating. It is the same. The desmear treatment was performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes. When the semiconductor element mounting package substrate after desmearing was observed with an optical microscope, the resin component around the conductive component of the conductive resin 17 was attacked on the conductive resin 17 and the conductive component was dropped. Further, it was found that the adhesive 8 and the photosensitive resin layer 10 between the cavity layer 5 and the base layer 6 were attacked to be depressed or lost gloss. Thereafter, electroless nickel plating was performed on the conductive resin 17 without subjecting it to a catalyst with a target thickness of 5 μm. As a result, spots where no precipitation occurred were observed, and the coating with the metal film 16 was not sufficient.
（比較例２）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作成した。 (Comparative Example 2)
[Cavity layer fabrication]
A cavity material was prepared in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　導電樹脂１７を有底ビア１３内に充填・硬化した後の導電樹脂１７に、バフ研磨をしないで、直接デスミア処理を行ってから、無電解めっきによって金属皮膜１６を形成したこと以外は、実施例１と同様である。デスミア処理は、過マンガン酸ナトリウム水溶液に温度８５℃で６分間の条件で行った。デスミア後の半導体素子搭載用パッケージ基板を、光学顕微鏡で観察したところ、キャビティ層５とベース層６の間の接着剤８や感光性樹脂層１０がアタックされ、窪んだり、光沢がなくなっているのがわかった。また、この後、触媒処理なしに導電樹脂１７上への無電解ニッケルめっきを目標厚み５μｍの条件で行ったが、ほとんど析出せず、金属皮膜１６は形成されなかった。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
Except that the conductive resin 17 after filling and curing the conductive resin 17 in the bottomed via 13 is subjected to desmear treatment directly without buffing, and then the metal film 16 is formed by electroless plating. Similar to Example 1. The desmear treatment was performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes. When the semiconductor element mounting package substrate after desmearing is observed with an optical microscope, the adhesive 8 and the photosensitive resin layer 10 between the cavity layer 5 and the base layer 6 are attacked and become dimpled or not glossy. I understood. Thereafter, electroless nickel plating on the conductive resin 17 was performed without a catalyst treatment under the condition of a target thickness of 5 μm, but almost no deposition occurred and the metal film 16 was not formed.
（比較例３）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作成した。 (Comparative Example 3)
[Cavity layer fabrication]
A cavity material was prepared in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　導電樹脂１７を有底ビア１３内に充填・硬化し、バフ研磨した後の導電樹脂１７に、さらにデスミア処理を行ってから、電気ニッケルめっきによって金属皮膜１６を形成したこと以外は、実施例１と同様である。デスミア処理は、過マンガン酸ナトリウム水溶液に温度８５℃で６分間の条件で行った。デスミア後の半導体素子搭載用パッケージ基板を、光学顕微鏡で観察したところ、導電樹脂１７上では、導電樹脂１７の導電成分の周囲の樹脂成分がアタックされ、導電成分の脱落が見られた。また、キャビティ層５とベース層６の間の接着剤８や感光性樹脂層１０がアタックされ、窪んだり、光沢がなくなっているのがわかった。この後、導電樹脂１７上に電気ニッケルめっきを目標厚み１０μｍの条件で行ったところ、所々析出しない箇所が観察され、金属皮膜１６による被覆は十分ではなかった。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
Example 1 except that the conductive resin 17 was filled and cured in the bottomed via 13 and buffed, and the conductive resin 17 was further desmeared and then the metal film 16 was formed by electro nickel plating. It is the same. The desmear treatment was performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes. When the semiconductor element mounting package substrate after desmearing was observed with an optical microscope, the resin component around the conductive component of the conductive resin 17 was attacked on the conductive resin 17 and the conductive component was dropped. Further, it was found that the adhesive 8 and the photosensitive resin layer 10 between the cavity layer 5 and the base layer 6 were attacked to be depressed or lost gloss. Then, when electro nickel plating was performed on the conductive resin 17 under the condition of a target thickness of 10 μm, portions where no precipitation occurred were observed, and the coating with the metal film 16 was not sufficient.
（比較例４）
［キャビティ層の作製］
　実施例１と同様にしてキャビティ材を作成した。 (Comparative Example 4)
[Cavity layer fabrication]
A cavity material was prepared in the same manner as in Example 1.
［ベース層の作製］
　実施例１と同様に作製した。 [Preparation of base layer]
It was produced in the same manner as in Example 1.
［半導体素子搭載用パッケージ基板及び半導体素子搭載用パッケージの作製］
　導電樹脂１７を有底ビア１３内に充填・硬化した後の導電樹脂１７に、バフ研磨をしないで、直接デスミア処理を行ってから、電気めっきによって金属皮膜１６を形成したこと以外は、実施例１と同様である。デスミア処理は、過マンガン酸ナトリウム水溶液に温度８５℃で６分間の条件で行った。デスミア後の半導体素子搭載用パッケージ基板を、光学顕微鏡で観察したところ、キャビティ層５とベース層６の間の接着剤８や感光性樹脂層１０がアタックされ、窪んだり、光沢がなくなっているのがわかった。また、この後、導電樹脂１７上への電気ニッケルめっきを目標厚み１０μｍの条件で行ったが、ほとんど析出せず、金属皮膜１６は形成されなかった。 [Production of semiconductor device mounting package substrate and semiconductor device mounting package]
Except that the conductive resin 17 after the conductive resin 17 is filled and cured in the bottomed via 13 is subjected to desmear treatment directly without buffing, and then the metal film 16 is formed by electroplating. Same as 1. The desmear treatment was performed on a sodium permanganate aqueous solution at a temperature of 85 ° C. for 6 minutes. When the semiconductor element mounting package substrate after desmearing is observed with an optical microscope, the adhesive 8 and the photosensitive resin layer 10 between the cavity layer 5 and the base layer 6 are attacked and become dimpled or not glossy. I understood. Thereafter, electro nickel plating on the conductive resin 17 was performed under the condition of a target thickness of 10 μm, but almost no precipitation occurred and the metal film 16 was not formed.
　各実施例及び比較例についての、有低ビア１３への導電樹脂１７の充填性や導電樹脂１７上への無電解めっき析出性や電気めっき析出性の判定、接続信頼性試験は、以下のように行った。 For each example and comparative example, the filling property of the conductive resin 17 into the low and low vias 13, the determination of the electroless plating deposition property and the electroplating deposition property on the conductive resin 17, and the connection reliability test are as follows. Went to.
［基板のダメージの判定］
　半導体素子搭載用パッケージ基板１の外観を、光学顕微鏡で観察し、デスミアによるダメージ（接着剤８への窪みの形成や感光性樹脂層１０の光沢の消失等）が認められた場合を不合格（×）とした。 [Determination of substrate damage]
The appearance of the package substrate 1 for mounting a semiconductor element is observed with an optical microscope, and it is rejected when damage due to desmear (formation of a depression in the adhesive 8 or loss of gloss of the photosensitive resin layer 10) is recognized ( X).
［被覆性（めっき析出性）の判定］
　無電解めっきや電気めっき後の導電樹脂１７の表面を光学顕微鏡で観察し、導電樹脂１７が完全に覆われているものを合格（○）とした。 [Determination of coverage (plating precipitation)]
The surface of the conductive resin 17 after electroless plating or electroplating was observed with an optical microscope, and a case in which the conductive resin 17 was completely covered was judged as acceptable (◯).
［接続信頼性試験］
　各実施例、参考例及び各比較例で作製した導体素子搭載用パッケージ基板１を使用して、－５５～１２５℃の冷熱サイクル試験（それぞれ１５分）を行い、１００サイクルごとに有底ビア１３の層間接続３１を通した接続抵抗を測定し、１０００サイクル後の接続不良の有無を確認した。接続抵抗が、初期値に比べて１０％以上増加したものを不合格（×）とした。 [Connection reliability test]
Using the conductive element mounting package substrate 1 produced in each example, reference example, and each comparative example, a thermal cycle test (15 minutes each) of −55 to 125 ° C. was performed, and a bottomed via 13 was formed every 100 cycles. The connection resistance through the interlayer connection 31 was measured, and the presence or absence of connection failure after 1000 cycles was confirmed. A case where the connection resistance increased by 10% or more compared to the initial value was regarded as rejected (x).
　表１にその結果を示す。実施例１、２、３、４では、半導体素子搭載用パッケージ基板１のダメージがなく、めっき析出性、接続信頼性ともに良好であった。ニッケルめっきの厚みを薄くした参考例１、２では、導電樹脂１７上の金属皮膜１６の被覆が十分ではなかった。バフ研磨に加えデスミアを行った比較例１、３は、導電樹脂１７がアタックされ、導電成分の脱落やニッケルめっきによる金属皮膜１６の被覆が十分ではなかった。また、基板の接着剤８や感光性樹脂層１０にダメージが観察された。バフ研磨なしでデスミアのみを行った比較例２、４は、触媒処理なしでは導電樹脂１７上に無電解めっきが析出せず、接続信頼性もＮＧであった。
Figure JPOXMLDOC01-appb-T000001
 Table 1 shows the results. In Examples 1, 2, 3, and 4, there was no damage to the package substrate 1 for mounting a semiconductor element, and both the plating deposition property and the connection reliability were good. In Reference Examples 1 and 2 in which the thickness of the nickel plating was reduced, the coating of the metal film 16 on the conductive resin 17 was not sufficient. In Comparative Examples 1 and 3 in which desmear was performed in addition to buffing, the conductive resin 17 was attacked, and the metal component 16 was not sufficiently covered by the removal of the conductive component or nickel plating. Further, damage was observed on the adhesive 8 and the photosensitive resin layer 10 of the substrate. In Comparative Examples 2 and 4 in which only desmear was performed without buffing, electroless plating did not deposit on the conductive resin 17 without catalyst treatment, and the connection reliability was NG.
Figure JPOXMLDOC01-appb-T000001
１…半導体素子搭載用パッケージ基板、２…半導体素子、３…封止剤、４…ボンディングワイヤ、５…キャビティ層、６…ベース層、7…キャビティ材、８…接着剤、９…キャビティ部、１０…感光性樹脂層、１１…接続パッド、１２…ワイヤボンド端子、１３…有底ビア、１４…接続端子Ａ、１５…接続端子Ｂ、１６…金属皮膜、１７…導電樹脂、１８…金属被覆、１９…内層回路、２０…内層接続、２１…ベース材、２２…コンフォーマルマスク、２３…ソルダーレジスト、２４…貫通孔Ａ、２５…開口、２６…レーザ孔、２７…接続端子Ｃ、２８…ベース材ａ、２９…ベース材ｂ、３０…ベース材ｃ、３１…層間接続、３２…トップ基板、３３…ボトム基板、３４…トップパッケージ、３５…ボトムパッケージ、３６…半導体パッケージ、３７…接続端子、３８…はんだボール、３９…貫通孔Ｂ、４０…銅箔、４１…めっき、４２…層間接続、４３…めっきレジスト、４４…端子間距離 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device mounting package substrate, 2 ... Semiconductor device, 3 ... Sealant, 4 ... Bonding wire, 5 ... Cavity layer, 6 ... Base layer, 7 ... Cavity material, 8 ... Adhesive, 9 ... Cavity part, DESCRIPTION OF SYMBOLS 10 ... Photosensitive resin layer, 11 ... Connection pad, 12 ... Wire bond terminal, 13 ... Bottomed via, 14 ... Connection terminal A, 15 ... Connection terminal B, 16 ... Metal film, 17 ... Conductive resin, 18 ... Metal coating , 19 ... inner layer circuit, 20 ... inner layer connection, 21 ... base material, 22 ... conformal mask, 23 ... solder resist, 24 ... through hole A, 25 ... opening, 26 ... laser hole, 27 ... connection terminal C, 28 ... Base material a, 29 ... Base material b, 30 ... Base material c, 31 ... Interlayer connection, 32 ... Top substrate, 33 ... Bottom substrate, 34 ... Top package, 35 ... Bottom package, 36 ... Semiconductor package , 37 ... connection terminals, 38 ... solder balls, 39 ... through holes B, 40 ... copper foil, 41 ... plating, 42 ... interlayer connection, 43 ... plating resist, 44 ... distance between terminals

Claims (7)

  1. 　開口及び貫通孔を有するキャビティ層と、このキャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板において、
    　前記有底ビアの内壁に金属被覆が形成され、これを下地として前記有底ビアに導電樹脂が充填され、
    　この導電樹脂中に含まれる導電成分が、露出した状態で前記有底ビアの入り口側に配置され、この露出した導電成分上に、めっきが直接析出することにより形成された金属皮膜を有する半導体素子搭載用パッケージ基板。     A package for mounting a semiconductor device, comprising: a cavity layer having an opening and a through hole; a base layer stacked on the cavity layer; a cavity formed by the opening; and a bottomed via formed by the through hole. In the substrate,
    A metal coating is formed on the inner wall of the bottomed via, and the bottomed via is filled with a conductive resin as a base,
    A semiconductor element having a metal film formed by placing a conductive component contained in the conductive resin on the entrance side of the bottomed via in an exposed state, and plating is directly deposited on the exposed conductive component. Package substrate for mounting.
  2. 　請求項１において、
    　ベース層上のキャビティ層側に設けられる接続パッドと、前記キャビティ層上のベース層と反対側に設けられ、前記接続パッドと有底ビアによって層間接続される接続端子Ａとを有し、
    　前記接続端子Ａが、前記有底ビアに充填された導電樹脂中に含まれる導電成分に、直接析出しためっきにより形成される金属皮膜を有する半導体素子搭載用パッケージ基板。     In claim 1,
    A connection pad provided on the cavity layer side on the base layer; and a connection terminal A provided on the opposite side of the base layer on the cavity layer and connected between the connection pad and a bottomed via.
    A package substrate for mounting a semiconductor element, wherein the connection terminal A has a metal film formed by plating directly deposited on a conductive component contained in a conductive resin filled in the bottomed via.
  3. 　請求項１または２において、
    　金属皮膜を形成するめっきが、物理的研磨によって有底ビアの入り口側に露出した導電樹脂の導電成分上に、直接析出した半導体素子搭載用パッケージ基板。     In claim 1 or 2,
    A package substrate for mounting a semiconductor element, in which a plating for forming a metal film is deposited directly on a conductive component of a conductive resin exposed to an entrance side of a bottomed via by physical polishing.
  4. 　請求項１から３の何れかにおいて、
    　金属皮膜を形成するめっきが、無電解ニッケルめっきまたは無電解金めっきまたは無電解ニッケルめっきと置換金めっきもしくは無電解金めっきを有する半導体素子搭載用パッケージ基板。     In any one of Claim 1 to 3,
    A package substrate for mounting a semiconductor element, wherein the plating for forming the metal film includes electroless nickel plating, electroless gold plating, electroless nickel plating and displacement gold plating or electroless gold plating.
  5. 　請求項１から３の何れかにおいて、
    　金属皮膜を形成するめっきが、電気ニッケルめっきまたは電気金めっきまたは電気ニッケルめっきと置換金めっきもしくは無電解金めっきもしくは電気金めっきを有する半導体素子搭載用パッケージ基板。     In any one of Claim 1 to 3,
    A package substrate for mounting a semiconductor element, wherein the plating for forming the metal film includes electro nickel plating, electro gold plating, electro nickel plating and displacement gold plating, electroless gold plating, or electro gold plating.
  6. 　請求項１から５の何れかにおいて、
    　導電樹脂中に含まれる導電成分が、銀めっき銅粉または金めっき銅粉である半導体素子搭載用パッケージ基板。     In any of claims 1 to 5,
    A package substrate for mounting a semiconductor element, wherein the conductive component contained in the conductive resin is silver-plated copper powder or gold-plated copper powder.
  7. 　開口及び貫通孔を有するキャビティ層と、このキャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板の製造方法において、
    　前記有底ビアの内壁に金属被覆が形成され、これを下地として前記有底ビアに導電樹脂が充填される工程と、
    　この導電樹脂表面を物理的に研磨して前記導電樹脂中の導電成分を露出させる工程と、
    　この導電成分上に無電解めっきまたは電気めっきを直接析出させる工程と、
    を有する半導体素子搭載用パッケージ基板の製造方法。     A package for mounting a semiconductor device, comprising: a cavity layer having an opening and a through hole; a base layer stacked on the cavity layer; a cavity formed by the opening; and a bottomed via formed by the through hole. In the method for manufacturing a substrate,
    A metal coating is formed on the inner wall of the bottomed via, and the bottomed via is filled with a conductive resin as a base, and
    A step of physically polishing the surface of the conductive resin to expose a conductive component in the conductive resin;
    Directly depositing electroless plating or electroplating on the conductive component;
    Manufacturing method of semiconductor device mounting package substrate having
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594386A (en) * 2012-08-17 2014-02-19 宏启胜精密电子(秦皇岛)有限公司 Laminated packaging composition and making method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014072325A (en) * 2012-09-28 2014-04-21 Hitachi Chemical Co Ltd Multilayer wiring board and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226456A (en) * 1993-04-23 1995-08-22 Nippon Micron Kk Ic package and its manufacturing method
JPH1065339A (en) * 1996-08-22 1998-03-06 Sony Corp Multilayer printed wiring board and method manufacturing therfor
JP2001068624A (en) * 1999-08-26 2001-03-16 Toshiba Corp Semiconductor device and its manufacture
JP2004265956A (en) * 2003-02-26 2004-09-24 Ibiden Co Ltd Multilayer printed wiring board
JP2008016819A (en) * 2006-07-06 2008-01-24 Samsung Electro-Mechanics Co Ltd Bottom substrate of package-on-package and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226456A (en) * 1993-04-23 1995-08-22 Nippon Micron Kk Ic package and its manufacturing method
JPH1065339A (en) * 1996-08-22 1998-03-06 Sony Corp Multilayer printed wiring board and method manufacturing therfor
JP2001068624A (en) * 1999-08-26 2001-03-16 Toshiba Corp Semiconductor device and its manufacture
JP2004265956A (en) * 2003-02-26 2004-09-24 Ibiden Co Ltd Multilayer printed wiring board
JP2008016819A (en) * 2006-07-06 2008-01-24 Samsung Electro-Mechanics Co Ltd Bottom substrate of package-on-package and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594386A (en) * 2012-08-17 2014-02-19 宏启胜精密电子(秦皇岛)有限公司 Laminated packaging composition and making method thereof

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