TW497236B - A soc packaging process - Google Patents
A soc packaging process Download PDFInfo
- Publication number
- TW497236B TW497236B TW90121249A TW90121249A TW497236B TW 497236 B TW497236 B TW 497236B TW 90121249 A TW90121249 A TW 90121249A TW 90121249 A TW90121249 A TW 90121249A TW 497236 B TW497236 B TW 497236B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- wafer
- patent application
- scope
- solvent
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
497236 五、發明說明(1) 【發明領域】 本發明係有關於一種SOC (Substrate-On-Chip)封裝 過程’特別係有關於一種S 0 C封裝過程中之黏晶步驟。 【先前技術】 所謂的「S0C封裝」即為Substrate-On-Chip封裝〔基 板在晶片上〕之簡稱,屬於一種常用之半導體封裝結構, 其係以一具有窗口之電路基板黏貼於一晶片,並以複數個 金屬焊線穿過該窗口連接電路基板與晶片,該電路基板並 形成有複數個矩陣排列之焊球,在美國專利案第 6, 1 90, 943號「晶片尺寸封裝方法」中揭示一種s〇c封裝結_ _ 構及其封裝方法,如第1圖所示,該s〇c封裝結構2〇係包含 有一基板22、一晶片24及複數個焊球44,該基板22係具有 一用以黏固晶片24之上表面30、一用以焊接焊球44之下表 面38以及貫穿上表面3〇與下表面38之通孔34,其中晶片 係以熱塑性黏著層28黏固於基板22之上表面3〇,由於基板 22之通孔34係裸露在晶片24之主動面26〔active surface〕中間之焊墊36,使得金屬焊線32可穿過通孔 34,以電性連接晶片24之焊墊36與基板22之導接墊ο,該 導接墊41係由在基板22下表面38之導電層4〇所構成,並在 通孔34處以及晶片24之周邊形成有封膠材42,其係為一種_ 絕緣性及熱固性之環氧樹脂矽氧填充材料。 在美國專利案第6, 1 90, 943號「晶片尺寸封裝方法」 中,關於上述S0C封裝結構2〇之封裝方法係如第2圖所示, 包含以下步驟:a)提供一基板22,在該基板22之上表面30
第4頁 497236 五、發明說明(2) 具有至少一黏晶區域3 0 2,其包含上述之通孔3 4 ; b )將液 悲之熱塑性黏者層2 8網版印刷〔s t e n c i 1 i n g〕於黏晶區域 302,c)黏貼晶片24至黏晶區域302,使得晶片24之主動面 26接觸熱塑性黏著層28,且在主動面26之焊墊36係位置對 應於通孔3 4,d)在預定之溫度、壓力及時間之下,施壓加 熱基板22與晶片24,e)以打線〔wire-bonding〕將金屬焊 線32經由通孔34連接基板22之導接墊41與晶片24之焊墊 36 ;f)提供一封膠材42於該通孔34及晶片24之周邊;g)在 基板2 2之下表面3 8接植複數個呈矩陣排列之焊球4 4。藉由 上述之步驟以製備S0C封裝結構20,其中在b)步驟中之熱丨 塑性黏著層2 8係為一種無溶劑、彈性且半透明之石夕橡膠 〔silicone rubber〕,由於未黏合前的熱塑性黏著層28 ^系呈液態,在d)步驟中的施壓加熱容易使得液態熱塑性黏 著層2 8溢流並覆蓋晶片2 4之焊墊3 6,而導致封裝失敗,故 這種soc封裝方法良率較低,此外,另一不便之處為在b) 步驟印刷上液態熱塑性黏著層28之後,無法將多個基板22 堆疊以供搬運或儲放,必須儘速黏固上晶片24,否則基板 2 2會受到污染以及基板2 2間會不當黏著,造成加工之 難。 【發明目的及概要】 本發明之主要目的在於提供一種s〇c封裝過程,利用 種兩階段特性〔two s tage〕具有溶劑之熱固性混合 物,以黏貼晶片,在印刷於基板及乾燥後在基板表面形成 一不具黏性之熱固性黏著乾膜,使得在加熱施壓時熱固性
第5頁 497236 五、發明說明(3) 黏著乾膜不易覆蓋晶片之焊墊,以增加s〇c封裝良率。 本發明之次一目的在於提供一種s〇c封裝過程, 特?广。stage〕具有溶… 黏貼曰曰片,在印刷於基板及乾燥後在基板表面形 具黏性^熱固性黏著乾膜,使得具有熱固性黏著乾膜之Z 板可堆璺搬運或儲放,有利於後續s〇C封裝之加工。、土 依本發明之SOC封裝過程,其第一步驟為提供一美 板上表面、一下表面及連通上下表面:通 在土板之上表面網版印刷一層兩階段特性 〔two stage〕具有溶劑之熱固性混合物;然後,去 劑,使熱固性混合物形成無溶劑之黏著乾膜;接 提 5 /|> ,一^ 曰 μ η , · ^ 日日曰,日日片具有一主動面及複數個在主動面之焊 你ir Ϊ I ί片ί主動面係接觸基板之上表面且晶片之焊塾 係位置對應於基板之通孔;爾後,施壓加熱基板與晶片, 使上述無溶劑之黏著乾膜固化並結合晶片與基板;之後, 經由通孔打線電性連接晶片之焊塾至基板;最後,形成一 於該基板之通孔處,如有需要,並接植複數個焊球 於基板之下表面,以構成soc封裝結構。 【發明詳細說明】 請參閱所附圖式,本發明將列舉以下之實施例說明:丨 依本發明之—具體實施例,S0C封裝過程之步驟詳述 如下: 一如第3圖所示,首先提供一基板110,該基板110具有 一上表面111、一下表面112及連通上下表面丨“、112之通
第6頁 497236 五、發明說明(4) 孔11 3,在本實施例中,基板11 0係為一種印刷電路板〔如 FR-4、FR-5或BT等玻璃纖維強化樹脂〕,在基板11〇之下 表面112形成有一電路圖案層〔circuit pattern〕〔圖未 繪出〕,如導接墊、焊球墊以及連接導接墊與焊球墊之金 屬線路;之後’在基板1 1 0之上表面111網版印刷上一層兩 階段特性〔two stage〕具有溶劑〔s〇ivent〕之熱固性混 合物130 C thermosetting mixture〕,該兩階段黏著之熱 固性混合物1 3 0係包含有熱固性樹脂,如聚亞醯胺 〔polyimide〕、聚喳啉〔p〇lyqUinolin〕或苯環丁烯 〔benzocyclobutene〕,以及能夠溶解上述熱固性樹脂之馨 溶劑,如丁内脂〔butyro lactone〕與環戊酮 〔cyclopentanone〕之混合溶劑或是1,3, 5 -三甲基苯 〔mesitylene〕,由該兩階段之熱固性混合物13〇在塗施 時係具有A階段〔A-stage〕之特性,其呈液態,使得易於 塗施附者’故除了網版印刷方法之外,更可以印刷 〔painting〕、喷塗〔spraying〕、旋塗〔spinning〕或 浸染〔dipping〕等方式形成於基板110之上表面m ;然 後’加熱基板11 0至一適當溫度〔約攝氏9 〇〜1 5 〇 °c〕,以 除去溶劑,使熱固性混合物1 3 〇形成無溶劑之黏著乾膜 1 31,較佳地,另執行一真空乾燥加熱,以完全去除溶 _ 劑’此時,在基板11 〇之黏著乾膜丨3 1係具有B階段 〔B-stage〕之特性,即在室溫下成為不具有黏性〔Tg ^ 4 0 °C〕之膠膜,可供堆疊搬運或儲放,有利於後續s〇(:制; 裝之加工;接著,提供至少一晶片i 2 〇,該晶片i 2 〇具有一
497236 五、發明說明(5) 主動面121〔active surface〕及複數個在主動面121之焊 墊122,其中晶片120之主動面121係接觸基板110之上表面 111且晶片120之焊墊122係位置對應於基板110之通孔 113,在本實施例中,焊墊122係位於晶片120主動面121之 中間部位;爾後,施壓加熱基板11 〇與晶片1 20,約在攝氏 1 8 0 °C並在適當壓力下維持數秒鐘之久,使得上述無溶劑 之黏著乾膜131固化〔curing〕並結合晶片120與基板 110,由於在熱黏合晶片120與基板1 1〇,黏著乾膜丨31並不 具有高流動性,不會有受擠壓流至晶片12〇之焊墊丨22的現 象,爾後,經由通孔11 3以金屬焊線1 4 Q打線電性連接晶片 120之焊墊122至基板11〇 ;最後,形成一熱固性封膠材15〇 於該基板11 0之通孔11 3處,在本實施例中,其係以壓模 〔mold ing〕方式形成該封膠材丨5〇,該封膠材丨5〇並密封 晶片1 2 0 ’如有需要,並接植複數個焊球丨6 〇於基板丨丨〇之 下表面120,並在切割分離後,構成複數個s〇(:封裝結構 100 ° 因此,本發明係運用兩階段特性〔tw〇 stage〕具有 溶劑之熱固性混合物130於S0C封裝過程中,作為基板11() 片120之黏合材料,避免了液態黏膠覆蓋晶片12〇之焊 # # β的缺失’以增加S〇C封裝良率,同時已形成熱固性黏_ 31之基板1 1〇可供堆疊搬運或儲放,有利於後續 soc封裝之加工。 附之申請專利範圍所界定 在不脫離本發明之精神和 故本發明之保護範圍當視後 者為準,任何熟知此項技藝者, 497236 五、發明說明(6) 範圍内所作之任何變化與修改,均屬於本發明之保護範 圍。 _ 1__1 第9頁 497236 圖式簡單說明 【圖式說明】 第1圖:在美國專利案第6,ig〇,943號「晶片尺寸封裝方 法」中,一SOC封裝結構之截面圖’ 第2圖:在美國專利案第6,i9〇,gw號「晶片尺寸封袭方 法」中,該SOC封裝結構之製造流程圖,及 第3圖:依本發明之一具體實施例,〆S 〇 C封裝方法之製 造流程圖。 【圖號說明】 20 SOC封裝結構 22 基板 24 晶 28 熱塑性黏著層 30 上 34 通孔 36 焊 40 導電層 41 導 44 焊球 片 26 主動面 表面 32 金屬焊線 墊 38 下表面 接墊 42 封膠材
1 00 SOC封裝結構 110基板 111 120 130 140 302 上表面 晶片 兩階段熱固 金屬焊線 黏晶區域 112下表面 1 2 1主動面 混合物 150封膠材 113通孔 1 2 2焊墊 1 31黏著乾膜 1 6 0焊球
Claims (1)
- 六、申請專利範圍 【申請專利範圍】 1、一種SOC封裝過程,其步驟為: 通:ΪΓ:基板,該基板具有—上表面、-下表面及連 通上下表面之通孔; b)在基板之上表面形成一層兩階段特性㈣ tage〕具有溶劑之熱固性混合物; 膜C;)去除溶劑’使熱固性混合物形成無溶劑之黏著乾 動H:i十:晶片晶片具有-主動面及複數個在主 曰片t煜中晶片之主動面係接觸基板之上表面且丨 曰曰片^知墊係位置對應於基板之通孔; 化2 = iff板與晶片,使上述無溶劑之黏著乾膜固 化並結合晶片與基板; f) 經由通孔打線電性連接晶片之焊塾至基板;及 g) 形成一封膠材於該基板之通孔處。 2、 如申請專利範圍第!項中所述之如 以網版印刷方法形成一層熱固性混合物。 -係 3、 =請專利範圍第!項中所述之聊 以印刷〔Painty〕、喷塗〔寧aying〕、旋私塗八係 ^p,nnlng. CdippingJ 封袭過程,其* 於基板之下表面。 任植後數個焊球 第11頁 六、申請專利範圍 5、如申請專利範圍第1 係以壓模方式形成該封膠材。 項中所述之SOC 封裝 過程, 其中 6、如申請專利範圍第5 該封膠材係密封晶片。 項中所述之SOC封裝過程,其令 :如申请專利範圍第!項中所述之s〇c封裝過程,其 係以加熱或真空乾燥方式去除溶劑。 /、 、如申請專利範圍第1項中所述之s〇C封裝過程,其中 在e)步驟之施壓加熱溫度係高於c)步驟之溫度。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90121249A TW497236B (en) | 2001-08-27 | 2001-08-27 | A soc packaging process |
US10/227,341 US6689638B2 (en) | 2001-08-27 | 2002-08-26 | Substrate-on-chip packaging process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90121249A TW497236B (en) | 2001-08-27 | 2001-08-27 | A soc packaging process |
Publications (1)
Publication Number | Publication Date |
---|---|
TW497236B true TW497236B (en) | 2002-08-01 |
Family
ID=21679180
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW90121249A TW497236B (en) | 2001-08-27 | 2001-08-27 | A soc packaging process |
Country Status (2)
Country | Link |
---|---|
US (1) | US6689638B2 (zh) |
TW (1) | TW497236B (zh) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI395297B (zh) * | 2005-06-29 | 2013-05-01 | Freescale Semiconductor Inc | 源極端注入儲存裝置以及用於其之方法 |
TWI395326B (zh) * | 2008-07-31 | 2013-05-01 | Toshiba Kk | 固態攝影裝置及其製造方法 |
TWI397132B (zh) * | 2005-07-29 | 2013-05-21 | Freescale Semiconductor Inc | 使用多晶粒面板之三維積體電路之製造 |
TWI399820B (zh) * | 2009-05-06 | 2013-06-21 | Au Optronics Corp | 電漿處理裝置及其絕緣蓋板 |
TWI399823B (zh) * | 2005-07-09 | 2013-06-21 | Tec Sem Ag | 用以存放基板之裝置 |
TWI402964B (zh) * | 2005-06-20 | 2013-07-21 | Univ Tohoku | 層間絕緣膜及配線構造與此等之製造方法 |
TWI470737B (zh) * | 2008-07-10 | 2015-01-21 | Taiwan Semiconductor Mfg Co Ltd | 積體電路結構 |
TWI482308B (zh) * | 2007-09-28 | 2015-04-21 | Samsung Electronics Co Ltd | 形成細微圖案之方法及製造使用該細微圖案的半導體發光裝置之方法 |
TWI490971B (zh) * | 2008-12-31 | 2015-07-01 | Archers Systems Usa Inc | 基板的處理系統、傳輸系統和傳輸方法以及橫向移動室 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6967123B2 (en) * | 2002-04-11 | 2005-11-22 | Agilent Technologies, Inc. | Adhesive die attachment method for a semiconductor die and arrangement for carrying out the method |
DE10240460A1 (de) * | 2002-08-29 | 2004-03-11 | Infineon Technologies Ag | Universelles Halbleitergehäuse mit vorvernetzten Kunststoffeinbettmassen und Verfahren zur Herstellung desselben |
TW582078B (en) * | 2002-11-29 | 2004-04-01 | Chipmos Technologies Bermuda | Packaging process for improving effective die-bonding area |
US6703075B1 (en) * | 2002-12-24 | 2004-03-09 | Chipmos Technologies (Bermuda) Ltd. | Wafer treating method for making adhesive dies |
US20040238925A1 (en) * | 2003-05-23 | 2004-12-02 | Paul Morganelli | Pre-applied thermoplastic reinforcement for electronic components |
US7332411B2 (en) * | 2004-08-12 | 2008-02-19 | Hewlett-Packard Development Company, Lp | Systems and methods for wafer bonding by localized induction heating |
US7400037B2 (en) * | 2004-12-30 | 2008-07-15 | Advanced Chip Engineering Tachnology Inc. | Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP |
US7446407B2 (en) * | 2005-08-31 | 2008-11-04 | Chipmos Technologies Inc. | Chip package structure |
US20070080435A1 (en) * | 2005-10-06 | 2007-04-12 | Chun-Hung Lin | Semiconductor packaging process and carrier for semiconductor package |
US7344917B2 (en) * | 2005-11-30 | 2008-03-18 | Freescale Semiconductor, Inc. | Method for packaging a semiconductor device |
TW200723495A (en) * | 2005-12-07 | 2007-06-16 | Chipmos Technologies Inc | Chip package structure |
CN100463157C (zh) * | 2006-07-10 | 2009-02-18 | 南茂科技股份有限公司 | 防止粘晶胶污染芯片焊垫的封装构造及其基板 |
TWI313050B (en) * | 2006-10-18 | 2009-08-01 | Advanced Semiconductor Eng | Semiconductor chip package manufacturing method and structure thereof |
CN101350335B (zh) * | 2007-07-19 | 2010-06-02 | 矽品精密工业股份有限公司 | 开窗型球栅阵列半导体封装件及其应用的网板结构 |
US8680674B2 (en) | 2012-05-31 | 2014-03-25 | Freescale Semiconductor, Inc. | Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices |
US9093429B2 (en) | 2012-06-27 | 2015-07-28 | Freescale Semiconductor, Inc. | Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices |
EP2873031B1 (en) * | 2012-07-12 | 2018-08-22 | Assa Abloy Ab | Method of manufacturing a functional inlay |
US8933433B2 (en) | 2012-07-30 | 2015-01-13 | LuxVue Technology Corporation | Method and structure for receiving a micro device |
US9484504B2 (en) | 2013-05-14 | 2016-11-01 | Apple Inc. | Micro LED with wavelength conversion layer |
US20160329173A1 (en) | 2013-06-12 | 2016-11-10 | Rohinni, LLC | Keyboard backlighting with deposited light-generating sources |
US9111464B2 (en) | 2013-06-18 | 2015-08-18 | LuxVue Technology Corporation | LED display with wavelength conversion layer |
JP6959697B2 (ja) | 2016-01-15 | 2021-11-05 | ロヒンニ リミテッド ライアビリティ カンパニー | 装置上のカバーを介してバックライトで照らす装置及び方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6046072A (en) * | 1993-03-29 | 2000-04-04 | Hitachi Chemical Company, Ltd. | Process for fabricating a crack resistant resin encapsulated semiconductor chip package |
JP3410202B2 (ja) * | 1993-04-28 | 2003-05-26 | 日本テキサス・インスツルメンツ株式会社 | ウェハ貼着用粘着シートおよびこれを用いた半導体装置の製造方法 |
US6281044B1 (en) * | 1995-07-31 | 2001-08-28 | Micron Technology, Inc. | Method and system for fabricating semiconductor components |
US6017776A (en) * | 1997-04-29 | 2000-01-25 | Micron Technology, Inc. | Method of attaching a leadframe to singulated semiconductor dice |
US5840598A (en) * | 1997-08-14 | 1998-11-24 | Micron Technology, Inc. | LOC semiconductor assembled with room temperature adhesive |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
US6534861B1 (en) * | 1999-11-15 | 2003-03-18 | Substrate Technologies Incorporated | Ball grid substrate for lead-on-chip semiconductor package |
US6190943B1 (en) | 2000-06-08 | 2001-02-20 | United Test Center Inc. | Chip scale packaging method |
-
2001
- 2001-08-27 TW TW90121249A patent/TW497236B/zh not_active IP Right Cessation
-
2002
- 2002-08-26 US US10/227,341 patent/US6689638B2/en not_active Expired - Lifetime
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI402964B (zh) * | 2005-06-20 | 2013-07-21 | Univ Tohoku | 層間絕緣膜及配線構造與此等之製造方法 |
TWI395297B (zh) * | 2005-06-29 | 2013-05-01 | Freescale Semiconductor Inc | 源極端注入儲存裝置以及用於其之方法 |
TWI399823B (zh) * | 2005-07-09 | 2013-06-21 | Tec Sem Ag | 用以存放基板之裝置 |
TWI397132B (zh) * | 2005-07-29 | 2013-05-21 | Freescale Semiconductor Inc | 使用多晶粒面板之三維積體電路之製造 |
TWI482308B (zh) * | 2007-09-28 | 2015-04-21 | Samsung Electronics Co Ltd | 形成細微圖案之方法及製造使用該細微圖案的半導體發光裝置之方法 |
TWI470737B (zh) * | 2008-07-10 | 2015-01-21 | Taiwan Semiconductor Mfg Co Ltd | 積體電路結構 |
TWI395326B (zh) * | 2008-07-31 | 2013-05-01 | Toshiba Kk | 固態攝影裝置及其製造方法 |
TWI490971B (zh) * | 2008-12-31 | 2015-07-01 | Archers Systems Usa Inc | 基板的處理系統、傳輸系統和傳輸方法以及橫向移動室 |
TWI399820B (zh) * | 2009-05-06 | 2013-06-21 | Au Optronics Corp | 電漿處理裝置及其絕緣蓋板 |
Also Published As
Publication number | Publication date |
---|---|
US6689638B2 (en) | 2004-02-10 |
US20030040142A1 (en) | 2003-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW497236B (en) | A soc packaging process | |
US7520052B2 (en) | Method of manufacturing a semiconductor device | |
US7445957B2 (en) | Method for fabricating wafer level semiconductor package with build-up layer | |
TW582078B (en) | Packaging process for improving effective die-bonding area | |
US7446407B2 (en) | Chip package structure | |
KR100352865B1 (ko) | 반도체 장치 및 그 제조방법 | |
US8334174B2 (en) | Chip scale package and fabrication method thereof | |
US8334602B2 (en) | Die package including encapsulated die and method of manufacturing the same | |
JP2002057241A (ja) | 移植性導電パターンを含む半導体パッケージ及びその製造方法 | |
JP2010147153A (ja) | 半導体装置及びその製造方法 | |
US7886609B2 (en) | Pressure sensor package | |
CN114050113A (zh) | 封装方法 | |
US20070080435A1 (en) | Semiconductor packaging process and carrier for semiconductor package | |
JP2625654B2 (ja) | 半導体装置およびその製造方法 | |
US7417313B2 (en) | Method for manufacturing an adhesive substrate with a die-cavity sidewall | |
TWI425580B (zh) | 製造半導體晶片封裝模組之方法 | |
TW511258B (en) | Substrate-on-chip packaging process | |
JP2928755B2 (ja) | 電子部品の製造方法 | |
JP3895920B2 (ja) | 半導体装置 | |
JP2002319650A (ja) | フリップチップ実装体及び半導体チップの実装方法 | |
JP4408015B2 (ja) | 半導体装置の製造方法 | |
CN1405869A (zh) | 基板在晶片上的封装方法 | |
JP4473668B2 (ja) | 半導体装置およびその製造方法 | |
JP3718083B2 (ja) | 半導体装置用接着フィルム | |
TW541671B (en) | Semiconductor chip package method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |