TW486780B - A method for reducing dishing related issues during the formation of shallow trench isolation structures - Google Patents

A method for reducing dishing related issues during the formation of shallow trench isolation structures Download PDF

Info

Publication number
TW486780B
TW486780B TW090113472A TW90113472A TW486780B TW 486780 B TW486780 B TW 486780B TW 090113472 A TW090113472 A TW 090113472A TW 90113472 A TW90113472 A TW 90113472A TW 486780 B TW486780 B TW 486780B
Authority
TW
Taiwan
Prior art keywords
patent application
film
item
scope
dielectric material
Prior art date
Application number
TW090113472A
Other languages
English (en)
Chinese (zh)
Inventor
Sailesh Chittipeddi
Ankineedu Velaga
Arun K Nanda
Original Assignee
Agere Syst Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Syst Guardian Corp filed Critical Agere Syst Guardian Corp
Application granted granted Critical
Publication of TW486780B publication Critical patent/TW486780B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
TW090113472A 2000-06-02 2001-06-04 A method for reducing dishing related issues during the formation of shallow trench isolation structures TW486780B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/586,384 US6500729B1 (en) 2000-06-02 2000-06-02 Method for reducing dishing related issues during the formation of shallow trench isolation structures

Publications (1)

Publication Number Publication Date
TW486780B true TW486780B (en) 2002-05-11

Family

ID=24345514

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090113472A TW486780B (en) 2000-06-02 2001-06-04 A method for reducing dishing related issues during the formation of shallow trench isolation structures

Country Status (4)

Country Link
US (1) US6500729B1 (https=)
JP (1) JP5239107B2 (https=)
GB (1) GB2368460B (https=)
TW (1) TW486780B (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7514336B2 (en) * 2005-12-29 2009-04-07 Agere Systems Inc. Robust shallow trench isolation structures and a method for forming shallow trench isolation structures
CN105702573B (zh) * 2014-11-27 2019-03-26 联华电子股份有限公司 平坦化半导体装置的方法
FR3054927B1 (fr) * 2016-08-04 2018-07-13 Soitec Procede de fabrication d'une structure de semi-conducteur
CN113611663A (zh) * 2021-08-23 2021-11-05 上海芯物科技有限公司 一种半导体表面平坦化的方法及制得的半导体和用途
US20230129131A1 (en) * 2021-10-25 2023-04-27 Soitec Method for manufacturing a semiconductor structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5189501A (en) 1988-10-05 1993-02-23 Sharp Kabushiki Kaisha Isolator for electrically isolating semiconductor devices in an integrated circuit
JP2597022B2 (ja) 1990-02-23 1997-04-02 シャープ株式会社 素子分離領域の形成方法
US5376222A (en) * 1991-09-04 1994-12-27 Fujitsu Limited Polishing method for polycrystalline silicon
JP3265199B2 (ja) * 1996-09-30 2002-03-11 株式会社東芝 化学的機械研磨法、化学的機械研磨法に用いる研磨剤および半導体装置の製造方法
JP3904676B2 (ja) * 1997-04-11 2007-04-11 株式会社ルネサステクノロジ トレンチ型素子分離構造の製造方法およびトレンチ型素子分離構造
US5872045A (en) * 1997-07-14 1999-02-16 Industrial Technology Research Institute Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation
US6136664A (en) * 1997-08-07 2000-10-24 International Business Machines Corporation Filling of high aspect ratio trench isolation
JPH1187487A (ja) * 1997-09-03 1999-03-30 Oki Electric Ind Co Ltd 選択酸化方法
JPH11284061A (ja) * 1998-03-31 1999-10-15 Kawasaki Steel Corp 半導体装置の製造方法
US6303461B1 (en) 1998-12-23 2001-10-16 United Microelectronics Corp. Method for fabricating a shallow trench isolation structure
JP3450221B2 (ja) 1999-04-21 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
TW429514B (en) * 1999-10-06 2001-04-11 Mosel Vitelic Inc Planarization method for polysilicon layer deposited on the trench
US6316331B1 (en) * 2000-10-13 2001-11-13 Vanguard International Semiconductor Corp. Method of making dishing-free insulator in trench isolation

Also Published As

Publication number Publication date
US6500729B1 (en) 2002-12-31
GB0113492D0 (en) 2001-07-25
JP5239107B2 (ja) 2013-07-17
JP2002076110A (ja) 2002-03-15
GB2368460B (en) 2005-01-05
GB2368460A (en) 2002-05-01

Similar Documents

Publication Publication Date Title
CN100424850C (zh) 浅沟槽隔离结构的制造方法以及半导体结构
US6566224B1 (en) Process for device fabrication
JP2004363595A5 (https=)
TW379406B (en) Shallow trench isolation method
JP2004363595A (ja) ポリシラザンをベースとする材料による高アスペクト比の分離構造体の充填
JPS62500134A (ja) 半導体デバイス内の電気コンタクト
TW392308B (en) Method of making metal oxide semiconductor (MOS) in IC
TW405212B (en) The flatten process of interlayer dielectric
TW201409611A (zh) 溝渠絕緣製程
TW471056B (en) Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing
TW400605B (en) The manufacturing method of the Shallow Trench Isolation (STI)
TW486780B (en) A method for reducing dishing related issues during the formation of shallow trench isolation structures
CN110444470A (zh) 一种改善半导体器件内不同线宽电晶体栅极高度的方法
US6358785B1 (en) Method for forming shallow trench isolation structures
JP2000269318A (ja) 半導体装置及びその製造方法
TWI240357B (en) Shallow trench isolation fabrication
CN111403340B (zh) 半导体器件的形成方法
US6551900B1 (en) Trench gate oxide formation method
US7026211B1 (en) Semiconductor component and method of manufacture
TW393724B (en) A manufacturing method of shallow trench isolation
KR19990015602A (ko) 질화막 스페이서를 이용한 트랜치 소자분리방법
JPH11233617A (ja) 半導体装置の製造方法及び半導体装置
KR0147629B1 (ko) 반도체 장치의 소자분리방법
TW466154B (en) Method for chemical mechanical polishing in combination with spin coating
US20060286756A1 (en) Semiconductor process and method for reducing parasitic capacitance

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees