TW473962B - Cavity down ball grid array package and its manufacturing process - Google Patents

Cavity down ball grid array package and its manufacturing process Download PDF

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Publication number
TW473962B
TW473962B TW090101425A TW90101425A TW473962B TW 473962 B TW473962 B TW 473962B TW 090101425 A TW090101425 A TW 090101425A TW 90101425 A TW90101425 A TW 90101425A TW 473962 B TW473962 B TW 473962B
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TW
Taiwan
Prior art keywords
cavity
pads
grid array
substrate
scope
Prior art date
Application number
TW090101425A
Other languages
English (en)
Inventor
Ming-Shiun Li
Jin-De Chen
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW090101425A priority Critical patent/TW473962B/zh
Priority to US09/955,849 priority patent/US6515361B2/en
Application granted granted Critical
Publication of TW473962B publication Critical patent/TW473962B/zh
Priority to US10/310,588 priority patent/US6670219B2/en

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

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473962 6680twf.doc/006 A7 B7 五、發明說明（I ) 本發明是有關於一種晶穴朝下型球格陣列式封裝及 其製程，且特別是有關於一種基板之貫穿孔內具有導電凸 塊，以提高晶穴朝下型球格陣列式封裝之可靠度。 C請先閱讀背面之注意事項再填寫本頁) 在現今資訊爆炸的世界，積體電路已與日常生活有 密不可分的關係，無論在食衣住行育樂方面，都常會用到 積體電路元件所組成之產品。隨著電子科技的不斷演進， 更人性化、功能性更複雜之電子產品不斷推陳佈新，然而 各種產品無不朝向輕、薄、短、小的趨勢設計，以提供更 便利舒適的使用。 在電子構裝的領域中，球格陣列（Ball GridArray， BGA)的封裝形式係爲一般常見的封裝形式，其封裝形式係 透過貼帶或其他黏著材質，將晶片以其背面貼附於基板之 晶片座（die pad)上，並藉由導線使晶片之焊墊（bonding pad)與基板之接點電性連接，一封裝材料包覆晶片、導線、 接點，而多個銲球植入於基板之植球接點上，使得上述之 BGA構裝可以透過銲球與外界電路電性連接。上述之BGA 封裝結構由於對外之電路佈局（layout)係呈現爲矩陣之形 式，因此其所可以容納的對外電路佈局之數目較多，適合 高密度的封裝。 經濟部智慧財產局員工消費合作社印製 然而，在晶片體積縮小的同時，由於元件的積集度 提高，使得兀件操作時單位面積的發熱量相對地增加’因 而必須考量散熱性的問題。就BGA封裝領域而言，晶穴朝 下型球格陣列式封裝（Cavity Down Ball Grid Array，CDBGA) 之散熱效率甚佳，此乃由於晶片之背面直接接觸散熱片 3 本紙張尺度適用中國國家標準（CNS)A4 ϋ721〇χ 297公爱） 473962 668〇twf.doc/006 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（之） (Heat Spreader)，透過散熱片將熱直接傳導至外界，爲 經常運用的封裝結構。 §靑參照第1圖至第4圖，其繪示美國專利第 6，020，617號之晶穴朝下型球格陣列式封裝製程的剖面示 意圖。 請先參照第1圖，並同時參照第1A圖，其繪示對 應於第1圖之俯視示意圖。就製程上而言，首先提供一散 熱片基材110，散熱片基材11〇係透過一黏著體 120(adhesive)，將一散熱片13〇、一接地板14〇貼合而成， 而接地板140位於散熱片130之一表面132之上，並且接 地板140具有一開口 142，使得散熱片基材110的中間部 份形成一凹穴U2。 接下來，接地板140之一表面144上還選擇性鍍上 環狀的一第一接點146與多個第二接點148，而第一接點 146與第二接點148之導電材質包括金、銀。然後再進行 黑化處理，使接地板140之表面144粗化，可以增加將來 與基板（未繪示）間的接合性。 請爹照弟2圖’提供一^基板150，基板150係由一* 絕緣膚160及一圖案化線路層170疊合而成，而基板150 係以其絕緣層160，並藉由一黏著體122，將基板150與 接地板140之表面144貼合，同時圖案化線路層170具有 多個接地墊Π2、多個銲球墊174、多個接點176。另外在 其板丨5〇上還具有一焊罩層180(Solder Mask) ’可以保護 圖案化線路層17〇 ’並暴露出接地墊Π2、銲球墊Π4、接 4 &紙張尺产,標準（CNS)A4規格（210 X 297公釐） ------------ 裝—— (請先閱讀背面之注意事項寫本頁) · --線· 473962 6680twf.doc/006 A7 B7 五、發明說明（3?) 點176。其中基板15Q具有多個貫穿孔190,貫穿孔19〇 貫穿圖案化線路層170、絕緣層160、黏著體122，而暴露 出第二接點148。 接下來以網板印刷（stencil printing)的方式，塡 入一導電物質於貫穿孔190內，使得接地墊172與第二接 點148電性連接。 言円參照弟3圖’提供一^晶片200 ’晶片200具有一^ 主動表面202以及對應之一背面2〇4，在主動表面2〇2之 表層具有多個焊墊206、接地焊墊208。接下來，藉由一 黏著體124 ’使晶片200以其背面204與散熱片13()之表 面132貼合。然後打上導線21〇，使焊墊206與接點ι76 電性連通，接地焊墊208與第一接點146電性連通。 請參照第4圖，接下來進行封膠（encapsulatlng) 的製程，使得一封裝材料220包覆晶片200、焊墊206、 接地焊墊208、導線210、第一接點146、接點176。然後 進行一植球之製程，形成多個銲球230分別植接於接地墊 172及銲球墊Π4。 經濟部智慧財產局員工消費合作社印製 然而，上述之晶穴朝下型球格陣列式封裝製程，必 須以網板印刷的方式，塡入一導電物質於貫穿孔190內， 如此之製程甚爲複雜，因而增加製造成本。並且在進行網 板印刷的同時，容易形成空孔（void)於貫穿孔190內之導 電物質間，造成產品信賴度降低之問題。 因此本發明的目的之一就是在提供一種晶穴朝下型 球格陣列式封裝及其製程，可以簡化製程，降低製造成本。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473962 6680twf.doc/006 A7 B7 五、發明說明（+) 本發明的目的之二就是在提供一種晶穴朝下型球格 陣列式封裝及其製程’可以確保貫穿孔內導電物質之電性 接合的狀態，以提高產品的信賴度。 爲達成本發明之上述和其他目的，提出一種晶穴朝 下型球格陣列式封裝，其包括：一散熱片基材，具有一晶 片放置區域位於中央，及一基板放置區域位於晶片放置區 域外圍。多個導電凸塊，配置於基板放置區域。一基板， 此基板係由一絕緣層及一圖案化線路層疊合形成，絕緣層 具有多個貫穿孔’分別對應於導電凸塊，基板以其絕緣層 貼附於基板放置區域’而圖案化線路層具有多個接地墊、 多個銲球墊及多個接點，接地墊分別位於貫穿孔上，其中 每一接地墊中央具有一孔洞與對應之貫穿孔貫通，基板還 包括一焊罩層覆蓋於圖案化線路層上，並暴露出接地墊、 銲球墊及接點。一晶片，具有一主動表面及對應之一背面， 此晶片以其背面貼附於晶片放置區域，其中晶片之主動表 面具有多個焊墊，而焊墊分別與接點電性連接。一封裝材 料，包覆晶片、接點及焊墊與接點連接的部分。多個銲球， 分別配置於接地墊及銲球墊，其中位於接地墊之銲球分別 充滿於貫穿孔中，並分別與導電凸塊電性連接。 爲達成本發明之上述和其他目的，提出一種晶穴朝 下型球格陣列式封裝製程，包括··提供一散熱片基材，此 散熱片基材具有一晶片放置區域位於中央，及一基板放置 區域位於晶片放置區域外圍。然後形成多個導電凸塊，配 置於基板放置區域。還要提供一基板，基板係由一絕緣層 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項寫本頁)
I I 線· 經濟部智慧財產局員工消費合作社印製 473962 6680twf.doc/006 A7 B7 五、發明說明（y) 及一圖案化線路層疊合形成，且絕緣層具有多個貫穿孔’ 分別對應導電凸塊，基板以其絕緣層貼附於基板放置區 域，圖案化線路層具有多個接地墊、多個銲球墊及多個接 點，接地墊分別位於貫穿孔上，其中每一接地墊中央具有 一孔洞與對應之貫穿孔貫通。然後形成一焊罩層’覆蓋於 圖案化線路層上，並暴露出接地墊、銲球墊及接點。提供 一*晶片’此晶片具有一'主動表面及對應之一面’且晶片 以其背面貼附於晶片放置區域，而晶片之主動表面具有多 個焊墊。接下來，電性連接焊墊與接點。然後進行一封膠 製程，以一封裝材料包覆晶片、接點及焊墊與接點連接的 部分。接下來將多個銲球分別植接於接地墊及銲球墊，其 中位於接地墊之銲球分別充滿於貫穿孔中，並分別與導電 凸塊電性連接。 經濟部智慧財產局員工消費合作社印製 依照本發明的一較佳實施例，其中散熱片基材有兩 種形式，第一種之散熱片基材係由一散熱片及一接地板疊 合形成，且接地板位於基板放置區域，並具有一開口暴露 出晶片放置區，以形成一凹穴，而接地板與晶片電性連接； 第二種之散熱片基材係在其晶片放置區域具有一凹穴，晶 片貼附於此凹穴底部，而散熱片基材與晶片電性連接。 此外’絕緣層之材質包括聚亞醯胺，而圖案化線路 層係由一銅箱層經由微影蝕刻步驟定義形成。另外，導電 凸塊之製作方法’可包括如下之方式製作：係利用一打線 機，形成多個打線凸塊；利用電鍍方法，形成多個金屬凸 塊’其金屬凸塊的材質包括金或銀；利用點膠方式，形成 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 473962 6680twf.doc/006 A7 B7 五、發明說明（6) 多個導電高分子凸塊。此外，在基板放置區域之表面還包 括電鍍一纟E層。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖示之簡單說明： 第1圖至第4圖繪示習知晶穴朝下型球格陣列式封 裝製程的剖面示意圖。 第1A圖繪示對應於第1圖之俯視示意圖。 第5圖至第9圖繪示本發明第一較佳實施例的一種 晶穴朝下型球格陣列式封裝製程的剖面示意圖。 第5A圖繪示對應於第5圖之俯視示意圖。 第10圖繪示本發明第二較佳實施例的一種晶穴朝 下型球格陣列式封裝製程的剖面示意圖。 第11圖繪示本發明第三較佳實施例的一種晶穴朝 下型球格陣列式封裝製程的剖面示意圖。 第12圖繪示本發明第四較佳實施例的一種晶穴朝 下型球格陣列式封裝製程的剖面示意圖。 圖示之標示說明： 110、310、500、600 :散熱片基材 314、602 :晶片放置區域 316、604 :基板放置區域 112、312、510 :凹穴 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝--- (請先閱讀背面之注意事項寫本頁) 訂· 線： 經濟部智慧財產局員工消費合作社印製 473962 6 6 8 Otwf. doc/ 0 0 6 A7 B7 五、發明說明（q) 130、1 330 :散熱片 140、340 ··接地板 142、342 :開口 144、132、332、344 :表面 350 ··鈀層 360 :導電凸塊 146、346 :第一接點 148、348 :第二接點 120、122、124、320、322、324 :黏著體 150、370 :基板 160、380 :絕緣層 170、390 :圖案化線路層 172、392 :接地墊 398 :孔洞 174、394 ··銲球墊 176、396 :接點 180、410 :焊罩層 190、400 :貫穿孔 200、420 :晶片 202、422 :主動表面 2〇4、424 :背面 206、426 :焊墊 208、428 :接地焊墊 210、430、520 :導線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝--------訂---------線 (請先閱讀背面之注意事項寫本頁) « 473962 6680twf.doc/006 pj ____—____B7 五、發明說明（/) 220、440 :封裝材料 230、450 :銲球 -------------裝--- (請先閱讀背面之注意事項寫本頁) 實施例 請參照第5圖至第9圖，其繪示本發明第一較佳實 施例的一種晶穴朝下型球格陣列式封裝製程的剖面示意 圖。 •線- 請先參照第5圖，並同時參照第5A圖，其繪示對 應於第5圖之俯視示意圖。首先提供一散熱片基材310， 散熱片基材310具有一晶片放置區域314以及一基板放置 區域316。而散熱片基材310係透過一黏著體320，將一 散熱片330、一接地板340貼合而成，接地板340位於散 熱片330之基板放置區域316的表面332之上，並且接地 板340具有一開口 342，使得散熱片基材310的中間部份 形成一凹穴312，此凹穴312形成的區域爲晶片放置區域 314 ° 經濟部智慧財產局員工消費合作社印製 接下來，可選擇性進行一表面處理之製程，將接地 板340之一表面344上全面鍍上一IG層350。然後再進行 一製作導電凸塊之製程，形成多個導電凸塊360於鈀層350 上，其中製作導電凸塊360的方式有三種：第一種方式係 利用一打線機（未繪示），打上多個打線凸塊，以形成導電 凸塊360。第二種方式係利用電鍍方法，鍍上多個金屬凸 塊，以形成導電凸塊360，其金屬凸塊的材質可包括金或 銀。第三種方式係利用點膠方式，點上多個導電高分子凸 ^紙張尺度顧巾關家鮮（CNS)A4規格（210 X 297公釐) 473962 6680twf.doc/005 A7 B7 五、發明說明（q ) 一 塊，以形成導電凸塊360。然而，在本實施例中僅繪示以 打線機（未繪示）製作的導電凸塊360之形狀。 請參照第ό圖，然後提供一基板370，基板37(3係 由一絕緣層380及一圖案化線路層390疊合而成，而基板 370係以其絕緣層380，並藉由一黏著體322，將基板370 與鈀層350貼合，同時圖案化線路層390具有多個接地墊 392、多個銲球墊394、多個接點396。另外絕緣層380還 具有多個貫穿孔400，分別對應導電凸塊360，並且接地 墊392位於貫穿孔400上，其中每一接地墊392中央具有 一孔洞398與對應之貫穿孔400貫通。 請參照第7圖，接下來在基板370上還鋪上一焊罩 層410(Solder Mask)，可以保護圖案化線路層390，並暴 露出接地墊392、銲球墊394、接點396。除了上述之焊罩 層410的製作方法外，亦可以先將焊罩層410鋪設於基板 370上，再將基板370與鈀層350貼合。 經濟部智慧財產局員工消費合作社印製 請參照第8圖，接下來還提供一晶片420，晶片420 具有一主動表面422以及對應之一背面424，在主動表面 422之表層具有多個焊墊426、接地焊墊428。然後藉由一 黏著體324 ’使晶片420以其背面424與散熱片330之晶 片放置區域314表面332貼合。然後打上導線430，使焊 墊426與接點396電性連通，接地焊墊428與接地板340 電性連通。 s円参"如桌9圖，接下來進行封膠（encapSUiating) 的製程’使得一封裝材料44〇包覆晶片“ο、焊墊426、 本紙張尺度適用中國國家標準（CNS)A4 ^7210^297 473962 6680twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（丨ο) 接地焊墊428、導線430、接點396。然後進行一植球之製 程，並透過迴焊（reflow)的過程，形成多個銲球450分別 植接於接地墊392及銲球墊394上，其中位於接地墊392 之銲球450的導電材質還塡入貫穿孔400中，並且與導電 凸塊360電性連接。 在上述之製程中，由於透過製作導電凸塊之製程， 當貼附基板370於散熱片基材310之接地板340之上時， 導電凸塊360會塡充於對應之基板370的貫穿孔400內， 再透過植球、迴焊之製程，使得貫穿孔400得以塡滿導電 材質，如此可以簡化製程，而降低製造成本，並且不易在 貫穿孔400內形成空孔，以確保貫穿孔400內導電物質之 電性接合的狀態，以提高產品的信賴度。 請參照第10圖，其繪示本發明第二較佳實施例的 一種晶穴朝下型球格陣列式封裝製程的剖面示意圖。上述 的第一較佳實施例中，在進行表面處理之製程時，接地板 之一表面上全面鍍上一鈀層，然後再形成多個導電凸塊於 鈀層上。然而電鍍之方式與材質並非侷限於上述的方式， 亦可以在接地板340之表面344選擇性鍍上多個第一接點 346與多個第二接點348，而第一接點346與第二接點348 之導電材質包括金、銀。接下來進行黑化處理，使接地板 340之表面344粗化，可以增加與基板37〇之絕緣層380 間的接合性。並且凸塊360配置於第二接點348上，而透 過導線430，可以使接地焊墊428與第一接點346電性連 通。 (請先閱讀背面之注意事項 鼢裝—— 寫本頁) 訂· •線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 473962 6680twf.doc/〇〇6 A7 _____ B7 五、發明說明（II) 請參照第π圖，其繪示本發明第三較佳實施例的 一種晶穴朝下型球格陣列式封裝製程的剖面示意圖。上述 的第一較佳實施例中，散熱片基材係透過一黏著體，將一 散熱片、一接地板貼合而成，然而散熱片基材的形式並非 限於上述之方式，亦可以選用一體成型的中央晶片放置區 域具有凹穴510之散熱片基材500，而基板直接貼附於散 熱片基材之基板放置區域，並且晶片420以其背面424貼 附於凹穴510之底部，而透過導線520，可以使接地焊墊 428與與散熱片基材500電性連通。 請參照第12圖，其繪示本發明第四較佳實施例的 一種晶穴朝下型球格陣列式封裝製程的剖面示意圖。在上 述的第三較佳實施例中，散熱片基材具有一凹穴，然而散 熱片基材的形式並非限於上述之方式，亦可以是無凹穴的 散熱片基材600,而晶片420貼附於晶片放置區域602上， 而基板370貼附於基板放置區域604上，而基板370之開 口即形成位於散熱片基材600表面的凹穴。 經濟部智慧財產局員工消費合作社印製 綜上所述，由於透過製作導電凸塊之製程，當貼附 基板於散熱片基材之上時，導電凸塊會塡充於對應之基板 的貫穿孔內，再透過植球、迴焊之製程，使得貫穿孔得以 塡滿導電材質，如此可以簡化製程，而降低製造成本，並 且不易在貫穿孔內形成空孔，以確保貫穿孔內導電物質之 電性接合的狀態，以提高產品的信賴度。 雖然本發明已以多個較佳實施例揭露如上，然其並 非用以限定本發明，任何熟習此技藝者，在不脫離本發明 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473962 6680twf.doc/006 A7 _B7_五、發明說明（之精神和範圍內，當可作些許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者爲準。 -----------k裝—— (請先閱讀背面之注意事項寫本頁) -·線」 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 473962 A8B8C8D8 六、申請專利範圍 1. 一種晶穴朝下型球格陣列式封裝，包括： 一散熱片基材，具有一晶片放置區域位於中央，及 (請先閱讀背面之注意事項再Wk本頁) 一基板放置區域位於該晶片放置區域外圍； 複數個導電凸塊，配置於該基板放置區域； 一基板，該基板係由一絕緣層及一圖案化線路層疊 合形成，該絕緣層具有複數個貫穿孔，分別對應該些導電 凸塊，該基板以該絕緣層貼附於該基板放置區域，該圖案 化線路層具有複數個接地墊、複數個銲球墊及複數個接 點，該些接地墊分別位於該些貫穿孔上，其中每一該些接 地墊中央具有一孔洞與對應之該貫穿孔貫通，該基板還包 括一焊罩層覆蓋於該圖案化線路層上，並暴露出該些接地 墊、該些銲球墊及該些接點； 一晶片，具有一主動表面及對應之一背面，該晶片 以該背面貼附於該晶片放置區域，其中該主動表面具有複 數個焊墊，該些焊墊分別與該些接點電性連接； ·-線- 一封裝材料，包覆該晶片、該些接點及該些焊墊與 該些接點連接的部分； 經濟部智慧財產局員工消費合作社印製 複數個銲球，分別配置於該些接地墊及該些銲球 墊，其中位於該些接地墊之該些銲球分別充滿於該些貫穿 孔中，並分別與該些導電凸塊電性連接。 2. 如申請專利範圍第1項所述之晶穴朝下型球格陣 列式封裝，其中該散熱片基材係由一散熱片及一接地板疊 合形成，其中該接地板位於該基板放置區域，並具有一開 口暴露出該晶片放置區，以形成一凹穴。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A8B8C8D8 473962 六、申請專利範圍 3. 如申請專利範圍第2項所述之晶穴朝下型球格陣 列式封裝，其中該晶片與該接地板電性連接。 4. 如申請專利範圍第1項所述之晶穴朝下型球格陣 列式封裝，其中該散熱片基材位於該晶片放置區域具有一 凹穴，該晶片係貼附於該凹穴底部。 5 .如申請專利範圍第1項或第4項所述之晶穴朝下 型球格陣列式封裝，其中該晶片與該散熱片基材電性連 接。 6. 如申請專利範圍第1項所述之晶穴朝下型球格陣 列式封裝，其中該絕緣層包括聚亞醯胺。 7. 如申請專利範圍第1項所述之晶穴朝下型球格陣 列式封裝，其中該圖案化線路層係由一銅箔層經由微影蝕 刻步驟定義形成。 8. 如申請專利範圍第1項所述之晶穴朝下型球格陣 列式封裝，其中該些導電凸塊係利用一打線機，形成複數 個打線凸塊。 9. 如申請專利範圍第1項所述之晶穴朝下型球格陣 列式封裝，其中該些導電凸塊係利用電鍍方法，形成複數 個金屬凸塊。 10. 如申請專利範圍第9項所述之晶穴朝下型球格 陣列式封裝，其中該些金屬凸塊的材質包括金及銀二者擇 -^ 〇 11. 如申請專利範圍第1項所述之晶穴朝下型球格 陣列式封裝，其中該些導電凸塊係利用點膠方式，形成複 (請先閱讀背面之注意事項再^^本頁) ¾ --線. 經濟部智慧財產局員工消費合作社印制衣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473962 6680twf.doc/006 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 數個導電高分子凸塊。 12. 如申請專利範圍第1項所述之晶穴朝下型球格 陣列式封裝，其中該基板放置區域表面還包括電鍍一鈀 層。 13. —種晶穴朝下型球格陣列式封裝製程，包括： 提供一散熱片基材，該散熱片基材具有一晶片放置 區域位於中央，及一基板放置區域位於該晶片放置區域外 圍； 形成複數個導電凸塊，配置於該基板放置區域； 提供一基板，該基板係由一絕緣層及一圖案化線路 層疊合形成，該絕緣層具有複數個貫穿孔，分別對應該些 導電凸塊，該基板以該絕緣層貼附於該基板放置區域，該 圖案化線路層具有複數個接地墊、複數個銲球墊及複數個 接點，該些接地墊分別位於該些貫穿孔上，其中每一該些 接地墊中央具有一孔洞與對應之該貫穿孔貫通； 形成一焊罩層，覆蓋於該圖案化線路層上，並暴露 出該些接地墊、該些銲球墊及該些接點； 提供一晶片，該晶片具有一主動表面及對應之一背 面，該晶片以該背面貼附於該晶片放置區域，其中該主動 表面具有複數個焊墊； 電性連接該些焊墊與該些接點； 進行一封膠製程，以一封裝材料包覆該晶片、該些 接點及該些焊墊與該些接點連接的部分； 將複數個銲球分別植接於該些接地墊及該些銲球 (請先閱讀背面之注意事項再本頁)
    νδ_ --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473962 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 ^ 中位於該些接地墊之該些銲球分別充滿於該些貫穿 孔中’並分別與該些導電凸塊電性連接。 14.如申請專利範圍第13項所述之晶穴朝下型球格 陣列^封裝製程，其中該散熱片基材係由一散熱片及一接 %1反®合形成’其中該接地板位於該基板放置區域，並具 有一開口暴露出該晶片放置區，以形成一凹穴。 15·如申請專利範圍第13項所述之晶穴朝下型球格 _歹(1式i封*^製程，其中該晶片與該接地板電性連接。 16·如申請專利範圍第13項所述之晶穴朝下型球格 陣歹fi式:封裝製程’其中該散熱片基材位於該晶片放置區域 具有一凹穴’該晶片係貼附於該凹穴底部。 17·如申請專利範圍第13項或第16項所述之晶穴 朝下型球格陣列式封裝製程，其中該晶片與該散熱片基材 電性連接。 18.如申請專利範圍第13項所述之晶穴朝下型球格 陣列式封裝製程，其中形成該些導電凸塊前，還包括在該 基板放置區域表面電鍍一 IE層。 19 ·如申請專利範圍第13項所述之晶穴朝下型球格 陣列式封裝製程，其中該絕緣層包括聚亞醯胺，且該圖案 化線路層係由一銅箔層經由微影蝕刻步驟定義形成。 20.如申請專利範圍第13項所述之晶穴朝下型球格 陣列式封裝製程，其中形成該些導電凸塊的方法包括利用 一打線機，形成複數個打線凸塊。 21 ·如申請專利範圍第13項所述之晶穴朝下型球格 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再11¾本頁)
    汀· --線· 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 陣列式封裝製程，其中形成該些導電凸塊的方法包括利用 電鑛方法，形成複數個金屬凸塊。 22. 如申請專利範圍第21項所述之晶穴朝下型球格 陣列式封裝製程，其中該些金屬凸塊的材質包括金及銀二 者擇一。 23. 如申請專利範圍第13項所述之晶穴朝下型球格 陣列式封裝製程，其中形成該些導電凸塊之方法包括利用 點膠方式，形成複數個導電高分子凸塊。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
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