TW466732B - Semiconductor device with deep substrate contacts - Google Patents

Semiconductor device with deep substrate contacts Download PDF

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Publication number
TW466732B
TW466732B TW088102471A TW88102471A TW466732B TW 466732 B TW466732 B TW 466732B TW 088102471 A TW088102471 A TW 088102471A TW 88102471 A TW88102471 A TW 88102471A TW 466732 B TW466732 B TW 466732B
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patent application
connection
scope
semiconductor
substrate
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TW088102471A
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Ted Johansson
Christian Nystrom
Arne Rydin
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Ericsson Telefon Ab L M
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Description

466732 五、發明說明 發明之技術領域 _ 本發明係關於一種半導體裝置及半導體積體電路安裝於 封裝體’封裝體包含一半導體電路及至少一半導體裝置。 相關技術之說明 近代電信電子裝置之工作頻率由數百MHz至GHz區域之範 圍。功率電晶體於信號位階大及電流密度高時工作最有 效。本高壓石夕RF功率電晶體可於大於2 GHz頻率輸送數百 瓦輸出功率'，典型於25伏工作。此等電晶體典型用於穩態 用途、，例如蜂巢式電話基地台、數位廣播或電視發射器之 輸出放大器。 用於類似無線手機電話之用途，電源功率限於2_6伏之 範圍（以蓄電池工作）’輸出功率係於〇 ·丨_4瓦範圍，及工 作頻率係於1-3 GHz之範圍。 此領域之主要技術類別係基於Ga As，但於此領域今曰開 發矽基電路。矽的主要優點是價格低廉，缺點係高頻性能 較受限。 全部射頻功率應用之共通困難係於工作頻率增高而電源 功率降低時如何維持功率增益及輸出功率。特別來自接線 的寄生發射器/來源電感之此種性能低劣，原因為其占有 傳輸功率給負載之關鍵部份。最終導致裝置尺寸受限，及 裝置用於某些應用之用途受限。此點亦適用於具有較低電 壓f較低功率之積體放大器，例如雙極性及M〇s技術之分 立高壓射頻功率電晶體。低阻抗連結接地為此型裝置所必
第5頁 466732 五、發明說明（2) 於半導體基材上製造之包含複數半導體裝置之積體電路 通常係設置於封裝體内，附有接腳或其它器具來接觸積體 電路。接腳通常係透過接線連接至積體電路，接線具有不 等長度。接地接腳可連結至引線框，所謂的熔合引線框， 引線柩上架設積體電路，此處基材反側係與引線框做電接 觸。 由積體電路上的接線墊至接腳之通常連結係透過長接線 獲得’對直徑10-30微米（1-2密耳）之接線而言，於直流具 有電感約InH/mm及電阻約3πιΩ/ιηιη。平行接線用於使電感 及電阻減至最低。 典型封裝體之接線長度為卜2毫米，獲得電感為卜2 ηΗ/ 接線。經由引進接線墊之短接線至引線框用於接地連結， 電感可降至0.2 ηΗ ’產生阻抗於2 GHz為約2. 5 Ω。 用於橫向DMOS電晶體介於源極與基材間形成低阻抗接觸 的既有技術，包含高度攙雜擴散柱塞或接觸結構，包括凹 槽以導體填補，如D’ Anna等之美國專利5, 821，144所述。 其它類型形成低祖抗接觸之接點具有貫穿基材之蝕刻 孔，而以金屬填補用於GaAs MESFET應用。 具有高頻應用之半導體裴置之深的以鎢填補的基材接 觸，述於Norstromf之專利申請案ψ〇 9?/35344。接觸提 供第一金屬層與馬度攙雜基材件透過低度攙雜磊晶層直接 耦合的手段，於其中實現該裝置。該專利申請案包含用做 接地平面、干擾及串音下降與筛檢之方法之裝置。 發明概述
第6頁 五、發明說明（3) 本發明之 此處該接地 封裝體上的 本發明之 電路，附有 之接地連結 此等目的 基材之一表 連接'*包含 雜的基材與 置成可連結 設置成使用 成透過基材 建立接地連 本發明之 接腳可建立 連結之半導體裝置， ’特別於高頻連結至 電路，包含一半導體 封裝體内，介於裝置 有低阻抗連結。 ’其係設置於半導體 雜，該基材包含一電 成的柱塞介於初步攙 有至少一接地連結設 該至少一接地連結係 ’此處該基材係設置 接地接腳，藉此設置 目的係提供一種具有接地 係設置成透過低阻抗遠站 接地接腳。 結與封裝體上之接地 對高頻應用尤為如 此 另一目的係提供一種積體 至少一半導體裝置安裝於 與封裝體之接地接腳間具 可藉一種半導體裝置達成 面上，该基材具有初步攙 至少一由高導電性材料製 基材表面間，及該袭置具 至封裝體上之接地接腳， 該電連接連結至接地接腳 反側連結至該表面反侧之 結與接地接腳間之連結。 優點為介於裝置之接地連 具有低阻抗之接觸，特別 另一優點為半導體基材表面上用於連半導 接線❹，原因為接地連結係透過基材反侧連結裝置斤需 又一優點為根據本發明之電路接線可較快速連結於封裝 體’原因為需要較少接線墊故。 、本發明之又另一優點為藉由對各接地連結有複數柱塞可 導引大量電流通過接地連結。 又另一優點為任何類型具有接地連結之裝置容易透過至 46 673 2 五 發明說明（4) 連結，而無需對根據本發明之含有至少一半導體 裝置之積體電路上的接線墊建立導電模式。牛導體 現在將參照附圖說明本發明。 圖式之簡單說明 為/導體電路之部份剖面圖，包含一雙重多晶矽自 丁’雙極性電晶體附有根據本發明之接地連結。 圖2a-2e顯示圖1之半導體裝置之電連結之製造步驟。 圖3顯示’安裝於封裝體上之積體電路之透視圖，封裝體 =有根據本發明之半導體電路具有連接至接地接腳之接地 連結》 較佳具體例之詳細說明 圖1顯不半導體電路之部份剖面圖，該電路包含至少一 雙重多晶石夕自行對正雙極性電晶體丨〇〇附有根據本發明 電連結1 0 1。 半導體裝置100於本例為雙極性NPN電晶體，係於基材 102上製造’談基材具有第一型p+初步高度攙雜，於基材 上生長第一蟲晶層形成一埋置層1〇3，該埋置層具有與第 一型P+相反的第二型n+高度攙雜。第二磊晶層生長於埋置 層103頂上形成n阱1〇4 ’此處第二磊晶層具有第二型η攙 雜。埋置層103及η阱104共同表示雙極性電晶體1〇〇之集極 區。 半導體裝置區係藉隔離裝置105劃界，隔離裝置由基材 表面106向下伸展至埋置層103下方進入初步攙雜基材。場 氧化物107遮蓋基材表面，基材具有集極C之第一開口及射
466732 五、發明說明（5) 開口及雙基極B。具有第二型n+攙雜之高度攙雜 體裝晉：目―：口表面向下延伸至埋置層103，#此型半導 ^常見者。集極c透過高導電性導體110，如鎢、金屬 接觸111及攙雜多晶矽層125連結至高度攙雜區1〇8 ^ 薄區109係於第二開口表面形成，具有第—型p攙 不基極區。於此區1〇9表面形成三個分開區1ΐ2，ιΐ3、。於 中央形成第一型n+攙雜之南度攙雜區’形成射極區112。 結至攙雜多晶石夕層114，其又透過金屬接觸115及 具有尚導電性之連接部丨丨6連結至射極e。 =接觸區113係於射極區112兩邊形成，各基透過 攙雜多晶矽層117、金屬接觸118及具有高導電性之連接部 119連結至該基極接觸區。基極接觸區113向下 通 極區109至η牌104。 "土 該裝置覆蓋以氧化物12〇及psg(磷矽玻璃）層。 隨後於半導體裝置區外侧姓刻一凹槽而形成一柱塞 121，構成電連結1 〇 i之一部份。凹槽由pSG層向下伸展至 初步攙雜基材，於此處以第一型p++高度攙雜形成柱塞接 觸區122。柱塞121係由高導電性，例如金屬，特別鎢，之 材料製成。柱塞透過連接部丨23連結至半導體裝置之任何 需要接地部份’本例為射極接觸E。 藉此方式，建立由射極接觸E至基材1〇2反側124之連 接，其可透過連接部Ϊ23及電連接101，包含柱塞121及柱 塞接觸區122接地。若高電流被導引通過已建立的連結， 則該電連結可包含多個柱塞。 466732 五、發明說明（6) =2a 2e不例說明包括圖j之電連結之半導體裝置之製造 热該圖主要顯示半導體裝置（本例為雙極性電晶體）介 ； 裝置1 0 5間形成區域，柱塞1 2 1係位於此區外側。 =2a顯示基材1〇2(p+型）已經被處理至一點，於此處完 =隨後各處理部份：生長第一磊晶層形成埋置層ι〇3(η + 二，生長第二磊晶層n阱1〇4(11型），引進隔離裝置ι〇5， 丄具5第一及第二開口之場氧化物107，形成高度攙雜 二η垔）由第一開口表面106向下伸展至埋置層1〇3，形成 換極區109 (ρ型）於第二開口表面，沉積具有第一型0高度 攙雜之多晶矽層117及沉積第一氧化物層201於多晶矽層 Π7上。此等步驟皆係以業界人士顯然易知之方式進行。 圖2b顯示半導體裝置之剖面圖，此處射極開口2〇2及集 極開口係形成於第一氧化物層2〇1及多晶矽層117向下伸展 至基極區109。然後第二氧化物層2〇3係沉積於半導體裝置 頂上。 圖2C顯示一半導體裝置之剖面圖，此處第二氧化物層 203已經被蝕刻去除，僅留下二間隔體2〇4來使射極開口縮 窄。具有第二型n+高度攙雜之第二多晶矽層沉積於裝置 上，且如圖2d所示’蝕刻而於射極開口 2〇2形成多晶矽層 114及於第一開口形成多晶矽層125，此乃集極開口。基材 接受退火’其將二區112 ’113驅策入基極區。射極區 112直接形成於射極開口 202之多晶矽層下方，及基極接觸 區113係形成於射極區112位在第一多晶硬層I〗？下方各邊 上’此處基極接觸區113係向下伸展貫穿基極區1〇9進入n
46673 2
阱 104。 圖2e顯示剖面圖，此處形成金屬接觸in ,ιΐ5，ιΐ8來 建立與雙極性電晶體100之電接觸。此種過程已經確立且 為業界人士已知_。 所得半導體裝置100包括由射極連結E至基材124反面之 連結，示例說明及描述於圖1。 圖1及2 a - 2 e僅說明N P N雙極性電晶體，但當然可為其它 類型半導體裝置，例如PNP雙極性電晶體，m〇S電晶體或分 立組件’具有接地連結連結至基材反侧，如圖1所示。半 導體裝置當然可為半導體電路之一部份，電路可由複數不 同半導體裝置組成。一大優點為可獲得較為密實之半導體 電路布局，結果使接觸墊數目減少。 圖3顯示積體電路300之透視圖，積體電路包含一封裝體 302 ’包括接腳及接觸墊303，接線304及一半導體電路 306，該電路包含至少一半導體裝置1〇〇附有根據本發明之 接地連結E連結至接地接腳3 01。 各接腳（接地接腳301除外）係透過接觸墊3〇3及接線3〇4 分別連結皇半導體電路306之至少一塾。接地接腳3〇1較佳 直接連結至引線框305，引線框上墊附接半導體電路3〇6之 反侧124。 先前技術積體電路通常有大量接線來建立由積體電路之 封裝體之接地連結。做出全部連結所需時間係由待附接之 接線數目決定。經由減少所需接線墊數目及做出根據本發 明之接地連結，由於需要附接之接線數目較少，故附接接
第11頁 46673 2 五、發明說明（8) 線至電路上接線墊之程序遠更加速。 可使用其它方式電連結半導體電路之反側，例如透過至 少一個別接線連結引線框。
第12頁

Claims (1)

  1. p a丨 修正補充 '46 673 2 -__案號 88102471 六、申請專利範圍 \ 一種半導體裝置（1 〇 〇 )，其係設置於具有初步攙雜 (P + )之半導體~基材（102)表面（106)上，該裝置具有一電連 ΪΙ1%1)入介於該初步气雜基材與該基材表°面（間，該電 連釔包含至少一由具尚導電性材料製 裝置具有至少一接地連結（Ε )設置成往的柱土（ 2 )" 之接地接腳(3。"，其特徵為封裝體(3, 用該電連接（101)連結至接地接腳（3巧），連此°(^ =成 ^ M ^ ^ „(301 ) , 1 °2^ ^ ^ ^ 與接地接腳（3(H)間之連結㈣配置成可建立接地連結（E) 其特徵為誶材 其特徵為該至 其特徵為該柱 2.如申請專利範圍第1項之半導體f置 料係屬基材（1 〇 2 )以外之類型。 、 3 ·如申請專利範圍第2項之半導體裝置 少一柱塞（121)為金屬柱塞。 4 ·如申請專利乾圍第1項之半導體 塞〇21)伸展入基材U02)内部至比其中已瘦、寺^為該柱 有PN接面更深處。 引進及/或既 5 ·如申請專利範圍第1項之丰導 塞（121)上端係透過導電材料（123) /特別i其^^為各柱 料，特別金屬材料連結至接地連結（ ”阿導電性材. 6. 如申請專利範圍第1至5項中任一項之 特徵為該半導體裝置為高頻襄置。 千導體裝置，其 7. 如申請專利範圍第6項之半導體裝f， 置為功率裝置。 八特散為該裝
    案號88102471 羊^^日 4 6 673 2 _1备正 六、申請專利範園 ___ 8.如申請專利範圍第6項之半導體裝置 置為雙極性電晶體及該接地連結為射極、最沾特徵為該農 9 .如申請專利範圍第6項之半導體裝置二。 晶體為MOS電晶體及該接地連結為 ，、特破為該電 10· —種安裝於一封裝體（3〇2)之本^科 裝體具有連結至半導體電路（ 3 0 6 )之1复數接娜體電路’該封 具有複數半導體裝置’其特徵為該複复數妾腳，及該電路 ^ ^ M f. !(!〇〇)_ . t, - Λ /Λ 含至少一由具局導電性材料製成的柱塞（121)，兮_梦匕 具有至少一接地連結（Ε )設置成待連接至封裝體（^ 〇 地接腳（301)，至少一接地連結（£)配置成使用該電連接 (101)連結至接地接腳（301) ’此處該基材（102)係設置 透過基材（1 2 4 )之與該表面（1 〇 2 )相對的反侧連結至^地 腳（301)，藉此配置成可建立接地連結（Ε)與接^接腳 接 (3 0 1)間之連結。 11.如申請專利範圍第10項之半導體積體電路，其特 為該材料係屬基材（1 0 2 )以外之類型。 ' ^ 1 2·如申請專利範圍第1 1項之半導體積體電路，其特 為該至少一柱塞（121)為金屬柱塞。 1 3 ·如申請專利範圍第1 〇項之半導體積體電路，其特徵 為該柱塞（121)伸展入基材（102)内部至比其中已經引進 /或既有ΡΝ接面更深處。 1 4·如申請專利範圍第1 〇項之半導體積體電路，其特徵 為各柱塞（121)上端係透過導電材料（123)，特別具高導電
    O:\57\57224.ptc
    2001. 08.16. 〇15 46673 2 修正 _案號 88102471 六、申請專利範圍 性材料，特別金屬材料結至接地連結（E )。 1 5.如申請溥利範圍第1 0項之半導體積體電路，其特徵 為該半導體裝置為高頻裝置。 1 6 .如申請專利範圍第1 5項之半導體積體電路，其特徵 為該裝置為功率裝置。 1 7.如申請專利範圍第1 5項之半導體積體電路，其特徵 為該裝置為雙極性電晶體及該接地連結為射極連結。 1 8.如申請專利範圍第1 5項之半導體積體電路，其特徵 為該電晶體為Μ 0 S電晶體及該接地連結為溽極連結。
    O:\57\57224.ptc 第3頁 2001.08. 16.016
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SE9900446L (sv) 2000-08-11
KR100781826B1 (ko) 2007-12-03
US6953981B1 (en) 2005-10-11
CN1160786C (zh) 2004-08-04
SE515158C2 (sv) 2001-06-18
HK1045024A1 (en) 2002-11-08
AU2953000A (en) 2000-08-29
KR20010110426A (ko) 2001-12-13
WO2000048248A1 (en) 2000-08-17
EP1169734A1 (en) 2002-01-09
CA2356868A1 (en) 2000-08-17
SE9900446D0 (sv) 1999-02-10
HK1045024B (zh) 2005-04-29
CN1340211A (zh) 2002-03-13
JP2002536847A (ja) 2002-10-29

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