TW446952B - Circuit-arrangement with temperature dependent semiconductor element test and repair logic - Google Patents

Circuit-arrangement with temperature dependent semiconductor element test and repair logic Download PDF

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Publication number
TW446952B
TW446952B TW088117410A TW88117410A TW446952B TW 446952 B TW446952 B TW 446952B TW 088117410 A TW088117410 A TW 088117410A TW 88117410 A TW88117410 A TW 88117410A TW 446952 B TW446952 B TW 446952B
Authority
TW
Taiwan
Prior art keywords
test
temperature
self
circuit configuration
patent application
Prior art date
Application number
TW088117410A
Other languages
English (en)
Chinese (zh)
Inventor
Connell Roderick Mc
Detlev Richter
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW446952B publication Critical patent/TW446952B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
TW088117410A 1998-11-13 1999-10-08 Circuit-arrangement with temperature dependent semiconductor element test and repair logic TW446952B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19852430A DE19852430C2 (de) 1998-11-13 1998-11-13 Schaltungsanordnung mit temperaturabhängiger Halbleiterbauelement-Test- und Reparaturlogik

Publications (1)

Publication Number Publication Date
TW446952B true TW446952B (en) 2001-07-21

Family

ID=7887726

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088117410A TW446952B (en) 1998-11-13 1999-10-08 Circuit-arrangement with temperature dependent semiconductor element test and repair logic

Country Status (6)

Country Link
US (1) US6297995B1 (ja)
EP (1) EP1008858B1 (ja)
JP (1) JP2000156093A (ja)
KR (1) KR100341685B1 (ja)
DE (2) DE19852430C2 (ja)
TW (1) TW446952B (ja)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6488405B1 (en) * 2000-03-08 2002-12-03 Advanced Micro Devices, Inc. Flip chip defect analysis using liquid crystal
JP2002109899A (ja) * 2000-07-26 2002-04-12 Mitsubishi Electric Corp 半導体記憶装置およびそれを備える半導体集積回路装置
US6865694B2 (en) * 2002-04-30 2005-03-08 Texas Instruments Incorporated CPU-based system and method for testing embedded memory
DE10354443B4 (de) * 2003-11-21 2008-07-31 Infineon Technologies Ag Halbleiterbauelementanordnung mit einer Defekterkennungsschaltung
US7496817B2 (en) * 2004-02-20 2009-02-24 Realtek Semiconductor Corp. Method for determining integrity of memory
US20050210205A1 (en) * 2004-03-17 2005-09-22 Chang-Lien Wu Method for employing memory with defective sections
JP4550053B2 (ja) 2004-06-22 2010-09-22 富士通セミコンダクター株式会社 半導体メモリ
NO20042771D0 (no) * 2004-06-30 2004-06-30 Thin Film Electronics Asa Optimering av driftstemperatur i et ferroelektrisk eller elektret minne
EP1640886A1 (en) * 2004-09-23 2006-03-29 Interuniversitair Microelektronica Centrum Method and apparatus for designing and manufacturing electronic circuits subject to leakage problems caused by temperature variations and/or ageing
KR100702300B1 (ko) * 2005-05-30 2007-03-30 주식회사 하이닉스반도체 테스트 제어 회로를 갖는 반도체 메모리 장치
US7765825B2 (en) * 2005-12-16 2010-08-03 Intel Corporation Apparatus and method for thermal management of a memory device
US8082475B2 (en) * 2008-07-01 2011-12-20 International Business Machines Corporation Enhanced microprocessor interconnect with bit shadowing
US20100005335A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Microprocessor interface with dynamic segment sparing and repair
US8234540B2 (en) * 2008-07-01 2012-07-31 International Business Machines Corporation Error correcting code protected quasi-static bit communication on a high-speed bus
US8201069B2 (en) * 2008-07-01 2012-06-12 International Business Machines Corporation Cyclical redundancy code for use in a high-speed serial link
US8245105B2 (en) * 2008-07-01 2012-08-14 International Business Machines Corporation Cascade interconnect memory system with enhanced reliability
US8139430B2 (en) * 2008-07-01 2012-03-20 International Business Machines Corporation Power-on initialization and test for a cascade interconnect memory system
US7895374B2 (en) * 2008-07-01 2011-02-22 International Business Machines Corporation Dynamic segment sparing and repair in a memory system
US8082474B2 (en) * 2008-07-01 2011-12-20 International Business Machines Corporation Bit shadowing in a memory system
US7979759B2 (en) * 2009-01-08 2011-07-12 International Business Machines Corporation Test and bring-up of an enhanced cascade interconnect memory system
US20100180154A1 (en) * 2009-01-13 2010-07-15 International Business Machines Corporation Built In Self-Test of Memory Stressor
KR102123991B1 (ko) 2013-03-11 2020-06-17 삼성전자주식회사 반도체 패키지 및 이를 구비하는 전자 시스템
KR102401882B1 (ko) * 2017-12-04 2022-05-26 에스케이하이닉스 주식회사 메모리의 신뢰성을 향상시킬 수 있는 메모리 시스템 및 그 메모리 관리 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2073916A1 (en) * 1991-07-19 1993-01-20 Tatsuya Hashinaga Burn-in apparatus and method
US5583875A (en) * 1994-11-28 1996-12-10 Siemens Rolm Communications Inc. Automatic parametric self-testing and grading of a hardware system
KR100333720B1 (ko) * 1998-06-30 2002-06-20 박종섭 강유전체메모리소자의리던던시회로

Also Published As

Publication number Publication date
DE19852430A1 (de) 2000-05-25
US6297995B1 (en) 2001-10-02
EP1008858B1 (de) 2004-07-14
EP1008858A3 (de) 2000-07-12
DE59909951D1 (de) 2004-08-19
JP2000156093A (ja) 2000-06-06
EP1008858A2 (de) 2000-06-14
DE19852430C2 (de) 2000-09-14
KR100341685B1 (ko) 2002-06-22
KR20000035292A (ko) 2000-06-26

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