經濟部智慧財產局員工消費合作社印製 441023 A7 _________B7_____ 五、發明說明（/ ) 發明領域： 本發明係關於一種積體電路中銅金屬的製作方法，特別 疋關於一種利用兩種不同光學敏感特性(记阳如¥丨以)的光阻材 質以減少蝕刻次數的雙嵌鑲銅製程。 發明背景： 一般而言，半導體元件隨著積體電‘密度的增加及體積 的縮小，可明顯改善電性動作的速度，並減少電子產品的生 產成本’是以元件尺寸極小化與高積集度，一直是積體電路 作上極為重要的發展方向之一。然而，元件尺寸極小化使 得晶片的表面無法提供足夠面積來製作所需的導線結構，多 層導線結構的需求也就越來越重要，此外，發展優於傳統紹 金屬的新金屬材料，亦是當今迫切需解決的課題。 傳統積體電路製程中’主要利用的鋁（A1)金屬製程， 在進入深次微米領域時，由於鋁金屬電阻值尚不夠低、階梯 覆蓋率隨接觸窗尺寸縮小而變差、應力導致空洞形成及抗電 子遷移（electromigration)不足等問題，將影響到產品的可 靠度，故如今已是面臨到發展新的金屬材料或新的沉積技術 的時代。新的金屬材料中具有先天上優勢的金屬銅（cu) 也開始廣泛的被研究’其優點如：（1)低電阻特性，可提供 較快的傳輸速度及減少電阻·電容延遲時間（Rcdelaytime); (2)良好的抗電子遷移性，避免造成斷路；（3)良好的抗應力 致空洞形成性質等。 然而，因為銅有著不易钮刻的問題，銅金屬製程必須用 一種特殊的方式來進行’也就是所謂的雙嵌鑲(dual _ 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------I ---t--------訂---------線 {請先閱讀脅面之注意事項再填寫本頁) '4 410 2 經濟部智慧財產局R工消費合作社印製 Α7 Β7 五、發明說明（f) damascene)銅製程，先在層間介電層中挖出溝槽後，再填入 銅金屬於溝槽内’最後再以化學機械研磨(CMP)方式將多餘 的銅金屬除去。另一方面’由於銅的游離能很低導致很容易 擴散出來污染了晶圓及環境，因此必須在銅金屬週圍加入一 稱為阻障金屬（barrier metal)的材料解決此一問題。 一般而言’雙鼓鑲(dual damascene)銅製程可分為先開 溝槽(trench first)或是先開介層孔(Via first)兩種方式。請參閱 圖一’為一習知先開介層孔(via flrst)雙嵌鑲(dual damascene) 銅製程的製程剖面圖，在一已完成下層金屬連線8的半導體 基板上，依序形成姓刻終止層12、第一金屬層間介電層μ、 第一抗反射層16、第二金屬層間介電層18以及第二抗反射層 20 ’如圖一A所示，接著，形成介層孔(via)光阻圖案22，進 行第一次姓刻，打開一介層孔的窗口28a，如圖一B所示， 然後，形成溝槽(trench)光阻圖案24，進行第二次蝕刻，打 開一溝槽的窗口28b，如圖一c所示，最後，進行第三次飯 刻’將蝕刻終止層12除去，打開與下層金屬連線8接觸的窗 口，如圖一D所示’相同·的道理，先開溝槽(trench f_雙嵌 鑲銅製程也是類似的作法，只是將圖一B和圖一€的步驟對 調罷了。 上述銅製程的最大缺點是必須經過三次餘刻之後才能完 全打開與下層金屬連線的接觸窗σ，過程十分繁複耗時，無 法有效地應用於積體電路產品的量產之用。 ^紙張尺度適用中國國家標準（CNS)A4規格（21Q χ视公楚-)--- I I---- ^--I! — !訂------- - -線' > (請先閱讀脅面之-注意事項再填寫本頁) 4/11 0 2 3 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（j) 故本發明揭露一種新穎的雙嵌鑲(dual damascene)銅製 程，可同時打開溝槽以及介層孔的窗口，大幅縮短製程所需 要耗費的時間。 發明之概述： 本發明之主要目的是提供一種新穎的雙嵌鑲付皿1 damascene)銅製程’能夠大幅縮短製程所需要耗費的時間。 本發明之次要目的是提供一種經濟簡易的雙嵌鑲(dual damascene)銅製程’可同時打開溝槽以及介層孔的窗口，減 少钱刻的次數。 本發明係使用下列步驟來達到上述之各項目的：首先， 提供一表面已形成有一金屬層間介電層、一蝕刻終止層以及 下層金屬連線的半導體基板’接著利用兩種不同光學敏感特 性(sensitivity)的光阻分別定義出介層孔與溝槽的光阻圖案， 然後分別進行兩次蝕刻將所述光阻圖案的輪廓複製到所述金 屬層間介電層上，以及將所述兹刻終止層除去，打開與下層 結構接觸的窗口’最後形成一銅金屬層以填滿所述介層孔與 溝槽，並除去基板表面多餘的銅金屬層，本發明所述之減少 蝕刻次數的雙嵌鑲銅製程於焉完成。 本發明的重點在於第一光阻和第二光阻必須有著不同光 學敏感特性，故在進行第二次微影時並不會改變原先已形成 的介層孔圖案’在介層孔與溝槽的光阻圖案都已定義完成的 情況下’故伽J可以一次吃到钱刻終止層，直接將光阻圖案 的輪靡複製於金屬層間介電層’減少了一次兹刻步驟，進而 降低了生產成本。 (諳先閱讀脅面之注意事項再填寫本頁> --------訂"--------*3^ 4 12-#刻終止層 16-第一抗反射層 20-第二抗反射層 28b-溝槽的窗口 1 di刻終止層 116-第一抗反射層 120-第二抗反射層 124-第二光阻 如同習知技藝一般，在一已〜 A7 五、發明說明（， 圖式簡要說明： 圖一 A到圖一 D為習知技藝雙欲鑲銅製程的製裎卑 示意圖。 '^面 圖一 A到圖二c為本發明實施例雙嵌鑲鋼製 剖面示意圖。 ㈣製程 圖號說明： 8-下層金屬連線 14-第一金屬層間介電層 18-第二金屬層間介電層 28a_介層孔的窗口 108-下層金屬連線 1H-第一金屬層間介電層 118-第二金屬層間介電層 122-第一光阻 發明詳細說明： 首先，請參閱圖二A〜C， 成下層結構(通常是下層金屬連線，也可以是其他的電性ς 件)108的半導體基板上，依序形成蝕刻終止層112、第—金 屬層間介電層114、第-抗反射層ι16、第二金間介電層 118以及第二抗反射層12〇，其中所述蝕刻終止層112是與金 屬層間介電層(IMD)相比有較高蝕刻選擇比的材料，通常是 氮化矽’所述金屬層間介電層(IMD)通常是化學氣相沉積 (CVD)或旋塗（spin-coating)形成之氧化層，或為其他低 介電係數（low k)材質’而所述抗反射層則通常是氧化i 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 441023 A7 _________B7_____ V. Description of the Invention (/) Field of the Invention: The present invention relates to a method for manufacturing copper metal in integrated circuits, and particularly to a method that utilizes two different optically sensitive characteristics ( A double-inlay copper process that remembers the photoresist material such as ¥ 丨 to) to reduce the number of etchings. Background of the Invention: Generally speaking, with the increase of the density of the semiconductor device and the reduction in volume, the semiconductor device can significantly improve the speed of electrical operation and reduce the production cost of electronic products. Degree has always been one of the most important development directions for integrated circuits. However, the miniaturization of components has made the surface of the wafer unable to provide enough area to make the required wire structure, and the demand for multilayer wire structures has become increasingly important. In addition, the development of new metal materials that are superior to traditional Shao metal is also today. Urgent issues to be addressed. In the traditional integrated circuit manufacturing process, the aluminum (A1) metal process is mainly used. When entering the deep sub-micron field, because the aluminum metal resistance value is not low enough, the step coverage becomes worse as the size of the contact window is reduced, and stress causes voids to form. And the problem of insufficient electron migration (electromigration) will affect the reliability of the product, so it is now facing the era of developing new metal materials or new deposition technologies. Among the new metal materials, copper (cu), which has an inherent advantage, has also been widely studied. Its advantages are as follows: (1) Low resistance characteristics, which can provide faster transmission speed and reduce the resistance and capacitance delay time (Rcdelaytime). (2) Good resistance to electron migration to avoid breaking; (3) Good resistance to stress-induced void formation. However, because copper has the problem of being difficult to be engraved, the copper metal process must be performed in a special way, which is the so-called dual inlay (dual _ 2) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) --------- I --- t -------- Order --------- line {Please read the precautions for the noodle before filling this page) '4 410 2 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, R Industrial Consumer Cooperative, A7, B7 V. Description of Invention (f) damascene) Copper process, after trenches are dug out in the interlayer dielectric layer, and then copper metal is filled in the trenches. Finally, the excess copper metal is removed by chemical mechanical polishing (CMP). On the other hand, because copper's free energy is very low, it easily diffuses and pollutes the wafer and the environment. Therefore, a material called barrier metal must be added around the copper metal to solve this problem. Generally speaking, the dual damascene copper process can be divided into two methods: trench first or via first. Please refer to FIG. 1 for a conventional process cross-sectional view of a via flrst dual damascene copper process. A semiconductor substrate on which the lower metal connection 8 has been completed is sequentially formed with a final engraved termination. The layer 12, the first metal interlayer dielectric layer μ, the first anti-reflection layer 16, the second metal interlayer dielectric layer 18, and the second anti-reflection layer 20 'are shown in FIG. 1A. Then, a via hole is formed (via ) The photoresist pattern 22 is engraved for the first time, and a window 28a of a via hole is opened, as shown in FIG. 1B. Then, a trench photoresist pattern 24 is formed, and a second etching is performed to open a trench. The slot window 28b is shown in FIG. 1c. Finally, a third meal is performed to “remove the etching stop layer 12 and open the window that is in contact with the underlying metal line 8. As shown in FIG. 1D, the same truth is true.” First, the trench (trench f_ double inlay copper process is similar, except that the steps of Figure 1B and Figure 1 € are reversed. The biggest disadvantage of the above copper process is that it must be opened three times after it is fully opened and The contact window σ of the lower metal connection is very complicated and time-consuming. The method is effectively applied to the mass production of integrated circuit products. ^ The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21Q χ as the public Chu-) --- I I ---- ^-I! — ! Order ---------line '> (Please read the threat-notes before filling out this page) 4/11 0 2 3 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation of the invention (j) Therefore, the present invention discloses a novel dual damascene copper process, which can simultaneously open the windows of the trench and the via hole, thereby greatly reducing the time required for the process. Summary of the invention: The main purpose is to provide a novel double-damascene 1 damascene) copper process, which can greatly reduce the time required for the process. A secondary object of the present invention is to provide an economical and simple dual damascene copper process' that can simultaneously open the window of the trench and the via of the interlayer, thereby reducing the number of times of money engraving. The present invention uses the following steps to achieve the above-mentioned objects: First, a semiconductor substrate having a metal interlayer dielectric layer, an etch stop layer and an underlying metal connection formed on the surface is provided. Then, two different optically sensitive characteristics are used ( The photoresist of the sensitivity) respectively defines the photoresist pattern of the hole and the trench of the interlayer, and then performs two etchings to copy the outline of the photoresist pattern to the interlayer dielectric layer, and The termination layer is removed, and the window in contact with the underlying structure is opened. Finally, a copper metal layer is formed to fill the via holes and trenches, and the excess copper metal layer on the surface of the substrate is removed. The inlaying copper process is completed in 焉. The main point of the present invention is that the first photoresist and the second photoresist must have different optically sensitive characteristics, so the second photolithography will not change the previously formed via hole pattern. When the photoresist patterns have been defined and completed, 'Gamma J can eat the money engraving termination layer at one time, and directly copy the photoresist pattern's turn to the metal interlayer dielectric layer'. This reduces the number of engraving steps, thereby reducing Cost of production. (谙 Please read the precautions for the flank surface before filling in this page> -------- Order " -------- * 3 ^ 4 12- # 刻 止 层 16- 第一 Anti-reflective Layer 20-second anti-reflection layer 28b-window window 1 di engraved termination layer 116-first anti-reflection layer 120-second anti-reflection layer 124-second photoresistor as in the conventional art 5. Description of the invention (, Brief description of the drawings: Figures 1A to 1D are schematic diagrams of the manufacturing process of the double copper inlaying process of the conventional art. '^ Figures 1A to 2c are dual-embedded embodiments of the present invention Schematic diagram of the section made of steel. ㈣ Process drawing number description: 8-lower metal connection 14-first metal interlayer dielectric layer 18-second metal interlayer dielectric layer 28a_window of via 108-lower metal connection 1H -The first metal interlayer dielectric layer 118-the second metal interlayer dielectric layer 122-The first photoresist invention is described in detail: First, please refer to FIGS. 2A to 2C to form a lower layer structure (usually a lower metal connection, or Are other electrical components) 108 on the semiconductor substrate, an etch stop layer 112, a first-metal interlayer dielectric layer 114, a first anti-reflection layer ι16, and a second intermetal dielectric are sequentially formed 118 and the second anti-reflection layer 120, wherein the etch stop layer 112 is a material having a higher etching selectivity compared to a metal interlayer dielectric layer (IMD), and is usually silicon nitride 'the metal interlayer dielectric Layer (IMD) is usually an oxide layer formed by chemical vapor deposition (CVD) or spin-coating, or other low-k material, and the anti-reflection layer is usually an oxide. This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)
I 訂 ♦ I I 線 441023 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（Γ) 化矽（oxynitride)，也可以是氮化鈦（TiN)或是非晶矽 (Amorphous Silicon ; α-Si)。當然，若是蝕刻能經夠精確控 制的話’也可以將蝕刻終止層112省去不用，或者甚至單一 層的抗反射層及金屬層間介電層就足夠了。 接下來的步驟為本發明之重要特徵，請參閱二A及圖二 B，分兩次捉塗上不同光學敏感特性(记肥出“以)的光阻材質 122、124 ’先以第一光阻122進行第一次微影以曝出介層孔 的圖案，如圖二B所示，接著再以第二光阻進行第二次 微影以曝出溝槽的圖案，如圖二8所示。本案的重點在於第 -光阻122和第二光阻124必須有著不同光學敏感特性，故在 進行第二次微影時並不會改變原先已形成的介層孔圖案，舉 例而言，所述第一光阻〗22和第二光阻124的材質可以分別是 I-line^365nm)及深紫外線(Duv)(>248nm)的光阻，或者 疋更新式的掃瞄曝光機(scamer)(x=193nm)的光阻。 "月參閱一C，接下來利用圖二a所形成的光阻圖案為幕 罩進行蝕刻，以挖出雙嵌鑲(dualdamascene)銅製程所須的凹 槽，因為介層孔與溝槽的光阻圖案都已形成，另—方面，在 银刻的過程中裸露出的光阻同時不可避免地會被消耗掉，所 以蝕刻可以一次吃到蝕刻終止層，直接將光阻 製於金屬㈣介上，紐，如㈣知技藝般， 二次侧’紐刻終止層除去，打開與下層金屬連線接觸的 窗口。 最後，就可以在形成的凹槽内填入阻障層及鋼金屬（未 於圖中標出），再將將多餘的銅金屬利用化學機械研磨$ I ^ i I -----^---------線 (靖先閱讀货面之注5-?事項再填寫本頁) 6 4 41 0 2 3 A7 五、發明說明（厶） 方式除去，本發明所述之減少蝕刻次數的雙嵌鑲銅製程於焉 完成。所述阻障層通常是鈕金屬（Ta)或氮化钽（TaN)結 構’但也有人利用其他的金屬如：氮化鶴（WNX)、氮石夕化 纽（TaSiN)、氮石夕化鈦（TiSiN)、氣石夕化鶴（WSiN)或 八他具上述金屬之四元化合物（temary⑶爪口加以）結構， 其厚度係介於50人至200A之間。所述銅金屬通常先利用CVD 法或IMP法形成一銅金屬成核層於所述阻障層上，再利用電 化學沉積（Electro-Chemical Deposition; ECD) —銅金屬層 填滿所述溝槽。 利用本發明製作積體電路中銅之阻障金屬層具有下列的 優點： 1·本發明係先形成了介層孔與溝槽兩者的光阻圖案， 所以蝕刻可以一次吃到蝕刻終止層，直接將光阻圖 案的輪廓複製於金屬層間介電層上。 z本發明係提供一種經濟簡易的雙嵌鑲(dua丨damasc如^ 銅製程’可同時打開溝槽以及介層孔的窗口，減少 姑刻的次數。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而作 些微的改變與調整’仍將不失本發明之要義所在’亦不脫離 本發明之精神和範圍，故都應視為本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 本纸張尺度適用中國國豕·標準（CNS)A4規格（2】0 X 297公爱I order ♦ II line 441023 Printed by A7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (Γ) Oxynitride, which can also be TiN or Amorphous Silicon; α-Si ). Of course, if the etching can be accurately controlled, the etching stop layer 112 may be omitted or even a single-layer anti-reflection layer and a metal interlayer dielectric layer are sufficient. The next step is an important feature of the present invention. Please refer to Figure 2A and Figure 2B. Capture and apply the photoresist material 122, 124 with different optically sensitive characteristics (marked with "") twice. The resist 122 performs the first lithography to expose the pattern of the via hole, as shown in FIG. 2B, and then uses the second photoresist to perform the second lithography to expose the trench pattern, as shown in FIG. 2-8. The focus of this case is that the first photoresist 122 and the second photoresist 124 must have different optically sensitive characteristics, so the second lithography will not change the previously formed via pattern of the interlayer, for example, The materials of the first photoresistor 22 and the second photoresistor 124 may be I-line ^ 365nm) and deep ultraviolet (Duv) (> 248nm) photoresist, or a newer scanning exposure machine ( scamer) (x = 193nm). " Refer to 1C, and then use the photoresist pattern formed in Figure 2a as a curtain to etch to dig out the dualdamascene copper process. Grooves, because the photoresist patterns of the vias and trenches have been formed. On the other hand, the photoresist exposed during the silver engraving process does not Avoidance will be consumed, so the etch stop layer can be eaten at one time, and the photoresist is directly restrained on the metal substrate. As is known in the art, the secondary side 'knot stop layer is removed, and the lower metal is opened. Connect the contact window. Finally, you can fill the formed groove with a barrier layer and a steel metal (not shown in the figure), and then use chemical mechanical polishing of the extra copper metal. I I ^ i I- ---- ^ --------- line (Jing first read the note 5-? On the front of the goods before filling in this page) 6 4 41 0 2 3 A7 V. Description of the invention (厶) The method is removed, this The double inlay copper process for reducing the number of etchings according to the invention is completed in yttrium. The barrier layer is usually a button metal (Ta) or tantalum nitride (TaN) structure ', but others also use other metals such as: nitrided crane (WNX), Nitrogen oxide (TaSiN), Nitrogen oxide (TiSiN), Gas-stone chemical crane (WSiN), or other quaternary compounds of the above metal (temary ⑶ claw mouth) structure, its thickness It is between 50 and 200 A. The copper metal is usually formed by a CVD method or an IMP method to form a copper metal nucleation layer on the barrier layer. And then use Electro-Chemical Deposition (ECD) —a copper metal layer to fill the trenches. The use of the present invention to make copper barrier metal layers in integrated circuits has the following advantages: 1. The present invention is the first The photoresist patterns of both the vias and the trenches of the interlayer are formed, so that the etching stop layer can be eaten at one time, and the outline of the photoresist pattern can be directly copied on the interlayer dielectric layer. The present invention provides an economical and simple Double inlay (dua 丨 damasc such as ^ copper process) can simultaneously open the window of the trench and the via hole, reducing the number of engravings. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that appropriate and slight changes and adjustments will not lose the essence of the present invention. 'It does not depart from the spirit and scope of the present invention, so it should be regarded as the further implementation status of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. This paper size is applicable to China National Standard · Standard (CNS) A4 (2) 0 X 297