''4443 4 4 I五、發明說明（u —一 本發明是有關於半導體積體電路（semiconductc)r ICs)之製程技術，特別是有關於雙鑲嵌結構（duai damascene )的製作方法，能夠消除底層蝕刻停止層 (bottom stop layer)姓穿的問題。 近年來’為了配合積體電路元件尺寸縮小化的發展以 及提高元件操作速度的需求，具有低電阻常數和高電子遷 移阻抗的鋼金屬，已逐漸被應用來作為金屬内連線的材 質，取代以往的鋁金屬製程技術。銅金屬的鑲嵌式 (damascene)内連線技術，不僅可達到内連線的縮小化並 ，可減少RC時間延遲，同時也解決了金屬銅蝕刻不易的問 題，因此已成為現今多重内連線主要的發展趨勢。 以下利用第圖所示用以填入銅内連線之雙鑲 嵌結構的製程剖面示意圖，來說明習知技術，此製程先蝕 刻接觸孔（via)再形成溝槽（trench)，亦可稱為c〇unter bored製程。 首先，請參照第1A圖，形成該剖面圖的步驟為，在形 成有導電區域12(例如銅内連線）的半導體基底1〇上依序形 成一蝕刻停止層14、金屬間介電層16、蝕刻停止層18、金 f間介電層20，然後選擇性蝕刻上述各層，直到露出蝕刻 停止層14為止，以形成接觸孔22, 22。 然後，請參照第1 B圖，塗佈一層有機防反射材料 ARC(亦稱為底層防反射材料_BARC)，其填入上述接觸孔 22, 22的底部’並且延伸於金屬間介電層2〇的表面，塗佈 防反射材料ARC的目的在於，當作後續溝槽蝕刻步驟之防'' 4443 4 4 I. V. INTRODUCTION TO THE INVENTION (u-This invention is a process technology of semiconductor integrated circuits (ICs), especially the manufacturing method of dual damascene, which can eliminate The problem of bottom stop stop layer penetration. In recent years, in order to meet the development of the reduction in the size of integrated circuit components and the need to increase the speed of component operation, steel metals with low resistance constants and high electron migration resistance have gradually been used as materials for metal interconnects, replacing the past. Aluminum metal process technology. The damascene interconnect technology of copper metal can not only reduce the interconnect size and reduce the RC time delay, but also solve the problem of difficult copper etching, so it has become the main issue of multiple interconnects today. Development trend. The following uses the schematic cross-sectional process diagram of the dual damascene structure to fill the copper interconnects shown in the figure below to illustrate the conventional technology. This process first etches the contact hole (via) and then forms the trench (also known as trench). c〇unter bored process. First, referring to FIG. 1A, the step of forming the cross-sectional view is to sequentially form an etch stop layer 14 and an intermetal dielectric layer 16 on the semiconductor substrate 10 on which a conductive region 12 (for example, a copper interconnect) is formed. , An etch stop layer 18, a gold-f dielectric layer 20, and then selectively etch the above layers until the etch stop layer 14 is exposed to form contact holes 22, 22. Then, referring to FIG. 1B, a layer of organic anti-reflection material ARC (also referred to as the bottom anti-reflection material_BARC) is coated, which is filled into the bottom of the above-mentioned contact holes 22, 22 'and extends to the intermetal dielectric layer 2 The surface of 〇 is coated with anti-reflection material ARC for the purpose of preventing subsequent trench etching steps.
第5頁 4443 4 4 五、發明說明（2) 钱保護層，用來避免蝕刻停止層14與導電區域12被蝕穿。 接著’請參照第1 C圖，利用傳統微影技術進行塗佈深 紫外線（deep UV)光阻材料、曝光、顯影、烘烤等步驟， 以形成溝槽蝕刻用的光阻圖案24。然後，利用上述光阻圖 案24當作钱刻罩幕，並且利用蝕刻步驟去除金屬間介電層 20表面的防反射材料ARC以及金屬間介電層2〇，直到露出 姓刻停止層18為止’其次，去除剩餘之防反射材料ARc， 以形成如第ID圖所示之溝槽3〇以及雙鑲嵌結構DD。 然而’由於上述有機防反射材料ARC具有高黏度等特 性，不易在接觸孔22, 22之内填入太厚的防反射材料ARc， 並且蝕刻溝槽30的步驟必須先將金屬間介電層2〇表面的防 反射材料ARC蝕刻掉（請參照第1 c圖），此將導致接觸孔22, 22内的防反射材料ARC變得非常薄，使保護效果太受影 響’往往造成如第1D圖所示之凹陷AC。 有鑑於上述習知技術的問題，本發明的目的在於提供 一種雙鑲嵌結構的製作方法，利用負型光阻材料當作防钱 保護結構’以確實防止底層蝕刻停.止層被蝕穿，進而提高 產品良率。 根據上述目的，本發明提供一種雙鑲嵌結構的製作方 法’適用於具有導電區域的半導體基底，且上述雙镶叙許 構的製作方法包括下列步驟：在上述半導體基底上依序^ 成一第1蝕刻停止層、第i介電層、第2蝕刻停止層以及第2 介電層；選擇性蝕刻上述第2介電層、第2蝕刻停止層及第 1介電層直到露出第1蝕刻停止層為止，以在上述導電區域Page 5 4443 4 4 V. Description of the invention (2) The money protection layer is used to prevent the etching stop layer 14 and the conductive region 12 from being eroded. Next, please refer to FIG. 1C, using a conventional lithography technique to apply a deep UV photoresist material, exposure, development, baking and other steps to form a photoresist pattern 24 for trench etching. Then, the photoresist pattern 24 is used as a mask for money engraving, and the anti-reflection material ARC on the surface of the intermetal dielectric layer 20 and the intermetal dielectric layer 20 are removed by an etching step until the engraved stop layer 18 is exposed. Next, the remaining anti-reflection material ARc is removed to form a trench 30 and a dual damascene structure DD as shown in FIG. ID. However, 'because the above-mentioned organic anti-reflection material ARC has high viscosity and other characteristics, it is not easy to fill too thick an anti-reflection material ARc into the contact holes 22, 22, and the step of etching the trench 30 must first be an intermetal dielectric layer 2 〇The surface of the anti-reflection material ARC is etched away (please refer to Figure 1c), which will cause the anti-reflection material ARC in the contact holes 22, 22 to become very thin, which will affect the protection effect too often. Depression AC shown. In view of the problems of the above-mentioned conventional technology, an object of the present invention is to provide a method for manufacturing a dual-mosaic structure, which uses a negative photoresist material as a money protection structure to prevent the bottom layer from being stopped. Improve product yield. According to the above object, the present invention provides a manufacturing method of a dual damascene structure, which is applicable to a semiconductor substrate having a conductive region, and the manufacturing method of the dual damascene structure includes the following steps: sequentially forming a first etching on the semiconductor substrate Stop layer, i-th dielectric layer, second etch stop layer, and second dielectric layer; selectively etch the second dielectric layer, second etch stop layer, and first dielectric layer until the first etch stop layer is exposed To the above conductive area
第6頁 444344 五、發明說明（3) 上接觸?L;塗佈-填入上述接觸孔的 以佯Si層，對上述接觸孔區域之該負型光阻層進行曝光 構。 廣乂屯成一溝槽，而構成雙鑲嵌結 第2姓Ί雙鑲嵌結構的製作方法，纟中第1蝕刻停止層及 層及第1 ϊ ΐ :可以是氮化矽或氮氧化矽層，並且第1介電 層及第2介電層可以是二氧化矽。 =者，上述之雙鑲嵌結構的製作方法，其中形成上述 溝槽後，最好更包括去除防蝕保護結構的步驟。 根據上述目的，本發明提供另一種雙鑲嵌結構的製作 適用於具有導電區域的半導體基底，且上述雙鑲嵌 开 :的製作方法包括下列步驟：在上述半導體基底上依序 $成^第1蝕刻停止層、第1介電層、第2姓刻停止層以及 一"電層，在上述第2介電層上塗佈一正型光阻層丨透過 :先罩對該正型光阻進行曝光、顯影以形成一正型光阻罩 棊，利用上述正型光阻罩幕為遮蔽物，並且蝕刻上述第2 介電層、第2钱刻停止層及第1介電層直到露出第工姓刻停 止層為止，以在上述導電區域相對位置上方形成一接觸 孔；去除上述正型光阻罩幕；塗佈一填入上述接觸孔的負 里光阻層，透過該光罩對該負型光阻層進行曝光顯影以 在該接觸孔内形成一防蝕保護結構；以及選擇性蝕刻上述 第2介電層直到露出第2蝕刻停止層，以形成—溝槽，而 成雙鑲嵌結構。Page 6 444344 V. Description of the invention (3) Upper contact? L; coating-filling the contact hole with a 佯 Si layer, and exposing the negative photoresist layer in the contact hole area. The method of making a double-mosaic junction into a trench and forming a double-mosaic structure with a double-mosaic structure. The first etch stop layer and layer and the first ϊ in the 纟: can be a silicon nitride or silicon oxynitride layer, and The first dielectric layer and the second dielectric layer may be silicon dioxide. In other words, in the method for manufacturing the dual damascene structure described above, it is preferable to further include a step of removing the anti-corrosion protection structure after the grooves are formed. According to the above object, the present invention provides another dual damascene structure suitable for manufacturing a semiconductor substrate having a conductive region, and the above dual damascene fabrication method includes the following steps: sequentially forming the first etching stop on the semiconductor substrate Layer, the first dielectric layer, the second engraved stop layer, and an " electrical layer. A positive photoresist layer is coated on the second dielectric layer. 丨 Transmission: First mask the positive photoresist to expose it. 2. Develop to form a positive photoresist mask, use the positive photoresist mask as a shield, and etch the second dielectric layer, the second stop layer, and the first dielectric layer until the first working name is exposed. Until the stop layer is etched, a contact hole is formed above the relative position of the conductive area; the positive photoresist mask is removed; a negative photoresist layer filled in the contact hole is coated, and the negative type is passed through the photomask. The photoresist layer is exposed and developed to form an anti-corrosion protection structure in the contact hole; and the second dielectric layer is selectively etched until the second etch stop layer is exposed to form a trench, forming a dual damascene structure.
第7頁 444344 j五、發明說明（4) 為了讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附囷式，作詳細說 明如下： 圖式之簡單說明： 第1A-1D圖為習知用以填入銅内連線之雙鑲嵌結構的 製程剖面示意圖。 第2A〜第2F圖為根據本發明實施例之雙鑲嵌結構的製 程剖面示意圖。 符號之說明 100〜半導體（矽）基底；120〜導電區域；140、180〜蝕 刻停止層；160、200〜金屬間介電層；220〜接觸孔；240〜 正型光阻罩幕；260〜光罩；260a〜不透光區；260b〜透光 區；270〜負型光阻層；270a〜防蝕保護結構；280〜溝槽蝕 刻用光阻圖案；300〜溝槽：DD〜雙鑲嵌結構。 實施例 以下利用第2A~第2F圖所示之雙鑲嵌結構的製程剖面 圖，以更詳細地說明本發明。 首先’請參照第2A圖，形成該剖面圖的步驟為，在形 成有導電區域120(例如銅内連線）的半導體基底1〇〇上依序 形成一蝕刻停止層1 4 0、金屬間介電層1 6 〇、蝕刻停止層 180、金屬間介電層200、及一正型光阻層（亦即，曝光部 分能夠以顯影方式去除、而未曝光部分能夠保留之光阻 層）’然後透過具有不透光區260a與透光區$60b之光罩 260 ’對上述正型光阻層選擇性地曝深紫外光（deepPage 7 444344 j V. Description of the invention (4) In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is given below, and it is described in detail with the accompanying formula as follows: : Brief description of the drawings: Figures 1A-1D are schematic cross-sectional views of the manufacturing process of the dual-damascene structure used to fill copper interconnects. 2A to 2F are schematic cross-sectional views of a process of a dual mosaic structure according to an embodiment of the present invention. Explanation of symbols 100 ~ semiconductor (silicon) substrate; 120 ~ conductive area; 140, 180 ~ etch stop layer; 160, 200 ~ intermetal dielectric layer; 220 ~ contact hole; 240 ~ positive photoresist mask; 260 ~ Photomask; 260a ~ opaque area; 260b ~ transparent area; 270 ~ negative photoresist layer; 270a ~ anti-corrosion protection structure; 280 ~ photoresist pattern for trench etching; 300 ~ groove: DD ~ dual mosaic structure . EXAMPLES The present invention will be described in more detail with reference to the process cross-sectional views of the dual mosaic structure shown in Figs. 2A to 2F. First, please refer to FIG. 2A. The step of forming the cross-sectional view is to sequentially form an etch stop layer 140, an intermetallic interlayer on a semiconductor substrate 100 on which a conductive region 120 (such as a copper interconnect) is formed. The electrical layer 16, the etch stop layer 180, the intermetal dielectric layer 200, and a positive-type photoresist layer (that is, a photoresist layer in which the exposed portion can be removed by development and the unexposed portion can be retained) ' The positive photoresist layer is selectively exposed to deep ultraviolet light through a mask 260 'having an opaque area 260a and a transparent area $ 60b.
第8頁 4443 4 4 五、發明說明（5) ultraviolet ;DUV) ’再進行顯影步驟以形成正型光阻罩 幕240。然後’利用上述正型光阻罩幕240當作遮蔽物’並 且蝕刻上述金屬間介電層2〇〇、蝕刻停止層1 80、金屬間介 電層160 ’以在上述導電區域120的相對位置上方形成接觸 孔2 2 0，2 2 0。接著’利用傳統乾或溼蝕刻方式以去除正型 光阻罩幕240，而構成如第2B圖所示之剖面圖。 其次’請參照第2C圖，利用旋轉塗佈方式（sp i η coat ing)全面性地形成一負型光阻層27〇(亦即未曝光部分 能夠以顯影方式去除、而曝光部分能夠保留之光阻層）， 由於負型光阻層之材料特性（例如黏度較小）的關係，所以 能夠填滿上述接觸孔220, 220之内，並且延伸於金屬間介 電層200的表面。然後，透過第2人圖所示之相同光罩26〇對 負型光阻層270選擇性地曝紫外光，之後，進行顯影步驟 以形成如第2D圖所示之防蝕保護結構27〇a。 緊接著’請參照第2 E圏，利用傳統微影技術進行塗佈 深紫外線（deep UV)光阻材料、曝光、顯影、烘烤等步 驟’以形成溝槽蝕刻用的光阻圖案28〇。然後，利用上述 光=圖案280當作蝕刻罩幕，並且利用蝕刻步驟去除未被 覆蓋之金屬間介電層2〇〇，直到露出蝕刻停止層為止， 其-人’利用氧電漿等方式去除由負型光阻材料構成之防蝕 保護結構270a，以形成如第2F圖所示之溝槽3〇〇以及 嵌結構DD。 後續還包括去除接觸孔22〇, 22〇露出部分蝕刻停止層 140 ’以及在雙鑲嵌結構DD之内填入銅等金屬材料的步驟Page 8 4443 4 4 V. Description of the invention (5) ultraviolet (DUV) 'Then, a developing step is performed to form a positive photoresist mask 240. Then 'use the positive photoresist mask 240 as a shield' and etch the intermetallic dielectric layer 200, the etch stop layer 180, and the intermetallic dielectric layer 160 'to the relative position of the conductive region 120. Contact holes 2 2 0, 2 2 0 are formed above. Next, a conventional dry or wet etching method is used to remove the positive photoresist mask 240, and a sectional view shown in FIG. 2B is formed. Secondly, please refer to FIG. 2C, using a spin coating method (sp i η coating ing) to comprehensively form a negative photoresist layer 27 ° (that is, the unexposed portion can be removed by development, and the exposed portion can be retained. (Photoresist layer), due to the material characteristics (such as low viscosity) of the negative photoresist layer, it can fill the contact holes 220, 220 and extend on the surface of the intermetal dielectric layer 200. Then, the negative photoresist layer 270 is selectively exposed to ultraviolet light through the same mask 26 as shown in the second figure, and then, a developing step is performed to form a corrosion protection structure 27 o as shown in FIG. 2D. Next, please refer to step 2E 圏, using conventional lithography technology to apply deep UV photoresist material, steps of exposure, development, and baking to form a photoresist pattern 28 for trench etching. Then, the above-mentioned light = pattern 280 is used as an etching mask, and the uncovered intermetal dielectric layer 200 is removed by an etching step until the etching stop layer is exposed, which is removed by an oxygen plasma or the like. The anti-corrosion protection structure 270a made of a negative photoresist material is used to form the trench 300 and the embedded structure DD as shown in FIG. 2F. The subsequent steps also include the steps of removing the contact holes 22, 22 to expose a part of the etch stop layer 140 ', and filling a metal material such as copper within the dual damascene structure DD.
4443 44 五、發明說明（6) (圖未顯示）。 發明特徵與效果 本發明採用負型光阻材料構成之防蝕保護結構 2 70a ’不需要增加光罩即可容易地以曝光、顯影的方式去 除接觸孔220，220以外區域的負型光阻層，而保留足夠厚 度的防蝕保護結構270a，再者，由於負型光阻低黏度的特 性，可填滿接觸孔2 20，220，而確保其保護效果，因此能 釣避免底層蝕刻停止層1 4 0被蝕穿的問題，進而提高產品 良率。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内’當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 第10頁4443 44 V. Description of the invention (6) (not shown). Features and effects of the present invention The present invention uses a negative-type photoresist material to form a corrosion protection protective structure 2 70a ', which can easily remove the negative photoresist layer in areas other than the contact holes 220 and 220 by exposing and developing without adding a photomask. While retaining a sufficient thickness of the anti-corrosion protection structure 270a, in addition, due to the low viscosity of the negative photoresistor, it can fill the contact holes 2 20, 220 to ensure its protection effect, so it can avoid the bottom etching stop layer 1 4 0 The problem of erosion is to improve the product yield. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. Page 10