TWI247379B - Manufacturing method of double damascene structure - Google Patents

Manufacturing method of double damascene structure Download PDF

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Publication number
TWI247379B
TWI247379B TW90120219A TW90120219A TWI247379B TW I247379 B TWI247379 B TW I247379B TW 90120219 A TW90120219 A TW 90120219A TW 90120219 A TW90120219 A TW 90120219A TW I247379 B TWI247379 B TW I247379B
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Taiwan
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layer
photoresist
plug
contact hole
dielectric layer
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TW90120219A
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Chinese (zh)
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Chung-Hsiu Cheng
Pin-Yi Hsin
Ming-Chyi Liu
Chih-Hsien Hsu
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Taiwan Semiconductor Mfg
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Publication of TWI247379B publication Critical patent/TWI247379B/en

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Abstract

This invention provides a manufacturing method of double damascene structure, which includes steps of first forming a first etch stop layer, a first dielectric layer, a second etch stop layer, and a second dielectric layer upon a semiconductor substrate sequentially; spreading a positive photoresist upon the second dielectric layer; performing to expose and develop the positive photoresist in formation of a positive photoresist mask upon the position intended for formation of contact holes; using the positive photoresist mask as a shield to etch the second dielectric layer, the second etch stop layer and the first dielectric layer until the first etch stop layer is exposed to form a contact hole upon a position corresponding to the aforementioned conducting area; next forming a photoresist plug in the aforementioned contact hole; coating a positive photoresist layer upon the photoresist plug and the second dielectric layer, which the sensing properties of the positive dielectric layer is different from that of the photoresist plug; adopting a lithography process to define the aforementioned positive photoresist layer to form a trench pattern to expose the photoresist plug and the second dielectric layer which, the photoresist plug is not affected by the mentioned lithography process; and employing the trench pattern and the photoresist plug as a mask to etch the second dielectric layer until the second etch stop layer is exposed to form a trench; and lastly removing the photoresist plug in the contact hole to form a double-damascene structure.

Description

1247379 Λ 曰 _修正 案號 90120WQ 五、發明說明(1) 本發明是有调於半導體積體雷 .1247379 Λ 曰 _ Amendment Case No. 90120WQ V. Description of the Invention (1) The present invention is tuned to a semiconductor integrated body.

Cs)之衣釭技術,特別是有關於雙鑲嵌結 damascene)的製作方法,Α 可 μ 、 層(bottom st〇p layer)所造^核衫底層㈣停止 孰征俅邊層的過程中產生孔洞。 年來’為了配合積體電路 菸接古々此4品於、太ώ a U 1干人T、%小化的發展以 及&冋7C件操作速度的需求,具有 移阻抗的銅金屬,已逐漸被岸用來你:::數和南電子遷 „ ^ t / 所破應用來作為金屬内連線的材 貝’取代以在的紹金屬製程技術。銅金屬的鑲嵌式 (d a m a s c e n e )内連、線技4奸,尤禮可、去艺,上、 、b 不僅可達到内連線的縮小化並 且可減少RC時間延遲,同時也解決了金屬銅勉刻不易的問 題,因此已成為現今多重内連線主要的發展趨勢。 請爹照第1圖,其為習知技術形成之雙鑲嵌結構剖面 圖,該結構在填入銅金屬以及施以銅金屬平坦化之後即 成銅金屬内連線。 形成上述第1圖的步驟為,在形成有導電區域丨2 (例如 銅内連線)的半導體基底1 〇上依序形成蝕刻停止層丨4、介 電層16、蝕刻停止層18、介電層20、防反射遮蔽層22,狹 後利用傳統的微影技術以及選擇性蝕刻上述防反射遮蔽層 2 2、介電層2 0、蝕刻停止層1 8、介電層丨6直到露出上述蝕 刻停止層1 4為止’以形成接觸孔2 4。接著,利用旋塗 (spin coating)的方式在上述接觸孔24填入例如伸芳香基 醚類聚合物(polyUrylene ether) p〇lymer),具體例 ^ Schumacher公司所製造的PAE-2或是Allied Signal公司所 製造的FLARE、H0SP ' L0SP等有機聚合物材料,以當作後 0503-6582TWFl.ptc 第5頁 1247379 五、發明說明(2) 續蝕刻步驟的犧牲保護會2 6 1來避免上述底層蝕刻声 1 4受損。 曰 然而,接觸孔24的尺寸已逐漸縮小至〇. 3 /zm甚至〇. 2 # ^以下,並且上述當作犧牲保護層26的傳統有機材料具 有高黏度及填入均一度不佳的特性,所以容易產生如第j 圖所示的孔洞(void)30,此將使得犧牲保護層26在後續溝 槽餘刻的過程之保護效果大受影響。 一 有鑑於上述習知技術的問題,係有人提出採用i — line ,阻^料當作犧牲保護層,由於其具有極佳的填溝能力, 月b夠/肖除習知的孔洞問題,防止底層蝕刻停止層被蝕穿。 有鑑於此,本發明提供一種雙鑲嵌結構的製作方法, 括:先’在上述半導體基底上依序形成一第一蝕刻 ^ , 弟一介電層、第二蝕刻停止層以及第二介電層。 Ϊ:丄:ί接觸孔於上述第二介電層、第二蝕刻停止層及 光阻二耷二之十,以露出上述第一蝕刻停止層。再形成一 光阻插塞及第二id ίζ佈一正光阻層於上述 電層之上,其中上述正光阻層之减;*特 性不同於上述光阻插塞。再 I之α應特 3 成溝槽圖案並露出上述光阻插塞及上述第二介電 f ’ :、中上述光阻插塞不受上述微影製程之影響。接下 電戶以ΐίί 3 ΐ圖案及上述光阻插塞為罩幕,蝕刻第二介 電層,直到路出上述筮― 德,本疒ρ+、# ^ 第一蝕刻停止層以形成一溝槽,最 去除上述接觸孔中之光阻插塞而 上述雙鑲嵌結構的制从七又叉蛾肷、、口稱 ^ ^ ^ ^ s 〇 I作方法,更包括去除上述接觸孔 -----述第一 ”電層表面上形成之防反射 第6頁 0503-6582TWFl.ptc 1247379Cs) 釭 釭 technology, especially for the fabrication of double damascene damascene), Α μ, layer (bottom st〇p layer) made of nucleus bottom layer (4) to stop the engraving of the edge layer in the process of creating holes . In the past year, in order to cooperate with the integrated circuit, the four kinds of products, the development of the U 1 dry person T, the development of the small and the operation speed of the 7C parts, the copper metal with shift resistance has gradually Used by the shore for you::: and the number of South Electronics moved to ^ ^ / broken application as a metal interconnect wire material replaced by the metal technology in the process. Copper metal mosaic (damascene) inline, Line skills, ritual, ritual, go, art, up, b can not only achieve the reduction of the interconnection and reduce the RC time delay, but also solve the problem of metal copper engraving is not easy, so it has become more than today The main development trend of the connection. Please refer to Fig. 1, which is a cross-sectional view of a dual damascene structure formed by the prior art, which is formed into a copper metal interconnect after the copper metal is filled and the copper metal is flattened. The step of forming the first FIG. 1 is to sequentially form an etch stop layer 丨4, a dielectric layer 16, an etch stop layer 18, and a dielectric on the semiconductor substrate 1 on which the conductive region 丨2 (for example, a copper interconnect) is formed. Layer 20, anti-reflection shielding layer 22, narrowly utilized The lithography technique and the selective etching of the anti-reflection shielding layer 2, the dielectric layer 20, the etch stop layer 18, and the dielectric layer 丨6 until the etch stop layer 14 is exposed to form a contact hole 24 Then, the contact hole 24 is filled with, for example, a polyUrylene ether p〇lymer by spin coating, and the specific example is PAE-2 or Allied manufactured by Schumacher. Organic polymer materials such as FLARE and H0SP 'L0SP manufactured by Signal Corporation, as the latter 0503-6582TWFl.ptc page 5 1247379 V. Invention description (2) Continued etching step sacrificial protection meeting 2 6 1 to avoid the above bottom layer The etching sound 14 is damaged. However, the size of the contact hole 24 has been gradually reduced to 〇. 3 /zm or even #. 2 # ^ below, and the above-mentioned conventional organic material serving as the sacrificial protective layer 26 has high viscosity and filled in. Uniformly poor characteristics, so it is easy to produce a void 30 as shown in Fig. j, which will greatly affect the protective effect of the sacrificial protective layer 26 in the subsequent trench remnant process. Know the technical problems, It has been proposed to use i-line as a sacrificial protective layer. Due to its excellent filling ability, the monthly b is sufficient to eliminate the conventional hole problem and prevent the underlying etch stop layer from being etched. The present invention provides a method for fabricating a dual damascene structure, comprising: first forming a first etch, a dielectric layer, a second etch stop layer, and a second dielectric layer on the semiconductor substrate.丄: ί contact holes in the second dielectric layer, the second etch stop layer and the photoresist two to two to expose the first etch stop layer. And forming a photoresist plug and a second id ζ 一 a positive photoresist layer on the electrical layer, wherein the positive photoresist layer is reduced; the characteristic is different from the photoresist plug. Further, the α of the I should be in a groove pattern and expose the photoresist plug and the second dielectric f ′ : , wherein the photoresist plug is not affected by the lithography process. After the electrician connects the ΐίί 3 ΐ pattern and the above-mentioned photoresist plug as a mask, the second dielectric layer is etched until the above-mentioned 筮 德, 疒 ρ+, # ^ first etch stop layer is formed to form a trench a slot for removing the photoresist plug in the contact hole, and the double damascene structure is formed by a method of removing a contact hole from a seven-and-forked moth, and a method of removing the contact hole---- Anti-reflection formed on the surface of the first "electric layer" page 6 0503-6582TWFl.ptc 1247379

遮蔽層的步驟。上述'第 氮化矽或氮氧化矽層, 二氧化碎。 -触刻停止層及第二蝕刻停止層 且上述第一介電層及第二介電層 為 為 再者,上述第二介電層 例如為氮氧化矽或有機底部 為了讓本發明之上述目 懂,下文特舉一較佳實施例 明如下: 表面上形成之防反射遮蔽層, 防反射層。 的、特徵、和優點能更明顯易 ’並配合所附圖式,作詳細說 圖式簡單說明 第1圖為習知用以埴λ力 示音圖。 真入鋼内連線之雙鑲嵌結構的剖面 第2a〜第2f圖為太 馬$ ^明之雙鑲嵌結構的製程剖面示意 [符號說明] 習知技術 1 2〜導電區域; 1 6、2 0〜介電層; 2 4〜接觸孔; 3 0〜孔洞。 1 02〜導電區域; 1 0 8〜第二蝕停止層 1 12〜防反射遮蔽層 1 0〜半導體基底; 1 4、1 8〜兹刻停止層 2 2〜防反射遮蔽層; 26〜犧牲保護層; 本發明 底 層 100〜半導體(矽)基 1 0 4〜第一 I虫刻停止 106、110〜金屬間介電層; 1247379 __ 案號 90120219 五、發明說明(4) I 13〜接觸孔; II 6〜光.罩; 118a、118b〜正型光阻罩幕; 1 3 0〜溝槽蝕刻用光阻圖案;1 2 0〜溝槽; DD〜雙鑲嵌結構。 實施例 以下利用第2 a〜第2 d圖所示之雙鑲嵌結構的製程剖面 圖,以更詳細地說明本發明。 首先’睛參照第2 a圖’形成該剖面圖的步驟為,首 先’在形成有導電區域1 〇 2 (例如銅内連線)的半導"體基底 100上依序形成第一巍刻停止層1〇4、介電層、第二|虫 刻停止層1 08、介電層11 〇、防反射遮蔽層丨丨2。上述介電 層1 0 6、1 1 0例如為化學氣相沈積法形成之二氧化石夕層戋豆 他低介電常數材料層,第一、第二飯刻停止層1〇4 ^^ 防反射遮蔽層11 2係由氮化矽或氮氧矽化物構成。 接著,於上述防反射遮蔽層112上塗佈一層正型光阻 I 1 8,透過一光罩11 β在欲形成接觸孔的位置對該正型光阻 層118進行曝光、顯影,以形成一正型光阻罩幕ιΐ8&、 118b,如第2b圖中所示。 接著,參照第2c圖,使用上述正型光阻罩幕n8a、 II 8b當作遮蔽物,蝕刻上述防反射遮蔽層丨丨2、上述第二 Π層二I、/二蝕刻停止層108及第一介電層106直到露 ”::刻:止層104為止,以在上述導電區域102相對位 置上形成一接觸孔1 1 3。 第8頁 0503-6582TWFl.ptc 五、發明說明(5) ^^ Ϊ ’塗佈一光阻材料於上述接觸孔1 1 3中,接著以 t二^二光進行照射使之硬化,形成一光阻插塞1 14a,以 /nzi蝕刻步驟的保護結構,來避免第一蝕刻停止層 来a又姑V ^第2d圖所示,其中上述插塞可選擇非深外線 ^ ^丄斜,如為負光阻型式以加熱或其他方式使之硬化, 插塞材料係不與後續微影製程中,使用之深紫外 線產生反應。 …、後’清參照第2e圖,利用微影技術進行塗佈深紫外 )光阻材料、曝光、顯影、烘烤等步驟,以形 友丨® i人,明參照第2 f圖,利用上述光阻圖案13 〇當作蝕 ,接著’蝕刻防反射遮蔽層112、介電層ιι〇,直到 刻二止層108為止’以形成溝槽120,其與接觸 法去Λ Λ 結構DD °緊接著,以乾式及㈣清除方 ^去除上述光阻圖案130及光阻插塞114a ’如第2f圖中所 102 /面績還以包上去除第一敍刻停止層104以露出導電,區域 ^真入銅等金屬以形成内連線的步驟。 f明採用光阻插塞當作保護結構,由 ΓΠΓΪ外光產生反應,所以能夠確實防止底ΐ: 停止層被蝕穿,進而提高產品良率。 -a蝕刻 雖然本發明已以較佳實施例揭露如上,铁i並 rtrr丄=熟習此技藝者’在不脫離;發明之精‘ =内,當可作些許之更動與潤舞,因此本發 3 耗圍*視後附之申請專利範圍所界定者為準。 ”濩The step of masking the layer. The above-mentioned 'the first layer of tantalum nitride or oxynitride is oxidized and crushed. a etch stop layer and a second etch stop layer, wherein the first dielectric layer and the second dielectric layer are, for example, bismuth oxynitride or an organic bottom layer, in order to achieve the above object of the present invention It is to be understood that a preferred embodiment is as follows: an anti-reflection shielding layer formed on the surface, an anti-reflection layer. The features, features, and advantages of the present invention are more apparent and easy to use and are described in detail with reference to the drawings. FIG. 1 is a conventional diagram for 埴λ force. Sections 2a to 2f of the double damascene structure of the true steel connection line are schematic diagrams of the process of the Taima $^ Ming's double damascene structure [Symbol Description] Conventional Technology 1 2~ Conductive Area; 1 6, 2 0~ Dielectric layer; 2 4~ contact hole; 3 0~ hole. 1 02 ~ conductive area; 1 0 8 ~ second etch stop layer 1 12 ~ anti-reflection shielding layer 1 0 ~ semiconductor substrate; 1 4, 1 8 ~ stop layer 2 2 ~ anti-reflection shielding layer; 26 ~ sacrificial protection Layer; the bottom layer 100~ semiconductor (矽) base of the invention 1 0 4~ first I insect stop 106, 110~ intermetal dielectric layer; 1247379 __ case number 90120219 5. Invention description (4) I 13~ contact hole; II 6 ~ light. Cover; 118a, 118b ~ positive resist mask; 1 3 0 ~ trench etching resist pattern; 1 2 0 ~ trench; DD ~ dual damascene structure. EXAMPLES Hereinafter, the present invention will be described in more detail by way of a process sectional view of a double damascene structure shown in Figs. 2a to 2d. First, the step of forming the cross-sectional view with reference to FIG. 2 a is to first form a first engraving on the semi-conductive body substrate 100 on which the conductive region 1 〇 2 (for example, a copper interconnect) is formed. The stop layer 1〇4, the dielectric layer, the second|insert stop layer 108, the dielectric layer 11〇, and the anti-reflection shielding layer 丨丨2. The dielectric layer 1 0 6 , 1 1 0 is, for example, a layer of a low dielectric constant material formed by a chemical vapor deposition method, the first and second rice stop layers 1〇4 ^^ The reflective shielding layer 11 2 is composed of tantalum nitride or oxynitride. Then, a positive-type photoresist I 1 8 is applied onto the anti-reflection shielding layer 112, and the positive-type photoresist layer 118 is exposed and developed through a mask 11 β at a position where a contact hole is to be formed to form a Positive photoresist masks ιΐ8&, 118b, as shown in Figure 2b. Next, referring to FIG. 2c, the positive-type resist masks n8a and II8b are used as a shield to etch the anti-reflection shielding layer 丨丨2, the second Π layer II I, the second etch stop layer 108, and the first A dielectric layer 106 is formed until a stop layer 104 is formed to form a contact hole 1 1 3 at a position opposite to the conductive region 102. Page 8 0503-6582TWFl.ptc V. Description of the invention (5) ^ ^ Ϊ 'coating a photoresist material in the above contact hole 1 1 3, followed by irradiation with t bis 2 light to harden it, forming a photoresist plug 1 14a, with the protective structure of the /nzi etching step, Avoiding the first etch stop layer to be aV V ^ 2d, wherein the plug may select a non-deep outer line ^ ^ skew, such as a negative photoresist type to heat or otherwise harden the plug material It does not react with the deep ultraviolet rays used in the subsequent lithography process. ..., after the 'clear reference to Figure 2e, using lithography to apply deep ultraviolet) photoresist, exposure, development, baking, etc.形 丨 i i i i i i i i i i i i i i i i i i i i i i i i 'etching the anti-reflection shielding layer 112, the dielectric layer ιι until the second stop layer 108' to form the trench 120, which is followed by the contact method Λ Λ structure DD °, followed by dry and (4) cleaning The photoresist pattern 130 and the photoresist plug 114a' are as shown in FIG. 2f, and the first stop layer 104 is removed to expose the conductive region, and the region is actually inserted into a metal such as copper to form an interconnect. The step of f is to use the photoresist plug as a protective structure, and the reaction is generated by the external light, so that the bottom layer can be surely prevented: the stop layer is etched, thereby improving the product yield. -a etching although the invention has been The preferred embodiment discloses the above, the iron i and rtrr丄 = familiar with the skilled person 'in the absence of the invention; the essence of the invention' = when the change can be made and the dance, so the hair of the 3 The scope defined by the patent scope shall prevail.

Claims (1)

1247379 曰 修正 案號 90120219 /、、申清專利範圍 之半鑲ί:崎 之平體基底’包括下列步驟: 一入ίΐ述ί導體基底上依序形成-第-蝕刻停止層、第 一"電層、第二蝕刻停止層以及第二介電層; 形成接觸孔於上述第-介蕾溫 卜卜 一介電層之中,以露ϊΐϋ電層、弟二#刻停止層及第 y 备出上迷弟一蝕刻停止層; 形成一光阻插塞於上述接觸孔中; 盆中光:層於上述光阻插塞及第二介電層之上, ’、以二^ f之感應特性不同於上述光阻插塞; 出上述光阻栝宾;? !·、+,β ,層形成溝槽圖案並露 - ^ 述弟一"電層’其中上述光阻插宾尤 党上述微景》製程之影# ; ^上述光阻插塞不 η以i述溝槽圖案及上述光阻插塞為罩幕,钱刻第-介 =上述第二㈣停止層以形成-溝』: ,、 萄孔中之光阻插塞而構成雙鑲嵌結構。 甘士明專利範圍第1項所述的雙鑲嵌結構的製作方 法,其中於2成上述接觸孔的步驟包括: 於t述第二介電層上塗佈一層正型光阻; 過:光罩在欲形成接觸孔的位置對該正型光阻層進 订曝先、顯影’以形成—正型光阻罩幕; ^ 雷屏使述正型光阻罩幕當作遮蔽物,蝕刻上述第二介 止i為止τ m: i第一介電層直到露出第-姓刻停 以及 逑導電區域相對位置上形成一接觸孔; 去除上述正型光阻罩幕。 I 0503-6582TWFl.ptc 第10頁 六、甲請專利範圍 3·如申請專利範圍匕 法,其t於上述接觸孔;/斤述的雙鑲嵌結構的製作方 塗佈一光阻材料於上^ f光阻插塞包括下列步驟: 使該光阻材料硬化以:;觸孔内,·以及 於該接觸孔内。 乂成作為光阻插塞之保護結構 4·如f請專利範圍 法,其中該光阻材料為負光^^成的雙鎮後結構的製作方 5 ·如申請專利範圍第 法,其中更包括於上述第二、入述的雙鑲嵌結構的製作方 的步驟。 一;丨電層上形成一防反射遮蔽層 6·如申請專利範圍第丨項所述山 法,其中上述第一介電層及 又鎮“構彻 去=申請專利範圍第1項所述的雙0鎮為嵌一社乳構化的石夕制。作 法,其中上述第一餘刻停鑲肷、、、口構的製作方 或氮氧化矽層。 弟—蝕刻停止層為氮化矽 8·如申請專利範圍第5項所述 層^其中上述防反射遮蔽層為氮氧化又石夕鎮或肷^構底^作反方射 之半導體基底,包括方法,適用於具有導電區域 在上述半導體基底上依序形成—蝕刻 電層以及第二介電層; τ止層、第一介 形成接觸孔於上述第二介電層及第一八 露出上述蝕刻停止層; 7丨電㈢之中,以 形成一光阻插塞於上述接觸孔中; 1247379 修正 曰 -案號 9012021Q 六'申請專利範圍 塗佈一正先阻層於土述 其中上述正光阻層之感應U阻插塞及第二介電層之上, 以微影製程定義1^下不同於上述光阻插塞; 出上述光阻插塞及上述第層,以形成溝槽圖案f露 受上述微影製程之影響;;1電層,其中上述光阻插塞不 以上述溝槽圖牵及卜 電層以形成一溝槽以及’L先阻插塞為罩幕,蝕刻第二介 _塞而構成雙賴結構。 法 JL中;^ 圍第9項所述的雙鑲嵌結構的製作方 其中於形成上述接觸孔的步驟包括: 第二介電層上塗佈-層正型光阻; 行眼光、'^,罩在奴形成接觸孔的位置對該正型光阻層進 订曝先顯影’以形成-正型光阻罩幕; 電層ίϊΐΐΐϊί:::當作遮蔽物,韻刻上述第二介 述導電區域相對位置上形成-接觸孔;以; 在上 去除上述正型光阻罩幕。 法 11 ·如申請專利範圍第9項所述的雙鑲嵌 其中於士述接觸孔内形成光阻插塞包括下歹ΐ步ς作方 塗佈:光阻材料於上述接觸孔内;以及 使該光阻材料硬化以形成一作為光阻插塞 於該接觸孔内。 τ更^構 、12·如申請專利範圍第11項所述的雙鑲嵌結構的製作 方法,其中δ亥光阻材料為負光阻組成。 Π·如申請專利範圍第9項所嵌y構的製i方 第12頁 0503-6582TWFl.ptc 1247379 案號 90120219 Λ_η 曰 修正 六、申請專利範圍 法,其中更包括於上述第二介電層上形成一防反射遮蔽 層 法 14.如申請專利範圍第9項所述的雙鑲嵌結構的製作方 其中上述第一介電層及第二介電層為二氧化矽。 法 1 5.如申請專利範圍第9項所述的雙鑲嵌結構的製作方 其中上述蝕刻停止層為氮化矽或氮氧化矽層。 16..如申請專利範圍第13項所述的雙鑲嵌結構的製作 方法,其中上述防反射遮蔽層為氮氧化矽或有機底部防反 射層。1247379 曰Amendment No. 90120219 /, the scope of the patent clearing half of the ί: Saki flat base 'includes the following steps: 入 ί ί ί 导体 导体 导体 导体 conductor substrate sequentially formed - the first - etch stop layer, first " An electric layer, a second etch stop layer, and a second dielectric layer; forming a contact hole in the first dielectric layer of the first dielectric layer, the deuterium layer, the second layer, and the second layer Forming a etch stop layer; forming a photoresist plug in the contact hole; the light in the basin: layer on the photoresist plug and the second dielectric layer, ', the characteristics of the two Different from the above-mentioned photoresist plug; ! ·, +, β, the layer forms a groove pattern and exposes - ^ 述一一 "quot; electric layer 'the above-mentioned photoresist inserts the guest of the above-mentioned micro-view" process of the shadow of the process #; ^ the above-mentioned photoresist plug does not η i The trench pattern and the photoresist plug are a mask, and the second (four) stop layer is formed to form a trench, and the photoresist plug in the hole is formed into a dual damascene structure. A method for fabricating a dual damascene structure according to the first aspect of the invention, wherein the step of forming the contact hole is: applying a positive photoresist on the second dielectric layer; Forming a contact hole to position the positive photoresist layer to expose and develop 'to form a positive photoresist mask; ^ Ray screen to make the positive photoresist mask as a shield, etching the second medium τ m: i The first dielectric layer forms a contact hole until the first-last stop and the opposite position of the conductive region are exposed; the positive-type photoresist mask is removed. I 0503-6582TWFl.ptc Page 10 VI. A. Patent scope 3. If the scope of the patent application is ,, the t is in the contact hole; the manufacturer of the dual damascene structure described above is coated with a photoresist material. The f-resist plug includes the following steps: hardening the photoresist material: in the contact hole, and in the contact hole.乂成 as a protective structure of the photoresist plug 4·such as f please patent scope method, wherein the photoresist material is a negative light-emitting double-town structure of the production side 5 · as claimed in the patent scope, including In the second step, the steps of the preparation of the dual damascene structure described above. Forming an anti-reflection shielding layer on the electric layer of the invention. The mountain method according to the third aspect of the patent application, wherein the first dielectric layer and the town are "constructed" = claim 1 of the patent application scope The double-zero town is a Shishi system inlaid with a body of milk. In the above method, the first remaining layer is inlaid with enamel, and the structure of the mouth structure or the layer of oxynitride. The etch-stop layer is tantalum nitride 8 The layer as described in claim 5, wherein the anti-reflection shielding layer is a semiconductor substrate which is oxidized by Nitrogen Oxide and is a reversed-radiation semiconductor substrate, and comprises a method for coating a semiconductor substrate having a conductive region. Forming an etched electrical layer and a second dielectric layer; a τ stop layer, a first via forming a contact hole in the second dielectric layer and a first 八 exposing the etch stop layer; 7 丨 electricity (3), Forming a photoresist plug in the contact hole; 1247379 Correction 案-Case No. 9012021Q Six' patent application scope coating a positive resist layer in the above-mentioned positive photoresist layer of the induced U-resistance plug and the second dielectric Above the layer, defined by the lithography process a photoresist plug; the photoresist plug and the first layer are formed to form a trench pattern f exposed by the lithography process; and an electrical layer, wherein the photoresist plug is not driven by the trench pattern And the electric layer forms a trench and the 'L first blocking plug is used as a mask, and the second dielectric plug is etched to form a double-layer structure. The method of manufacturing the double damascene structure described in Item 9 The step of forming the contact hole includes: coating a positive-type photoresist on the second dielectric layer; performing an eye-light, '^, covering the positive-type photoresist layer at a position where the slave forms a contact hole Developing 'to form a positive-type photoresist mask; an electric layer ίϊΐΐΐϊί::: as a shield, forming a contact hole at a relative position of the second-mentioned conductive region; to remove the above-mentioned positive-type photoresist The method of the method of claim 11, wherein the double damascene according to claim 9 is characterized in that the photoresist plug is formed in the contact hole of the contact, and the photoresist is coated in the contact hole; And curing the photoresist material to form a photoresist plug in the contact hole. The method for fabricating the dual damascene structure according to claim 11, wherein the δ hai photoresist material is composed of a negative photoresist. Π · The y structure of the ninth structure as claimed in claim 9 i is the 12th page 0503-6582TWFl.ptc 1247379 Case No. 90120219 Λ_η 曰 Amendment VI, the patent application scope method, which further includes forming an anti-reflection shielding layer method on the second dielectric layer 14. As claimed in claim 9 The fabrication of the dual damascene structure described above, wherein the first dielectric layer and the second dielectric layer are cerium oxide. The method of manufacturing the dual damascene structure according to claim 9 The etch stop layer is a tantalum nitride or hafnium oxynitride layer. 16. The method of fabricating a dual damascene structure according to claim 13, wherein the anti-reflection shielding layer is a ruthenium oxynitride or an organic bottom anti-reflection layer. 0503-6582TWFl.ptc 第13頁0503-6582TWFl.ptc Page 13
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106531611A (en) * 2015-09-09 2017-03-22 上海先进半导体制造股份有限公司 Method for enabling silicon groove to be filled with liquid material and gumming machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106531611A (en) * 2015-09-09 2017-03-22 上海先进半导体制造股份有限公司 Method for enabling silicon groove to be filled with liquid material and gumming machine

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