KR20000003186A - Contact hole forming method - Google Patents
Contact hole forming method Download PDFInfo
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- KR20000003186A KR20000003186A KR1019980024352A KR19980024352A KR20000003186A KR 20000003186 A KR20000003186 A KR 20000003186A KR 1019980024352 A KR1019980024352 A KR 1019980024352A KR 19980024352 A KR19980024352 A KR 19980024352A KR 20000003186 A KR20000003186 A KR 20000003186A
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- groove
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 230000003628 erosive effect Effects 0.000 claims description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 상·하층 배선들간의 접속공으로 이용되는 콘택홀 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole used as a connection hole between upper and lower wirings.
일반적으로, 금속 배선 재료로는 알루미늄 및 그의 합금이 주로 이용되고 있다. 이러한 알루미늄 및 그의 합금은 전도도가 높고, 경제성이 있기 때문에 반도체 소자의 고집적화가 진행되고 있는 상황에서도, 금속배선 재료로서 알루미늄 및 그의 합금이 주로 사용되고 있음은 주지의 사실이다.Generally, aluminum and its alloy are mainly used as a metal wiring material. Since aluminum and its alloys are high in conductivity and economical, it is well known that aluminum and its alloys are mainly used as metal wiring materials even in a situation where high integration of semiconductor devices is in progress.
도 1a 내지 도 1c는 상기와 같은 알루미늄 금속막을 이용한 종래 기술에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정 단면도로서, 우선, 도 1a에 도시된 바와 같이, 소정의 하부층(도시안됨)이 형성되어 있는 반도체 기판(1) 상에 절연막(2)을 증착하고, 이 절연막(2) 상에 그의 소정 부분을 노출시키는 제1감광막 패턴(도시안됨)을 형성한다.1A to 1C are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to the prior art using the aluminum metal film as described above. First, as shown in FIG. 1A, a predetermined lower layer (not shown) is formed. An insulating film 2 is deposited on the formed semiconductor substrate 1, and a first photosensitive film pattern (not shown) for exposing a predetermined portion thereof is formed on the insulating film 2.
그런 다음, 상기 제1감광막 패턴을 식각 마스크로 하는 1차 식각 공정을 실시한 후에 상기 식각 마스크로 사용된 제1감광막 패턴을 제거하여 절연막 표면에 소정 폭으로된 홈(3)을 형성한다.Then, after performing the first etching process using the first photoresist pattern as an etching mask, the first photoresist pattern used as the etching mask is removed to form grooves 3 having a predetermined width on the surface of the insulating film.
다음으로, 도 1b에 도시된 바와 같이, 절연막(2) 상에 감광막을 토포한 상태에서, 상기 감광막에 대한 노광 및 현상 공정을 실시하여 절연막 표면에 형성된 홈(3)의 중심부를 노출시키는 제2감광막 패턴(4)을 형성하고, 이어서, 상기 제2감광막 패턴(4)을 식각 마스크로 하는 식각 공정을 실시하여 절연막내에 반도체 기판(1)을 노출시키는 콘택홀(5)을 형성한다.Next, as shown in FIG. 1B, in a state in which the photoresist film is spread on the insulating film 2, a second process of exposing and developing the photoresist film to expose the center portion of the groove 3 formed on the surface of the insulating film. The photosensitive film pattern 4 is formed, and then, an etching process using the second photosensitive film pattern 4 as an etching mask is performed to form a contact hole 5 exposing the semiconductor substrate 1 in the insulating film.
이후, 도 1c에 도시된 바와 같이, 식각 마스크로 사용된 제2감광막 패턴을 제거한 상태에서, 콘택홀이 매립되도록 전체 상부에 알루미늄 금속막을 증착하고, 이어서, 상기 알루미늄 금속막을 패터닝하여 금속배선(6)을 형성한다.Subsequently, as shown in FIG. 1C, in a state in which the second photoresist layer pattern used as an etch mask is removed, an aluminum metal film is deposited on the entire upper portion of the contact hole to be buried, and then the aluminum metal film is patterned to form a metal wiring 6 ).
그러나, 상기와 같은 종래 기술에서는 콘택홀 내부에 존재하는 첨점 부분(A)이 날카롭게 되어 있기 때문에 콘택홀 내부에서 알루미늄 금속막의 스텝 커버리지(Step Coverage) 불량을 야기시키게 되고, 이는 콘택홀의 매립 불량을 유발시키기 때문에 결과적으로는, 콘택홀 내부에서 보이드와 같은 결함이 발생시켜 반도체 소자의 특성을 저하시키게 되는 문제점이 있었다.However, in the prior art as described above, since the sharp portion A existing inside the contact hole is sharp, the step coverage of the aluminum metal film is caused inside the contact hole, which causes a poor filling of the contact hole. As a result, defects such as voids are generated inside the contact holes, thereby degrading the characteristics of the semiconductor device.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 콘택홀 내부의 첨점 부위가 라운드 형태가 되도록 할 수 있는 콘택홀 형성방법을 제공하는데, 그 목적이 있다.Therefore, the present invention devised to solve the above problems, to provide a contact hole forming method that can be made so that the cusp portion inside the contact hole in a round form, an object thereof.
도 1a 내지 도 1c는 종래 기술에 따른 금속배선 형성방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming metal wirings according to the prior art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 콘택홀 형성방법을 설명하기 위한 일련의 공정 단면도.2A to 2E are cross-sectional views of a series of processes for explaining a method for forming a contact hole according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 절연막11 semiconductor substrate 12 insulating film
13 : 제1감광막 패턴 14 : 제1홈13: first photosensitive film pattern 14: first groove
15 : 제2감광막 패턴 16 : 제2홈15: second photosensitive film pattern 16: second groove
20 : 콘택홀 A : 첨점20: contact hole A: point
상기와 같은 목적을 달성하기 위한 본 발명의 콘택홀 형성방법은, 소정 두께의 절연막이 도포된 반도체 기판을 제공하는 단계; 상기 절연막 상에 그의 소정 부분을 노출시키는 제1감광막 패턴을 형성하는 단계; 상기 제1감광막 패턴을 식각 마스크로 하는 1차 식각 공정을 실시하여 노출된 절연막 부분의 소정 두께를 식각하는 단계; 상기 제1감광막 패턴을 제거한 후에, 상부 표면에 제1홈이 형성된 절연막 상에 상기 제1홈의 중심부를 노출시키는 제2감광막 패턴을 형성하는 단계; 상기 제2감광막을 식각 마스크로 하는 2차 식각 공정을 실시하여 제1홈의 하부에 상기 제1홈 보다 작은 폭을 갖는 제2홈을 형성하는 단계; 상기 제2감광막에 대한 침식 공정을 실시하여 상기 제1홈과 제2홈이 경계면에 존재하는 첨점 부분을 노출시키는 단계; 및 상기 반도체 기판이 노출되도록 제2감광막 패턴을 식각 마스크로 하는 3차 식각 공정을 실시하여 상기 제2홈 하부의 절연막 부분을 식각하는 단계를 포함하며, 상기 3차 식각 공정시에 첨점 부위가 함께 식각되는 것을 특징으로 한다.Contact hole forming method of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate coated with an insulating film of a predetermined thickness; Forming a first photoresist film pattern exposing a predetermined portion thereof on the insulating film; Etching a predetermined thickness of the exposed insulating layer by performing a first etching process using the first photoresist pattern as an etching mask; After removing the first photoresist pattern, forming a second photoresist pattern that exposes a central portion of the first groove on an insulating film having a first groove formed on an upper surface thereof; Performing a second etching process using the second photoresist layer as an etching mask to form a second groove having a width smaller than the first groove in the lower portion of the first groove; Performing an erosion process on the second photoresist film to expose a peak portion in which the first groove and the second groove exist at an interface; And etching a portion of the insulating layer below the second groove by performing a third etching process using the second photoresist layer pattern as an etching mask so that the semiconductor substrate is exposed. It is characterized by being etched.
본 발명에 따르면, 콘택홀을 형성하기 위한 식각 공정전에 O2가스를 이용하여 식각 마스크로 사용되는 감광막 패턴을 침식시킴으로써, 이러한 감광막 패턴에 의해 형성되는 콘택홀 내부의 첨점 부위가 라운드 형태가 되도록 할 수 있으며, 이에 따라, 후속 공정에서 금속막의 매립 특성을 향상시킬 수 있다.According to the present invention, the photoresist pattern used as an etching mask is eroded by using O 2 gas before the etching process for forming the contact hole, so that the pointed portion inside the contact hole formed by the photoresist pattern becomes round. As a result, the embedding property of the metal film may be improved in a subsequent process.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 콘택홀 형성방법을 설명하기 위한 일련의 공정 단면도이다.2A to 2D are a series of cross-sectional views for explaining a method of forming a contact hole according to an exemplary embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이, 소정의 하부층(도시안됨)이 형성되어 있는 반도체 기판(11) 상에 절연막(12)을 두껍게 도포한다. 그런 다음, 상기 절연막(12) 상에 공지된 공정을 통해 그의 소정 부분을 노출시키는 제1감광막 패턴(13)을 형성한 상태에서, 상기 제1감광막 패턴(13)을 식각 마스크로 하는 1차 식각 공정을 실시하여 노출된 절연막 부분의 소정 두께를 식각한다. 이 결과, 절연막(12) 표면에는 소정 폭 및 깊이로된 제1홈(14)이 형성된다.First, as shown in FIG. 2A, an insulating film 12 is thickly coated on the semiconductor substrate 11 on which a predetermined lower layer (not shown) is formed. Then, in a state in which the first photoresist pattern 13 is formed on the insulating layer 12 to expose a predetermined portion thereof, a first etching using the first photoresist pattern 13 as an etching mask is performed. The process is performed to etch a predetermined thickness of the exposed insulating film portion. As a result, a first groove 14 having a predetermined width and depth is formed on the surface of the insulating film 12.
다음으로, 도 2b에 도시된 바와 같이, 1차 식각 공정에서 식각 마스크로 사용된 제1감광막을 제거한 후에, 표면에 제1홈(14)이 형성된 절연막(12) 상에 재차 감광막을 도포하고, 이 감광막에 대한 노광 및 현상 공정을 실시하여 제1홈(14)의 중심부를 노출시키는 제2감광막 패턴(15)을 형성한다.Next, as shown in FIG. 2B, after removing the first photoresist film used as the etch mask in the primary etching process, the photoresist film is again applied on the insulating film 12 having the first grooves 14 formed on the surface thereof. The photosensitive film is exposed and developed to form a second photosensitive film pattern 15 exposing the central portion of the first groove 14.
이어서, 도 2c에 도시된 바와 같이, 제2감광막 패턴(15)을 식각 마스크로 하는 2차 식각 공정을 실시하여 제1홈(14)의 하부에 상기 제1홈(14) 보다 작은 폭을 갖는 제2홈(16)을 형성한다. 이때, 2차 식각 공정에서는 반도체 기판(11)이 노출되지 않는 범위에서 제1홈(14) 하부의 절연막 부분을 식각한다.Subsequently, as illustrated in FIG. 2C, a second etching process using the second photoresist pattern 15 as an etching mask is performed to have a width smaller than that of the first groove 14 in the lower portion of the first groove 14. The second groove 16 is formed. In this case, in the second etching process, the insulating layer portion under the first groove 14 is etched in a range where the semiconductor substrate 11 is not exposed.
한편, 2차 식각 공정에서 절연막(12)의 식각 정도는 반도체 기판(11)이 노출되도록 식각할 수도 있다.Meanwhile, the etching degree of the insulating layer 12 may be etched to expose the semiconductor substrate 11 in the secondary etching process.
계속해서, 도 2d에 도시된 바와 같이, 제1홈의 하부에 제2홈을 형성한 상태에서, 식각 마스크로 사용된 제2감광막 패턴(15)에 대한 침식(Erosion) 공정을 실시하여 상기 제1홈과 제2홈의 경계면에 존재하는 첨점 부위(A)을 노출시킨다.Subsequently, as illustrated in FIG. 2D, in a state in which the second groove is formed below the first groove, an erosion process is performed on the second photoresist pattern 15 used as an etching mask. Exposed point portion (A) present at the interface between the first and second grooves.
여기서, 제2감광막 패턴(15)에 대한 침식 공정은 O2가스를 이용하여 실시하며, 그 양은 10 내지 100sccm으로 하고, 챔버내의 파워는 180 내지 220W로 하고, 상기 제2감광막 패턴(15)의 침식 정도는 100 내지 1,000Å 정도가 되도록 한다.Here, the erosion process for the second photoresist pattern 15 is carried out using O 2 gas, the amount is 10 to 100 sccm, the power in the chamber is 180 to 220W, the second photoresist pattern 15 Erosion degree is to be about 100 ~ 1,000Å.
이후, 도 2e에 도시된 바와 같이, 제2감광막 패턴(15)을 식각 마스크로 하는 3차 식각 공정을 실시하여 제2홈 하부의 절연막 부분을 식각함으로써, 절연막 내에 반도체 기판(11)이 노출시키는 콘택홀(20)을 형성한다. 이때, 식각 가스로는 플루오르 가스를 기본으로 하는 플루오린계 가스를 사용한다.Subsequently, as illustrated in FIG. 2E, a third etching process using the second photoresist layer pattern 15 as an etching mask is performed to etch the insulating layer portion below the second groove to expose the semiconductor substrate 11 in the insulating layer. The contact hole 20 is formed. In this case, a fluorine-based gas based on fluorine gas is used as the etching gas.
이 결과, 제2홈 하부의 절연막 부분이 식각되어 반도체 기판(11)이 노출될 뿐만 아니라, 제2감광막 패턴(15)에 대한 침식 공정에 의해 노출된 첨점 부위도 함께 식각되어, 도시된 바와 같이, 첨점 부위가 라운드 형태로 된다.As a result, not only the insulating portion of the lower portion of the second groove is etched to expose the semiconductor substrate 11, but also the pointed portions exposed by the erosion process on the second photoresist pattern 15 are also etched, as shown. The cusps are rounded.
이에 따라, 후속 공정에서 실시되는 금속배선 공정에서 콘택홀에 매립되는 금속막의 매립 특성이 개선되기 때문에 종래 문제점으로 야기되었던 보이드와 같은 현상은 발생되지 않게 된다.Accordingly, in the metallization process performed in the subsequent process, the embedding property of the metal film embedded in the contact hole is improved, so that a phenomenon such as voids caused by a conventional problem does not occur.
한편, 본 발명의 다른 실시예로서, 제2감광막 패턴에 대한 침식 공정을 추가로 실시할 필요없이 3차 식각 공정시에 플로오린계 가스와 O2가스를 혼합하여 상기 제2감광막 패턴에 대한 침식 공정과 절연막의 식각 공정을 동시에 수행할 수도 있으며, 이 경우에도 첨점 부위의 형태를 라운드 형태로 만들 수 있다. 이때, O2가스의 양은 전체 가스의 양에 대하여 20%가 넘지 않도록 한다.Meanwhile, as another embodiment of the present invention, the erosion of the second photoresist layer pattern may be performed by mixing the fluorine-based gas and the O 2 gas during the third etching process without further performing the erosion process of the second photoresist layer pattern. The process and the etching process of the insulating film may be performed at the same time, and in this case, the shape of the cusp portion may be rounded. At this time, the amount of O 2 gas should not exceed 20% with respect to the total amount of gas.
이상에서와 같이, 본 발명은 식각 마스크로 사용되는 감광막 패턴에 대한 침식 공정을 추가시킴으로써, 콘택홀내에 존재하는 첨점 부위의 형태를 라운드 형태로 만들 수 있는 것에 기인하여 콘택홀의 스텝 커버리지 특성을 향상시킬 수 있으며, 이에 따라, 후속 공정에서 금속막의 매립 특성을 향상시킬 수 있게 되어 금속배선의 특성을 향상시킬 수 있게 됨은 물론 반도체 소자의 신뢰성을 향상시킬 수 있게 된다.As described above, the present invention improves the step coverage characteristics of the contact hole due to the addition of an erosion process to the photoresist pattern used as an etch mask, thereby making the shape of the point portion present in the contact hole round. As a result, in the subsequent process, the embedding property of the metal film may be improved, thereby improving the properties of the metal wiring and improving the reliability of the semiconductor device.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024352A KR20000003186A (en) | 1998-06-26 | 1998-06-26 | Contact hole forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024352A KR20000003186A (en) | 1998-06-26 | 1998-06-26 | Contact hole forming method |
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| KR20000003186A true KR20000003186A (en) | 2000-01-15 |
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| KR1019980024352A KR20000003186A (en) | 1998-06-26 | 1998-06-26 | Contact hole forming method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451372B1 (en) * | 2002-04-10 | 2004-10-06 | 엘지산전 주식회사 | Devise operating shutter of cradle for vacuum circuit breaker |
| KR100866121B1 (en) * | 2002-06-29 | 2008-10-31 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
-
1998
- 1998-06-26 KR KR1019980024352A patent/KR20000003186A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451372B1 (en) * | 2002-04-10 | 2004-10-06 | 엘지산전 주식회사 | Devise operating shutter of cradle for vacuum circuit breaker |
| KR100866121B1 (en) * | 2002-06-29 | 2008-10-31 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
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