經濟部智葸財產局員工消費合作社印製 「432617 4925twf.doc/008 五、發明説明（f ) 本發明是有關於一種金屬內連線（interconnect)之製造 方法，且特別是有關於利用光阻層的矽化製程（silylaticm) 來製作金屬鑲嵌（damascene)和雙重金屬鑲嵌（dual damascene)的方法。 金屬鑲嵌係一種在介電層中先蝕刻出金屬內連線的溝 渠，再塡入金屬當作內連線的方法，此法可以滿足製程中 對高可靠度及高良率內連線的要求，所以此法將成爲在深 次微米（Sub-Quarter Micron)中內連線製造方法的最佳選 擇。 第1Α圖到第1Ε圖爲習知金屬鑲嵌製程的流程剖面示 意圖。請參照第1Α圖，首先，提供一半導體基底1〇〇 ’ 在基底100中已形成有部份半導體元件（圖中未繪出）。接 著，是在基底100上方形成一介電層102。 然後，請參照第1Β圖，以傳統的微影技術在介電層 上形成一層光阻圖案（photoresist pattern)l〇4。 之後，請參照第1C圖，透過光阻圖案1〇4非等向性 倉虫刻（anisotropic etch)介電層1〇2’以在其中形成開口 1〇6。 接著，將光阻圖案102剝除。 接著，請參照第1D圖，在介電層1〇2上方形成一金 屬層108，並塡滿開口 106。 最後，請參照第1E圖’利用化學機械硏磨法(CMP) ’ 以介電層102爲硏磨終止層，去除開口 1〇6以外之金屬層 108，完成金屬鑲嵌製程。 另外一種類似於金屬鑲嵌製程的是雙重金屬鑲嵌製 3 本紙張尺度適用中國國家標準（CNS )A4规格（210X297公釐} --------—裝------訂------彳 (請先W讀背面之注意事項再填寫本頁〕 經濟部智慧封產局員工消費合作社印製 顯4 3261 7 4925twf.doc/008 五、發明説明（π ) 程，其與金屬鑲嵌製程的不同處在於雙重金屬鑲嵌製程是 先在介電層中完成介層窗口和溝渠的圖案，之後經由一次 沈積導電材質的步驟，完成內連線。 第2A圖至桌2G圖爲習知的雙重金屬鑲嵌製造流程 剖面圖。請參照第2A圖，首先，提供一半導體基底2〇〇， 在基底200中已形成有部份半導體元件（圖中未繪出）。接 著’是在基底200上方形成一介電層202。 然後，請參照第2B圖，以傳統的微影技術在介電層 上形成一層光阻圖案204。 之後，請參照第2C圖，透過光阻圖案204非等向性 蝕刻介電層2〇2，去除部份介電層202，以在其中形成溝 渠(trench)206。接著，將光阻圖案204移除。 然後，請參照第2D圖，以傳統的微影技術在介電層 2〇2表面上形成另一層光阻圖案208。 其後，請參照第2E圖，透過光阻圖案208非等向性 蝕刻介電層2〇2，以形成開口 210，其中，部分之開口 210 形成於溝渠206之下方。再將光阻圖案208去除。 接著，請參照第2F圖，在介電層202上方形成一金 屬層212，並塡滿溝渠206和開口 210。 最後，請參照第2G圖，利用化學機械硏磨法’以介 電層202爲硏磨終止層，去除溝渠206和開口 210以外之 金屬層212，完成雙重金屬鑲嵌製程。 然而上述方法中，不論是金屬鑲嵌或是雙重金屬鑲 嵌，均須先將光阻層的圖形利用蝕刻製程轉移到介電層 4 本紙張尺度適用中國國家揉牟（CNS ) A4規格（210X297公釐） 1._!------—裝------訂------旅 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^4326 1 7 4925twf.doc/008 五、發明説明（4 ) 上，之後再將使用過之光阻層移除’過程相當繁瑣複雜， 而且在蝕刻介電層和移除光阻的過程中，可能會對下方之 基底或未完成之半導體元件造成傷害。尤其是雙重金屬鑲 嵌製程，須進行兩次微影製程，對於製程之控制更是不易。 本發明的目的之一 ’就是在提供一種金屬內連線之製 造方法 > 可簡化製p，節省成本，並增加元件效能。 本發明的另一目的，就是提供一種金屬內連線之製造 方法，利用光阻矽化製程’可將光阻層矽化而形成內金屬 介電層(IMD)，以使金屬內連線之製程簡化。 根據本發明一較佳實施例，提出一種金屬內連線之製 造方法，適用於半導體製程，包括下列步驟。首先，提供 一已形成部份元件之半導體基底。接著在基底上形成一光 阻層。之後，定義光阻層，以在光阻層中形成一開口，暴 露出基底。接著，進行一矽化製程，以使該光阻層矽化而 形成一矽化光阻層。然後，在矽化光阻層上形成一金屬層， 並塡滿開口。去除開口以外之金屬層以形成金屬內連線。 其中光阻層的材質係包括含有光酸產生因子成分的化 學增幅型光阻層。矽化製程係利用在富含矽烷的環境下加 熱。 根據本發明另一較佳實施例，提供一種雙重金屬鑲嵌 之製程，包括下列步驟。首先提供一已形成部份元件之半 導體基底。然後，在基底上形成一光阻層。接著，定義此 光阻層’已在光阻層中同時形成一開口和一溝渠，其中溝 渠的深度小於開口的深度。欲產生這樣的結構可利用具有 5 本紙張尺度適用中國國家標準（CNS } A4規格（210X297公釐) ' ——：------1¾衣------ΐτ---^---.,4. (請先閲讀背面之注意事項再填寫本頁) 4326 t 7 492 5twf doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明u) 開口圖形和溝渠圖形之一光罩’對光阻層進行曝光及顯 影，並在光罩之溝渠圖形上預先形成一可部份透光之膜 層，以使曝光用之光源通過溝渠圖形之強度小於通過開口 圖形之強度。如此在曝光時溝渠圖案區之光阻曝光之效果 較差，故顯影後仍保留部份厚度之光阻層，而在開口圖案 區之光阻層則因曝光效果較佳而在顯影後完全被去除。 接著，進行一矽化製程’以使光阻層矽化而形成一砂 化光阻層。在矽化光阻層上形成一金屬層，並塡滿開口和 溝渠。之後，去除開口以外之金屬層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖到第1E圖爲習知金屬鑲嵌製程的流程剖面示 意圖； 第2A圖至第2G圖爲習知的雙重金屬鑲嵌製造流程 剖面圖； 請參照第3A圖至第3D圖，其繪示依照本發明一較 佳實施例的一種金屬內連線的製造流程剖面圖；以及 請參照第4A圖至第4E圖，其繪示依照本發明一較佳 實施例的一種雙重金屬鑲嵌的製造流程剖面圖。 圖式之標記說明： 100，200，300，400 :基底 102，202 :介電層 6 ---------—裝------訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中( CNS ) ( 210X297^ ) 經濟部智慧財產局員工消費合作杜印製 F4326 1 7 A7 4925twf.doc/008 B7 "X、發明説明（Π 104，204，208，302，402 :光阻層 106，210，304，404 :開口 108，212，306，412 :金屬層 108a，212a，306a，412a :金屬內連線 206，406 :溝渠 302a :矽化光阻層 408 :光罩 409 :不透光層 410 :半透光層 室旆例 請參照第3A圖至第3D圖，其繪示依照本發明一較 佳實施例的一種金屬內連線的製造流程剖面圖。 首先’請參照第3 A圖，提供一已形成部份元件（圖中 未繪出）之半導體基底300,其中部份元件譬如是由位元 線，字元線或是金屬層所組成。接著，在基底300上形成 一層已圖案化之光阻層302,其中此圖案化之光阻層302 中具有開口 304，例如是溝渠或是接觸窗，在稍後製程中 可在開口 304塡入金屬層以作爲內連線。光阻層的材質例 如是含有光酸產生因子成分的化學增幅型光阻層，或是其 他能產生矽化之光阻材料。其形成方法例如是傳統的微影 製程。 接著，請參照第3B圖，進行一矽化製程，使光阻圖 案302矽化成形成一矽化光阻層3〇2a。例如使用一含矽之 矽化試劑(通常是矽烷類，如SiH4)，通入反應室中，使得 7 本紙張尺度適用中國國家榇牟（)八4規格（210X297公釐） II 1 I n n ^ . 旅 (諳先閲讀背面之注意事項再填寫本頁) P4 32 6 1 7 4925iwf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（d) 晶片在含矽的環境下加熱，此時矽成份會藉由擴散進入光 阻層302，而與光阻層302中的氧原子反應形成氧化矽。 然後，請參照第3C圖，在矽化光阻層3〇2a上形成一· 層金屬層306，並塡滿開口 304。其中金屬層的材質例如 是銅或鋁，形成方法例如是濺鍍法，化學汽相沉積法或電 鍍法。 之後，請參照第3D圖。去除開口以外之金屬層306 以形成金屬內連線3〇6a。例如利用化學機械硏磨法硏磨金 屬層306，以砂化光阻層302a表面爲終點，將開口 304以 外的金屬層306去除。 請參照第4A圖至第4E圖，其繪示依照本發明一較佳 實施例的一種雙重金屬鑲嵌的製造流程剖面圖。 首先，請參照第4A圖，提供一已形成部份元件（圖中 未會出）之半導體基底400’其中部份元件譬如是由位元 線，字元線或是金屬層所組成。接著，在基底上形成 一層光阻層402。光阻層的材質例如是含有光酸產生因子 成分的化學增幅型光阻層，或是其他能產生矽化之光阻材 料。 接著，請參照第4B圖’定義光阻層402，以在其中 同時形成開口 404及溝渠406，其中溝渠406的深度小於 開口 404之深度，且開口 404下方的基底400被暴露出來。 欲產生這樣的結構，可利用具有使開口圖形和溝渠圖形同 時被定義出之一光罩408，對光阻層4〇2進行曝光製程， 此光罩4〇2例如是利用使曝光用之光源無法通過之圖案 請 先 閲 讀 背 it- 事 項 再 !裝 頁 訂 本紙張尺度適用中國國家標準（CNS ) A4说格（2丨0 X 297公釐） A7 B7 4925twf.doc/008 五、發明説明（7 ) 409，將開口圖形轉移至光阻層402上，而在欲定義溝渠 圖形之位置上預先形成一可部份透光之膜層410,以使_ 光用之光源通過溝渠圖形之強度小於通過開口圖形之強 度。如此在曝光時溝渠圖案區之光阻曝光之效果較差’故 顯影後仍保留部份厚度之光阻層，形成溝渠4〇6。而在開 口圖案區之光阻層則因曝光效果較佳而在顯影後完全被$ 除，形成開口 4〇4並暴露出基底400。 接著，請參照第4C圖，進行一矽化製程，使光阻圖 案402矽化成形成一矽化光阻層402a。例如使用一含矽之 矽化試劑（通常是矽烷類，如SiH4)，通入反應室中，使得 晶片在含矽的環境下加熱，此時矽成份會藉由擴散進入光 阻層402，而與光阻層402中的氧原子反應形成氧化矽。 然後，請參照第4D圖，在矽化光阻層402a上形成一 層金屬層412,並塡滿開口 404與溝渠406。其中金屬層412 的材質例如是銅或鋁，形成方法例如是濺鍍法，化學汽相 沉積法或電鍍法。 之後，請參照第4E圖。去除開口以外之金屬層412 以形成金屬內連線412a。例如利用化學機械硏磨法硏磨金 屬層412，以矽化光阻層402a表面爲終點，將開口 404和 溝渠4〇6以外的金屬層412去除。 由上述本發明較佳實施例可知，本發明所提供一種金 屬內連線之製造方法，係利用可矽化之光阻層在形成金屬 內連線之圖案後’對圖案化後之光阻層進行矽化製程，使 其形成一矽化光阻層，此矽化光阻層可作爲內金屬介電 9 (錆先聞讀背面之注意事項其填寫本f) 裝· ▲ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（匚?^>夫4規格（210\297公楚：） 經濟部智慧財產局員工消費合作社印製 騮4326 1 7 4925tw!-,〇c/〇08 A? B7_ 五、發明説明（t ) 層，故可減少一介電層之製作，且減少一去光阻之步驟。 故可減少製作流程，降低成本。而且，減少蝕刻介電層和 去光阻步驟可避免對基底造成傷害，故可增進元件之良率 與效能。 此外，本發明應用於雙重金屬鑲嵌製程時，利用可砂 化之光阻層，在一次曝光過程中，在光阻層上形成雙重金 屬鑲嵌之圖案，之後，對圖案化後之光阻層進行矽化製程， 使其形成一砂化光阻層，此砂化光阻層可作爲內金屬介電 層。如此，除了可減少一介電層之製作，及節省一去光阻 之步驟外，尙可減少一道光罩之製作及一次微影蝕刻之製 程，對於製程的改善，更是顯而易見。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 10 本紙張尺度適用中國國家標準（CNS ) A4規格（2ΪΟΧ297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs "432617 4925twf.doc / 008 V. Description of the Invention (f) This invention relates to a method for manufacturing a metal interconnect, and in particular to the use of photoresist Layer silicatic process (silylaticm) to make damascene and dual damascene. Damascene is a type of trench in which a metal interconnect is first etched in a dielectric layer, and then the metal is used as Interconnection method. This method can meet the requirements of high reliability and high yield interconnections in the process. Therefore, this method will become the best choice for the manufacturing method of interconnections in Sub-Quarter Micron. Figures 1A to 1E are schematic cross-sectional views of a conventional metal damascene process. Please refer to Figure 1A. First, a semiconductor substrate 100 ′ is provided. Some semiconductor elements have been formed in the substrate 100 (not shown in the figure). (Drawing). Next, a dielectric layer 102 is formed over the substrate 100. Then, referring to FIG. 1B, a photoresist pattern (phot) is formed on the dielectric layer using a conventional lithography technique. oresist pattern) 104. After referring to FIG. 1C, the photoresist pattern 104 is passed through an anisotropic etch dielectric layer 102 ′ to form an opening 106 therein. Next The photoresist pattern 102 is peeled off. Next, referring to FIG. 1D, a metal layer 108 is formed over the dielectric layer 102 and fills the opening 106. Finally, referring to FIG. 1E, using chemical mechanical honing Method (CMP) 'The dielectric layer 102 is used as a honing stop layer, and the metal layer 108 other than the opening 106 is removed to complete the metal damascene process. Another type of metal damascene process is a double metal damascene process. China National Standard (CNS) A4 Specification (210X297 mm) ---------- Installation ------ Order ------ 彳 (Please read the precautions on the back before filling this page 〔Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3261 7 4925twf.doc / 008 5. The invention description (π) process is different from the metal damascene process in that the double metal damascene process is first in the dielectric layer. Complete the pattern of the vias and trenches, and then complete the step of depositing the conductive material once to complete Inner wiring. Figures 2A to 2G are cross-sectional views of a conventional dual metal damascene manufacturing process. Please refer to Figure 2A. First, a semiconductor substrate 200 is provided. Some semiconductor elements have been formed in the substrate 200. (Not shown in the figure). Next, a dielectric layer 202 is formed on the substrate 200. Then, referring to FIG. 2B, a photoresist pattern 204 is formed on the dielectric layer by a conventional lithography technique. After that, referring to FIG. 2C, the dielectric layer 202 is anisotropically etched through the photoresist pattern 204, and a part of the dielectric layer 202 is removed to form a trench 206 therein. Then, the photoresist pattern 204 is removed. Then, referring to FIG. 2D, another photoresist pattern 208 is formed on the surface of the dielectric layer 200 by a conventional lithography technique. Thereafter, referring to FIG. 2E, the dielectric layer 202 is anisotropically etched through the photoresist pattern 208 to form an opening 210, and a portion of the opening 210 is formed below the trench 206. The photoresist pattern 208 is removed. Next, referring to FIG. 2F, a metal layer 212 is formed over the dielectric layer 202, and the trenches 206 and the openings 210 are filled. Finally, referring to FIG. 2G, the chemical-mechanical honing method is used to remove the metal layer 212 other than the trench 206 and the opening 210 by using the dielectric layer 202 as a honing stop layer to complete the dual metal damascene process. However, in the above method, whether it is metal inlay or double metal inlay, the pattern of the photoresist layer must first be transferred to the dielectric layer by an etching process. 4 This paper size is applicable to China National Mill (CNS) A4 specification (210X297 mm) ) 1 ._! -------- install ------ order ------ brigade (please read the notes on the back before filling this page) ^ 4326 1 7 4925twf.doc / 008 5. In the description of the invention (4), the process of removing the used photoresist layer is very complicated and complicated, and in the process of etching the dielectric layer and removing the photoresist, May damage the underlying substrate or unfinished semiconductor components. In particular, the double metal inlaying process requires two lithographic processes, which makes it difficult to control the process. One of the objectives of the present invention is to provide a method for manufacturing a metal interconnect > which can simplify the manufacture of p, save costs, and increase component performance. Another object of the present invention is to provide a method for manufacturing metal interconnects. The photoresist silicidation process can be used to silicify the photoresist layer to form an inner metal dielectric layer (IMD), so as to simplify the process of metal interconnects. . According to a preferred embodiment of the present invention, a method for manufacturing a metal interconnect is proposed, which is suitable for a semiconductor process and includes the following steps. First, a semiconductor substrate having a part of a component formed is provided. A photoresist layer is then formed on the substrate. Then, a photoresist layer is defined to form an opening in the photoresist layer to expose the substrate. Then, a silicidation process is performed to silicify the photoresist layer to form a silicidated photoresist layer. Then, a metal layer is formed on the silicided photoresist layer and fills the opening. The metal layer outside the opening is removed to form a metal interconnect. The material of the photoresist layer includes a chemically amplified photoresist layer containing a photoacid generating factor component. The silicidation process utilizes heating in a silane-rich environment. According to another preferred embodiment of the present invention, a process for providing a dual metal damascene is provided, which includes the following steps. First, a semiconductor substrate having a part of a component formed is provided. Then, a photoresist layer is formed on the substrate. Next, it is defined that the photoresist layer 'has simultaneously formed an opening and a trench in the photoresist layer, wherein the depth of the trench is smaller than the depth of the opening. To produce such a structure can be used with 5 paper sizes applicable to Chinese national standards (CNS} A4 specifications (210X297 mm) '' ——: ----- 1¾ clothing ------ ΐτ --- ^- -., 4. (Please read the notes on the back before filling this page) 4326 t 7 492 5twf doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention u) Opening graphics and ditch graphics One photomask 'exposes and develops the photoresist layer, and a partially transparent film layer is formed in advance on the trench pattern of the photomask, so that the intensity of the light source for exposure through the trench pattern is less than that through the opening pattern. strength. In this way, the effect of photoresist exposure in the trench pattern area is poor during exposure, so a part of the thickness of the photoresist layer remains after development, and the photoresist layer in the open pattern area is completely removed after development due to better exposure effect. . Next, a silicidation process is performed to silicify the photoresist layer to form a sanded photoresist layer. A metal layer is formed on the silicided photoresist layer and fills the openings and trenches. After that, the metal layer other than the opening is removed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Fig. 1E is a schematic cross-sectional view of a conventional metal inlaying process; Figs. 2A to 2G are cross-sectional views of a conventional dual metal inlaying manufacturing process; please refer to Figs. 3A to 3D, which illustrate a method according to the present invention. A cross-sectional view of a manufacturing process of a metal interconnect according to a preferred embodiment; and FIG. 4A to FIG. 4E are cross-sectional views of a manufacturing process of a dual metal inlay according to a preferred embodiment of the present invention. Explanation of markings on the drawings: 100, 200, 300, 400: substrate 102, 202: dielectric layer 6 ----------- installation ------ order (please read the precautions on the back first) (Fill in this page) This paper is applicable (CNS) (210X297 ^) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperation Du F4326 1 7 A7 4925twf.doc / 008 B7 " X, Invention Description (Π 104, 204, 208 302, 402: photoresist layer 106, 210, 304, 404: opening 108, 212, 306, 412: metal layer 108a, 212a, 306a, 412a: metal interconnect 206, 406: trench 302a: silicidated photoresist layer 408: photomask 409: opaque layer 410: semi-transmissive layer chamber For examples, please refer to FIGS. 3A to 3D, which show a cross-section of a manufacturing process of a metal interconnect according to a preferred embodiment of the present invention First, please refer to FIG. 3A to provide a semiconductor substrate 300 having formed a part of elements (not shown), and some of the elements are, for example, composed of bit lines, word lines, or metal layers. Then, a patterned photoresist layer 302 is formed on the substrate 300, wherein the patterned photoresist layer 302 has an opening 304, such as a trench. It is a contact window. In the later process, a metal layer can be inserted into the opening 304 as an interconnect. The material of the photoresist layer is, for example, a chemically amplified photoresist layer containing a photoacid generating factor component, or other silicon resists The photoresist material is formed by a conventional lithography process. Next, referring to FIG. 3B, a silicidation process is performed to silicify the photoresist pattern 302 to form a silicidated photoresist layer 302a. For example, a Silicides of silicon (usually silanes, such as SiH4) are introduced into the reaction chamber, making 7 paper sizes suitable for the Chinese national standard (4) (210X297 mm) II 1 I nn ^. 旅 (谙 先Read the notes on the back and fill in this page) P4 32 6 1 7 4925iwf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (d) The chip is heated in a silicon-containing environment, at this time The silicon component diffuses into the photoresist layer 302 and reacts with oxygen atoms in the photoresist layer 302 to form silicon oxide. Then, referring to FIG. 3C, a metal layer is formed on the silicidated photoresist layer 302a. 306, and filled the opening 304. Among them The material of the metal layer is, for example, copper or aluminum, and the forming method is, for example, sputtering, chemical vapor deposition, or electroplating. After that, please refer to FIG. 3D. The metal layer 306 other than the opening is removed to form a metal interconnect 3. 6a. For example, the metal layer 306 is honed by a chemical mechanical honing method, and the metal layer 306 other than the opening 304 is removed by sanding the surface of the photoresist layer 302a as an end point. Please refer to FIG. 4A to FIG. 4E, which are cross-sectional views showing a manufacturing process of a dual metal inlay according to a preferred embodiment of the present invention. First, please refer to FIG. 4A, and provide a semiconductor substrate 400 'which has formed some elements (not shown in the figure), and some of the elements are composed of bit lines, word lines, or metal layers, for example. Next, a photoresist layer 402 is formed on the substrate. The material of the photoresist layer is, for example, a chemically amplified photoresist layer containing a photoacid generating factor component, or another photoresist material capable of generating silicidation. Next, please refer to FIG. 4B to define the photoresist layer 402 to simultaneously form an opening 404 and a trench 406 therein. The depth of the trench 406 is smaller than the depth of the opening 404, and the substrate 400 under the opening 404 is exposed. To produce such a structure, an exposure process can be performed on the photoresist layer 402 by using a photomask 408 having an opening pattern and a trench pattern defined at the same time. This photomask 402 is, for example, a light source for exposure. If you ca n’t pass the pattern, please read the it-item first! The paper size of the bound booklet applies the Chinese National Standard (CNS) A4 (2 丨 0 X 297 mm) A7 B7 4925twf.doc / 008 5. Description of the invention ( 7) 409. The opening pattern is transferred to the photoresist layer 402, and a partially transmissive film layer 410 is formed in advance at the position where the trench pattern is to be defined, so that the intensity of the light source passing through the trench pattern is less than Through the intensity of the opening pattern. In this way, the effect of the photoresist exposure in the trench pattern area during the exposure is poor ', so a portion of the photoresist layer remains after the development to form the trench 406. The photoresist layer in the opening pattern area is completely removed after development due to the better exposure effect, forming an opening 404 and exposing the substrate 400. Next, referring to FIG. 4C, a silicidation process is performed to silicify the photoresist pattern 402 to form a silicidated photoresist layer 402a. For example, a silicon-containing silicide (usually a silane type, such as SiH4) is used to pass into the reaction chamber so that the chip is heated in a silicon-containing environment. At this time, the silicon component will diffuse into the photoresist layer 402 and interact with The oxygen atoms in the photoresist layer 402 react to form silicon oxide. Then, referring to FIG. 4D, a metal layer 412 is formed on the silicided photoresist layer 402a, and the openings 404 and the trenches 406 are filled. The material of the metal layer 412 is, for example, copper or aluminum, and the forming method is, for example, sputtering, chemical vapor deposition, or electroplating. After that, please refer to Figure 4E. The metal layer 412 other than the opening is removed to form a metal interconnect 412a. For example, the metal layer 412 is honed by a chemical mechanical honing method, and the metal layer 412 other than the opening 404 and the trench 406 is removed with the surface of the silicidated photoresist layer 402a as an end point. As can be known from the foregoing preferred embodiments of the present invention, a method for manufacturing a metal interconnect provided by the present invention is to use a siliconizable photoresist layer to form a pattern of the photoresist layer after forming a pattern of the metal interconnect. The silicidation process makes it form a silicidated photoresist layer. This silicidated photoresist layer can be used as the inner metal dielectric 9 (锖 Please read the note on the back to read this f). The paper size of the paper is in accordance with the Chinese national standard (匚? ^ ≫ Husband 4 specifications (210 \ 297 Gongchu :) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 骝 4326 1 7 4925tw!-, 〇c / 〇08 A? B7_ V. Description of the invention (t) layer, so the production of a dielectric layer can be reduced, and the step of removing photoresist can be reduced. Therefore, the manufacturing process can be reduced, and the cost can be reduced. Moreover, the steps of etching the dielectric layer and removing the photoresist It can avoid damage to the substrate, so it can improve the yield and efficiency of the component. In addition, when the invention is applied to the dual metal damascene process, the sandable photoresist layer is used to form on the photoresist layer in one exposure process Double metal After embedding the pattern, a silicidation process is performed on the patterned photoresist layer to form a sanded photoresist layer, and the sanded photoresist layer can be used as an inner metal dielectric layer. In addition, a dielectric can be reduced. In addition to the production of a layer and the step of eliminating a photoresist, the process of making a photomask and a lithographic etching process can be reduced, and the improvement of the process is even more obvious. Although the present invention has been disclosed in a preferred embodiment As above, however, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be regarded as the attached patent. The scope is subject to definition. (Please read the notes on the back before filling out this page.) 10 This paper size applies the Chinese National Standard (CNS) A4 specification (2Ϊ〇 × 297 mm)