經濟部中央標準局負工消費合作社印製 415059 A7 __________一 五、發明説明（/ ) 本發明是有關於一種製造一般及特殊極大積體電路 (Ultra Large Scale Integration, (JLSI)晶片之方法，旦 特別是有關於一種利用雙重分層的表面成像（Top Surface Imaging，TSI)製程形成內連線層，藉以改善雙重嵌入式 (Dual Damascence)金屬導線技術之方法' 在高積集度的晶片上以極大積體電路技術，利用雙廢微 影製程形成內連線的重要性越來越高。當技術由超大型稹 體電路（VLSI)提昇到極大積體電路（ULSI)，爲了使其寅容 易的產生電子遷移，以提昇速度及操作電腦，半導體工_ 發展新的方法與技術以生產緊密堆積的半導體晶片。如熟 悉此項技藝者所知，在緊密堆積的晶片內，較近的元件® 離不只是以元件實際的縮短距離來提供電子訊號較快的傳 遞速度，也降低了訊號在媒介傳遞時產生的阻抗；另一方 面，緊密的堆積可使極大積體電路（ULSI)用極小的元件與 層間連線製作。層間連線的運作必須利用減少金屬導線割 面的條紋數，使增加的電阻最小以傳遞訊號；重要的是必 須盡可能的注意阻抗匹配，以及有利於固態連線。 在半導體晶片上通常包含一或多個導線，這些彼此導線 由一層絕緣層互相分離，或是更進一步的藉著另一絕緣層 與接近半導體表面的元件分離；這些導線彼此互相連接， 且在適當的地方與元件相連，導線連接的方式是在絕緣層 的孔洞中塡入金屬。習知有許多方法可以形成金屬線與層 間連線，這些透過絕緣層使金屬線彼此相連的孔洞（Hole) 稱爲介層洞（Via Hole)，而孔洞通過絕緣層連往位於下方 3 本紙浪尺度適用中國囤家標率（CNS ) Λ4規格（210X297公酱) " ~ (请先閲请背而之注意事項其填??本貫) 訂 415059 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（>) 的元件時則稱爲接觸窗口（Contact Hole)，這些孔洞通常 是於半導體基底上沈積絕緣層後，再進行蝕刻絕緣層而形 成的。之後再覆蓋一層金屬在絕緣層上方，藉以塡滿孔洞， 然後在透過定義（Pat tern)金屬層上的光阻進行蝕刻形成 金屬線。第一層金屬層透過接觸窗與下方昀元件做電性接 觸，使金屬可以透過介電絕緣材料往下延伸到元件上；第 二層金屬層以相同的方法形成，且透過介層洞與下方的金 屬層進行金屬層間的接觸。另外，這些孔洞也常分別的被 塡充金屬作爲金屬栓塞（Plug)，再進行平坦化使之對應於 絕緣層的表面，之後再沈積金屬層以形成介層洞栓塞的接 觸，然後蝕刻沈積的金屬層，以形成製程所要求的個別化 導線層。 ._ 爲了在金屬連線接觸或多層導線間介層洞栓塞的接合 部份提供堅固的接觸區域，通常必須增加金屬連線與孔洞 的空間，以掩蓋過平版印刷製程本身產生的覆蓋誤差 (Overlay Error)或製程偏差。這種設計的基本規則會使得 電路尺寸增加，造成元件設計的密度明顯的降低；因此， 發展微影技術與製程來改善覆蓋誤差或製程容忍力是g、須 的。爲了在考量覆蓋容忍以及微影的花費下，將晶片最小 化，自動對準（Self-Aligned)的製程於是發展。 另外，在基底的金屬層間形成接觸也會有一些其他的問 題存在，在蝕刻介電層形成接觸窗口時，接觸窗口的側壁 必須傾斜，以確保在金屬層有好的連續性；斜面越陡峭， 在金屬沈積方面越有可能因接觸窗的角度而造成斷路。然 4 本紙張尺度適用中國國家榇準（CNS ) Μ規格（2l〇X297公釐） --------,、裝— ,* ' <請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局眞工消费合作社印裝 41505^ A7 _-_B7 五、發明説明（3 ) 而，運用緩慢傾斜的側壁以確保金屬導線的連續性會提高 晶片的使用面積，且使接觸窗無法如預期般密集；此外， 使用接觸窗產生不規則且不平坦的表面會使製作隨後的內 連線層變得困難。 請參照第1圖，第1圖是習知一種製作半導體元件方法 的示意圖。提供一基底10，其上已定義出元件區11，形成 第一絕緣層12並定義出接觸窗；接著沈積第一金屬層13， 透過接觸窗14連接元件區11。同樣的，第二金屬層16透 過在第二絕緣層15上定義形成的介層洞17,連接第一層金 屬層13，此結構利用第三絕緣層18做爲保護層 (Passivate)。雖然第1圖所描述的結構並非基準，但爲顯 示出非常不規則的_面的一個例子，這種表面不規則的情 形會造成可靠度方面的問題；其中一個問題就是，當兩層 間的絕緣層變薄時，第一金屬層與第二金屬層間的S區域 會有短路危險，以及當金屬層變薄時，在0區域會產生電 路斷路的危險。 習知的一種解決上述問題的方法稱爲雙重嵌入式（Dual Damascence)製程，此製程最簡單的形式是在絕緣層_[：〜進 行，此絕緣層形成於在基底上，且經過平坦化；對絕緣層 進行定義，水平方向的溝渠與垂直方向的孔洞經由蝕刻絕 緣層同時彩成。在基底上，若通過第一絕緣層，那金屬導 線與孔洞會往下連往元件區；假若通過上方的絕緣層，那 就是連接另一層金屬層。接下來沈積金屬在已設有上述結 構的基底上藉以塡滿溝渠與孔洞，以此同時形成金屬導線 5 本紙張尺度適用中國國家標準（CNS 規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝- 訂 經濟部中央標準局员工消費合作社印製 41^059 A7 B7 五、發明説明（4) 及內連線孔洞。最後，利用化學機械硏磨法（Chenncal Mechanical Polish, CMP)使表面平坦，並且準備進行另一 個雙重嵌入式的結構，以完整的將導線嵌入進水平的溝渠 與垂直的孔洞內，此即爲製程的雙重性（DualUy·)。 請同時參照第2a圖與第2b圖，第2a圖繪示爲進行化 學機械硏磨前的雙重嵌入式結構；第2b圖繪示爲經過化學 機械硏磨的雙重嵌入式結構。兩道微影步驟及兩層絕緣層 分別被一蝕刻阻擋層（Etch Stop Layer)分開，結構敘述如 下：提供表面平坦的基底30,其中有定義圖案的第一金屬 層31，第一絕緣層32被沈積覆蓋在第一金屬層31上，將 第一絕緣層31平坦化後，覆蓋上蝕刻阻擋層33 ;利用第一 道微影蝕刻步驟在蝕刻阻擋層33上定義出接觸窗口，該處 將形成垂直栓塞的內連線，其中第一絕緣層32的厚度與栓 塞的高度相同。再形成第二絕緣層34於蝕刻阻擋層33上， 此時第一絕緣層32還未被蝕刻，第二絕緣層34的厚度與 定義後的第二金屬層厚度相同；第二絕緣層34在第二道微 影蝕刻步驟中被蝕刻，定義出導線通道40連往蝕刻阻擋層 33，其中一些通道40會對準前面步驟於蝕刻阻擋層33.上 定義的接觸窗口 41。通道40與接觸窗口 41重疊的區域f 在進行第二道微影蝕刻步驟時，會曝露出接觸窗口，而繼 續蝕刻第一絕緣層32,進而曝露出下方的第一金屬層31。 接著，在第一絕緣層與第二絕緣層中蝕刻形成的水平的通 道與垂直的孔洞上覆蓋塡滿金屬35 ;最後，利用蝕刻的方 式或化學機械硏磨法去除第二絕緣層34上方多餘的金屬 6 I--------Γ 裝！ (請先閱锖背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（2;0X297公釐） 415059 A7 B7 經濟部中央標準局員工消費合作社印掣 五、發明説明（f) 35，但不要去掉通道40或窗口 41內的金屬，形成如第2b 圖所示之結構。 爲了解決塡充金屬導線孔洞產生的問題，以及伴隨發生 的過度覆蓋容忍力的結果，雙重嵌入式的製程技術將會越 來越受重視。同時，架線工程（Wiring)將會在容忍力的範 圍內遵守最少的基本規則，而且因孔洞周圍薄的金屬或絕 緣層產生的問題也會被避開。但是，很明顯的這種製程是 複雜的’特別是需要用到兩道微影蝕刻製程以形成垂直孔 洞的區域；以此方法，首先需在蝕刻阻擋層形成後進行微 影定義出孔洞，且於更後面微影蝕刻出孔洞。此外，蝕刻 阻擋層通常爲氮化矽層；對氮化矽層進行蝕刻的設備必須 額外的增加，這些複雜步驟的加入會導致產率降低，增加 元件的密度，以及增加成本。 儘管如此’在習知技藝中雙重嵌入式的製程仍因其優點 而大量的被運用，比如Shoda在美國專利案號5,529,953 中揭露的，一種利用選擇性沈積製造金屬栓（Stud)(垂直 金屬栓塞）及（水平）層間連線的雙重嵌入式結構的方法， 其中選擇性的沈積係透過重複的運用光罩與微影步螺完 成。同樣的，Zheng在美國專利案號5,602,053中揭露的，-一種雙重嵌入式抗鎔化的結構在兩層之間形成。另一種方 式，基於對雙重嵌入式製程中重複運用光罩定義的認可， Avanzino在美國專利案號5,614,765中說明，利用光罩圖 案以同時形成導線與介層洞。 所以能夠以新的方法取代習知雙重嵌入式製程中複雜 7 (請先閏讀背面之注意事項再填寫本頁) 03- "°Printed by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives 415059 A7 __________ 15. Description of the Invention (/) The present invention relates to a method for manufacturing general and special Ultra Large Scale Integration (JLSI) chips. In particular, there is a method for forming an interconnect layer by using a double-layered surface imaging (Top Surface Imaging (TSI) process to improve dual damascence metal wire technology. With the extremely integrated circuit technology, it is increasingly important to use double waste lithography to form interconnects. When the technology was upgraded from VLSI to very large integrated circuit (ULSI), Easily generate electron migration to increase speed and operate computers. Semiconductor industry_ Develop new methods and technologies to produce tightly packed semiconductor wafers. As is known to those skilled in the art, in close-packed wafers, closer components ® Not only does the actual shortened distance of the component provide faster transmission speed of the electronic signal, but also reduces the resistance of the signal during the transmission of the medium On the other hand, the tight stacking allows the ultra-integrated circuit (ULSI) to be fabricated with very small components and inter-layer connections. The operation of the inter-layer connections must reduce the number of stripes on the cut surface of the metal wire and minimize the increased resistance to transfer It is important to pay attention to impedance matching as much as possible, and to facilitate solid-state wiring. Semiconductor wafers usually contain one or more wires, which are separated from each other by an insulating layer, or further by another An insulating layer is separated from the component near the semiconductor surface; these wires are connected to each other and connected to the component in the proper place. The way of connecting the wires is to insert metal into the hole of the insulating layer. There are many methods known to form metal wires. Connected to the layers. These holes, which connect the metal wires to each other through the insulation layer, are called via holes, and the holes are connected to the bottom through the insulation layer. ) Λ4 specification (210X297 male sauce) " ~ (please read the precautions for the back first and fill it out) Order 415059 Central Standard of the Ministry of Economic Affairs A7 B7 printed by the Bureau's Consumer Cooperatives 5. The components of the invention description are called contact holes. These holes are usually formed by depositing an insulating layer on a semiconductor substrate and then etching the insulating layer. Then cover a layer of metal over the insulating layer to fill the holes, and then etch through the photoresist on the metal layer to form metal lines. The first layer of metal layer uses the contact window to make electricity with the lower element. The sexual contact allows the metal to extend down to the element through the dielectric insulating material; the second metal layer is formed in the same way, and the metal layer contacts with the metal layer below through the hole in the dielectric layer. In addition, these holes are often filled with metal as metal plugs, and then planarized to correspond to the surface of the insulating layer, and then a metal layer is deposited to form the contact of the via hole plug, and then the deposited A metal layer to form the individualized wire layers required by the process. ._ In order to provide a solid contact area at the junction of the metal wiring contact or the via hole plug of the multilayer wire, the space between the metal wiring and the hole must usually be increased to cover the overlay error generated by the lithography process itself (Overlay Error) or process deviation. The basic rules of this design will increase the circuit size and cause a significant reduction in the density of the component design; therefore, it is necessary and necessary to develop lithography technology and processes to improve coverage errors or process tolerance. In order to minimize the wafers in consideration of the coverage tolerance and the cost of lithography, a self-aligned process was developed. In addition, there are some other problems in forming contact between the metal layers of the substrate. When the contact layer is formed by etching the dielectric layer, the sidewall of the contact window must be inclined to ensure good continuity in the metal layer. In terms of metal deposition, the more likely it is that the circuit is broken due to the angle of the contact window. However, 4 paper sizes are applicable to China National Standards (CNS) M specifications (210 × 297 mm) -------- ,, installed —, * '< Please read the precautions on the back before filling this page ) Ordered by the Central Standards Bureau of the Ministry of Economic Affairs of the Mathematics and Consumer Cooperatives 41505 ^ A7 _-_ B7 V. Description of the Invention (3) In addition, the use of slowly inclined sidewalls to ensure the continuity of the metal wires will increase the area of the chip and make contact. The windows cannot be as dense as expected; moreover, the use of contact windows to create irregular and uneven surfaces can make it difficult to make subsequent interconnect layers. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional method for fabricating a semiconductor device. A substrate 10 is provided, on which the element region 11 has been defined, a first insulating layer 12 is formed and a contact window is defined; then a first metal layer 13 is deposited, and the element region 11 is connected through the contact window 14. Similarly, the second metal layer 16 is connected to the first metal layer 13 through a via hole 17 defined and formed on the second insulating layer 15. This structure uses the third insulating layer 18 as a passivate. Although the structure described in Figure 1 is not a benchmark, it is an example of a very irregular surface. This irregular surface situation causes reliability problems; one of the problems is when the insulation between two layers is When the layer becomes thin, there is a danger of a short circuit in the S region between the first metal layer and the second metal layer, and when the metal layer becomes thin, there is a danger of a circuit break in the 0 region. A conventional method for solving the above problems is called a dual damascence process. The simplest form of this process is performed on an insulating layer _ [: ~, which is formed on a substrate and planarized; The insulating layer is defined. The trenches in the horizontal direction and the holes in the vertical direction are colored at the same time by etching the insulating layer. On the substrate, if the first insulation layer is passed, the metal wires and holes are connected down to the component area; if the upper insulation layer is passed, it is connected to another metal layer. Next, deposit metal on the substrate with the above structure to fill the trenches and holes to form metal wires at the same time. 5 This paper size applies to Chinese national standards (CNS specifications (210X297 mm). Please read the precautions on the back first) (Fill in this page again) Binding-Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 41 ^ 059 A7 B7 V. Description of the Invention (4) and the interconnecting holes. Finally, the chemical mechanical honing method (Chenncal Mechanical Polish, CMP ) Make the surface flat and prepare another double-embedded structure to completely embed the wires into the horizontal trenches and vertical holes, which is the duality of the process (DualUy ·). Please also refer to Figure 2a And Figure 2b, Figure 2a shows the double embedded structure before chemical mechanical honing; Figure 2b shows the double embedded structure after chemical mechanical honing. Two lithographic steps and two insulating layers They are separated by an etch stop layer, respectively. The structure is described as follows: a flat surface substrate 30 is provided, wherein a first metal layer 31 having a defined pattern is provided, and a first insulation layer is provided. 32 is deposited and covered on the first metal layer 31, and after the first insulating layer 31 is planarized, the etch stop layer 33 is covered; the first lithography etching step is used to define a contact window on the etch stop layer 33, where A vertical plug internal wiring will be formed, where the thickness of the first insulating layer 32 is the same as the height of the plug. A second insulating layer 34 is then formed on the etch stop layer 33. At this time, the first insulating layer 32 has not been etched. The thickness of the second insulating layer 34 is the same as the thickness of the second metal layer after the definition; the second insulating layer 34 is etched in the second lithography etching step, defining the wire channels 40 to be connected to the etching blocking layer 33, and some of the channels 40 The contact window 41 defined on the etching stop layer 33. in the previous step will be aligned. The area f where the channel 40 overlaps the contact window 41. During the second lithography etching step, the contact window will be exposed and the first etching will continue. The insulating layer 32 further exposes the first metal layer 31 below. Next, the horizontal channel and the vertical hole formed by etching in the first insulating layer and the second insulating layer are covered with the metal 35; finally, the etching is performed by etching Method or chemical mechanical honing method to remove excess metal 6 above the second insulating layer 34 I -------- Γ! (Please read the precautions on the back of the unit before filling in this page) National Standard (CNS) A4 specification (2; 0X297 mm) 415059 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Description (f) 35, but do not remove the metal in the channel 40 or the window 41, forming The structure shown in Figure 2b. In order to solve the problems caused by the holes of the metal-filled wires and the result of the over-tolerance caused by the over-embedding, the dual-embedded process technology will be paid more and more attention. At the same time, Wiring will adhere to the minimum basic rules within tolerance, and problems caused by thin metal or insulating layers around the holes will be avoided. However, it is obvious that this process is complicated. In particular, two lithographic etching processes are needed to form vertical holes. In this method, the lithography is required to define the holes after the etch stop layer is formed, and Holes were etched later in the lithography. In addition, the etch stop layer is usually a silicon nitride layer; the equipment for etching the silicon nitride layer must be additionally added. The addition of these complicated steps will lead to a reduction in yield, an increase in the density of the component, and an increase in cost. Nevertheless, the dual-embedded process is still widely used due to its advantages in conventional techniques, such as disclosed by Shoda in U.S. Patent No. 5,529,953, which uses selective deposition to make metal studs (vertical metal plugs). ) And (horizontal) layer-to-layer interconnected double-embedded structure methods, where selective deposition is performed by repeated use of photomasks and lithography snails. Similarly, Zheng disclosed in U.S. Patent No. 5,602,053 that a double embedded anti-sulfurization structure is formed between two layers. Another approach, based on the recognition of repetitive mask definitions in dual embedded processes, Avanzino, in US Patent No. 5,614,765, describes the use of a mask pattern to form both wires and vias. Therefore, it can replace the complicated process in the conventional dual-embedded process with a new method. 7 (Please read the precautions on the back before filling this page) 03- " °
本紙張尺度適用中國國家標华（CNS > Λ4規格（2丨〇><297公釐） 經濟部中央標率局貝工消资合作社印製 415059 Λ7 ___________B7_ 五、發明説明（“） 的部份，且能夠有效的運用在製造半導體基底及晶片上， 將會是一個很大的優勢。 因此本發明的主要目的就是，提供一種雙重嵌入式定義 的方法，利甩表面成像步驟製造半導體基底與晶片，利用 結合一種改良的光阻矽化（Siiyiati〇n)的製程，有效的改 善現行雙重嵌入式的製程。 本發明的另一主要目的就是，提供一種雙重嵌入式定義 的方法’在雙重嵌入式定義製程中加入光阻矽化的步驟。 本發明的再另一主要目的就是，提洪—種雙重嵌入式定 義的方法’改善在內連線接觸窗口圖案下方之導線的對準 性（A1ignment)。 本發明的再另'主要目的就是，提供—種雙重嵌入式定 義的方法，減少對準容忍力及製程偏差，藉以增加極大積 體電路晶片的積集度。 根據本發明的上述及其他目的，提出—種雙重嵌入式定 義的方法，此方法之簡述如下：提洪一基底，其上已形成 綜合絕緣層，其中綜合絕綠層包括第一介電層、透過中間 層或稱爲蝕刻阻擋層與第二介電層分隔開；形成光阻矽化 的第一光阻層於綜合絕緣層上，接著利用第一光罩曝露出 部份的第一光阻層，在第一光阻層上定義出孔洞圖案（Hole Patterning);對第一光阻層的表面部份進行光阻矽化的步 驟，以形成光阻砂化層（Silylated Layer)，利用在第一光 阻層上反應生成的光阻矽化層做爲罩幕，移除部份第一光 阻層；之後於第一光阻層上形成第二光阻層，利用第二光 8 (锖先閲讀背面之注意事項再填寫本頁) r 訂 本紙張尺度適用中國國家標準（CNS ) A4规格_( 210X 297公釐) ' — 輕濟部中央標準局員工消費合作社印掣 415Q59 ' A7 ______________ 五、發明説明（^ ) 罩曝露出部份的第二光阻層，在第二光阻層上定義出導線 圖案（Line Patterning)，再進行濕顯影（Wet Development)，曝光後移除部份的第二光阻層，在第二光 阻層間形成導線圖案；利用第一光阻層上的光阻矽化層做 爲第一罩幕，蝕刻第二介電層將第一光阻層內的孔洞圖案 轉換（Transfer)到第二介電層內；再利用第一光阻層上的 光阻矽化層做爲第二罩幕，蝕刻中間層將第一光阻層內的 孔洞圖案轉換到中間層內：透過第二光阻層的導線圖案蝕 刻第一光阻層，將第二光阻層內的導線圖案轉換到第一光 阻層內；利用第二光阻層與第一光阻層內的導線圖案做爲 第三罩幕，蝕刻第一介電層；再蝕刻綜合絕緣層，將第一 光阻層內的導線圖案轉換到第二介電層內，以形成導線溝 渠（Line Trench);同時將中間層內的孔洞圖案轉換到第一 介電層內，以形成接觸窗口（Contact Hole);移除第一光 阻層與第二光阻層，再沈積金屬於導線溝渠及接觸窗口內 以形成雙重嵌入式結構，之後再進行拋光（Polishing)。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說辱如 下： ·. 圖式之簡單說明： 第1圖繪示習知的一種不平坦的多層金屬結構之半導 體基底剖面圖； 第2a圖至第2b圖繪示係習知的一種雙重嵌入式結構 平坦化前與平坦牝後的半導體基底結構剖面圖： 9 本紙張尺度通用中國國家標率（CNS ) A4規格（210X297公龙） (諳先聞讀背面之注意事項再填寫本頁) 一裝 訂 經濟部中央標準局員工消費合作社印製 415059 A7 B7 五、發明説明（2 ) 第3a圖繪示係依照本發明一較佳實施例中，形成第一 光阻層後的半導體基底結構剖面圖； 第3b圖繪示係依照本發明一較佳實施例中，在第一光 阻層上定義孔洞圖案的半導體基底結構剖面圖； 第3c圖繪示係依照本發明一較佳實施例中，對第一光 阻層進行光阻矽化反應後之半導體基底結構剖面圖； 第3d圖繪示係依照本發明一較佳實施例中，在第一光 阻層中形成孔洞圖案之半導體基底結構剖面圖； 第3e圖繪示係依照本發明一較佳實施例中，對第二光 阻層進行導線定義的半導體基底結構剖面圖； 第3f圖繪示係依照本發明一較佳實施例中，在第二光 阻層間形成導線圖案,的半導體基底結構剖面圖； 第3g圖繪示係依照本發明一較佳實施例中，將第一光 阻層內的孔洞圖案轉換到第一介電層與中間層內的半導體 基底結構剖面圖； 第3h圖繪示係依照本發明一較佳實施例中，將第二光 阻層內的導線圖案轉換到第一光阻層內的半導體基底結構 剖面圖； / 第圖繪示係依照本發明一較佳實施例中，將第一光 阻層內的導線圖案轉換到綜合絕緣層中的第一介電層內， 以形成導線溝渠，以及將中間層內的孔洞圖案轉換到第二 介電層內，以形成接觸窗口的半導體基底結構剖面圖； 第.3」圖繪示係依照本發明一較佳實施例中，移走第一 光阻層與第二光阻層後在綜合絕緣層上形成雙重嵌入式圖 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本買) 一裝· -s 415059 A7 B7 五、發明説明 案的半導體基底結構剖面圖；以及 第3k圖繪示依照本發明一較佳實施例中，在導線溝 渠及接觸窗口內塡入金屬形成雙重嵌入式結構的半導體 基底結構剖面圖。 經濟部中央標準局員工消費合作社印製 元件符號說明 10基底 12第一絕緣層 14接觸窗 16第二金屬層 18第三絕緣層 31第一金屬層 33阻擋層 35金屬. 41接觸窗口 60底面介電層 80頂端介電層 91孔洞圖案 93光阻矽化層 96第二光阻層 100光罩 107曝光光線 11元件區_ 13第一金屬層 15.第ϋ絕緣層. 17介層洞 30基底 32第一絕緣層. 34第二絕緣層 40導線通道 50基底 70中間層 90第一光阻層 92第一光阻層較深層部分 95孔洞圖案 97金屬導線圖案 105曝光光線 11 n· - /. f In n I —^ϋ HI ^i·^— l J s.-a 1 (t先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠） 415059 A7 B7 經濟部中央橾準局員工消費合作社印裝 五、發明説明（/ Ο 實施例 請同時參照第3a圖至第3k圖，其繪示依照本發明一較 :佳實施例的一種利用雙重分層表面成像製程結合光阻砂化 步驟，形成雙重嵌入式結構之製造方法的結構剖面圖。 請參照第3a圖，在基底50上有由三層介電材料組成的 綜合絕緣層，包括底面介電層60、中間層70與頂端介帝層 80，底面介電層60與頂端介電層80被中間靥7〇分隔=， 第一光阻層90接著;形成在綜合絕緣層上，第〜光阻17 9〇 可做爲光阻矽化之光阻。 其中底面介電層60與頂端介電層80的形成方式，比如 以電漿化學氣相沈積法（PECVD)在低壓的環境丁形成的憐 矽玻璃（Phoshosilicate GLASS, PSG)，沈積室的壓力約爲 0.5-1 .0托爾，溫度範圍約爲300~500°C，而反應氣體砍甲 烷的流速範圍約爲100〜500標準立方公分每分鐘（sccm)， 其中加入稀釋劑的傳導氣體磷化氫PH3，流速範圍韵爲 20〜20〇sccm ;四乙基正矽酸鹽（TE0S)的氧化物也可被使 用；而底面介電層60與頂端介電層80的摩度範圍j約爲 中間層70比如氮化矽，做爲一蝕刻阻擋靨，藉以防止 在蝕刻步驟蝕刻綜合絕緣層下方，形成介層洞栓塞或接觸 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） (請先閲讀背面之注意事項再填寫本頁) 裝- 415059 經濟部中央標準局貝工消費合作社印聚 A7 87 五、發明説明（/1 ) 隔離時，中間層70上方的導線圖案會因繼續蝕刻而轉換到 中間層70下方（在第3a圖中，基底50內包括元件的下層 結構，其上可能已設有金屬層，這些並非本發明的特徵， 故不詳細敘述。）。其他的材料也可能用來當作阻擋層，使 用氮化矽是因爲氮化矽可以成爲綜合絕緣層的一部份，且 氮化矽比常用來做爲絕緣材料的二氧化矽或磷矽玻璃更不 易被蝕刻，因此氮化矽對應於下方材料的不同，可以提供 選擇性的蝕刻製程；當以聚亞醯胺（Polyinnde)做爲材料 時，旋塗式玻璃（Spin On Glass, S0G)及化學氣相沈積（CVD) 的氮化物也適合做爲蝕刻阻擋層；一般來說大多使用氮化 矽，形成方式比如電漿化學氣相沈積法（PECVD)，厚度範圍 約爲500〜2000A，實祭厚度要取決於氧氣對氮氣的選擇性。 在第3a圖中所示的頂端介電層80在形成後會被磨 平，進行方式比如化學機械硏磨法、回蝕法或利用覆蓋的 方式使頂端介電層80變的平坦；儘管如此，這些技術必須 ‘被熟習，特別是當絕緣層覆蓋於金屬層上方時，因爲在越 過邊角（Edge)或金屬導線線路的地方，可能會有表面不平 坦的現象。此外，即使第3a圖中的頂端介電層δ0沒有顯 示出不規則的表面，當光阻覆蓋在其上方時，在邊角或導 線線路的部份，光阻的厚度會改變，因爲其他區域的高度 略低於導線的表面，故在導線線路上方的光阻會較其他區 域薄；因此，在定義光阻的微影製程中，薄的區域會曝光 過度（Overexpose)，而較厚的區域則會曝光不足 (underexpose)，這種結果會導致越過線路的光阻圖案有線 13 本紙張尺度適用中國國家楯準（CNS ) Λ4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標準局員工消费合作社印^ 415059 A7 B7 五、發明説明（/z) 寬的變化，當導線的階梯高度接近線寬的大小時，這種線 寬的變化造成很大的誤差，這種誤差是製程中不允許的。 另外，在厚的光阻層內產生的駐波效應（Standing Wave Ef feet)會降低最小的解析度，如S . Wol f and R. N. Tauber , iCSilicon Processing for the VLSI Era ,55 vo 1 . 1, Lattice Press, Sunset Beach, California, 1986，p.423 中所提 到的說明。最後，反射性的基底也會降低厚光阻的解析度， 這竖問題可利用多層光阻（Multi Layer Resist, MLR)步驟 來改善，多層光阻的第一層是厚且平坦的，第二層爲一薄 的影像複製層（Image Transcribing Layer)，請參考 Wolf 在同一頁的敘述，無論如何，必須彤成兩層光阻，且氧化 物薄膜也可被用來當作中間層，做爲較下層的蝕刻罩幕。 對於雙重嵌入式的製程而言，多層光阻必須被重複運用兩 次以形成連接孔洞層及金屬層；在本發明中，只有一層光 阻層被用來同時形成垂直的孔洞及水平的金屬連線圖案 (Pattern)，較優於習知必須使用到兩道完整的光阻層的製 程。本發明藉由在光阻層上進行光阻矽化反應，使部份的 光阻表面變成玻璃態，以做爲蝕刻罩幕；光阻矽化反躍不 只提供較好的解析度（resolution)，更提供較大的焦距 (Focus)深度，使影像只形成在表面，因此降低了焦距深度 的損失及下方基底的反射性。在此以光阻矽化反應形成的 玻璃罩幕，對下方的絕緣介電層進行蝕刻，所以不需要像 傳統的製程再使用一中間層，且光阻矽化的光阻厚度較 薄，因此具有高吸收的特性。 _______U____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公费） (請先閲讀背面之注意事項再填寫本頁) "裝_ 415059 經濟部中央標準局貝工消費合作枉印製 A7 B7 五、發明説明（/ 5) 在第3a圖中’頂端介電層80上方覆蓋第一光阻層90， 所用的成分比如：化學倍增型光阻劑（Chemical Ampl ification Resist，CAR) ’ 含有感光酸性反應物（Photo Acid Generator，PAG)，或是Novalac基礎的光阻劑，含 有感光酸性化合物（Photo Acid Compound, PAC)的試劑； 這兩種形式都是負型（Negative Type)的光阻，在使用反向 色調罩幕（Reversed Tone Mask)下也可以使用正型的光 阻。第一光阻層90被甩來形成垂直的孔洞圖案91，CAR被 用來取代傳統的感光試劑，比如在日本的T0K使用正型或 .負型光阻時，分別使用TOK007及TOKN908。 請參照第3b圖，第一光阻層的厚度範圍約爲〇.4~0.8 #m，光罩1〇〇被用來進行曝光1〇5,曝露出第一光阻層90， 形成垂直的孔洞圖案91，曝光的光線105照射在第一光阻 層90上，使卩八0或？八(：變成酸進而轉換成樹脂，曝光量約 爲20〜200毫焦耳/平方公分。接著將第一光阻層90進行硬 烤（hard bake)，溫度約爲100~200°C，以在未曝光的孔洞 圖案91區域形成交連（Cross-Linking);接著對第一光阻 層90曝露出來的區域進行光阻矽化反應，光阻矽化的歩驟 在溫度範圍約爲100〜200°C時，將一種甲矽烷基化試劑擴散 .進曝光的區域，藉著将矽導入光阻層的有機化合物中，形 成含矽量高的光阻矽化層93，結構如第3c圖所示；反應會 影響曝光的區域90，而不會影響形成交連的區域91，且第 一光阻層較深層的部份92也不受影響；光阻矽化層93厚 度約爲1000〜4000A，用來進行光阻矽化反應的較佳試劑比 _ 15 本紙張尺度適用中國國家橒準（CNS ) Λ4規格（Ή0Χ 297公釐） (諳先聞讀背面之注項再填寫本頁) 訂This paper size applies to China National Standards (CNS > Λ4 specification (2 丨 〇 > < 297 mm)) Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 415059 Λ7 ___________B7_ 5. Description of the invention (") Part, and can be effectively applied to the manufacture of semiconductor substrates and wafers, it will be a great advantage. Therefore, the main object of the present invention is to provide a method of dual embedded definition to manufacture semiconductor substrates by using surface imaging steps. With the chip, an improved photoresist silicidation (Siiyiation) process is used to effectively improve the current dual-embedded process. Another main objective of the present invention is to provide a method for defining dual-embedded 'dual-embedded A photoresist silicidation step is added to the formula definition process. Yet another main object of the present invention is to improve the method of dual embedded definition 'improve the alignment of the wires under the interconnect window contact pattern (A1ignment) Another main purpose of the present invention is to provide a method of dual embedded definition, which reduces alignment tolerance and control. Based on the above and other objectives of the present invention, a method of dual embedded definition is proposed. The brief description of this method is as follows: a base is proposed to improve the integration. An insulating layer, wherein the integrated green insulation layer includes a first dielectric layer, which is separated from the second dielectric layer through an intermediate layer or an etch barrier layer; and a photoresist silicified first photoresist layer is formed on the integrated insulating layer, Then using the first photoresist to expose a portion of the first photoresist layer to define a hole pattern on the first photoresist layer; performing a photoresist silicidation step on the surface portion of the first photoresist layer, In order to form a photoresist sanded layer, a photoresist silicide layer formed on the first photoresist layer is used as a mask to remove a portion of the first photoresist layer; and then on the first photoresist layer Form the second photoresist layer and use the second light 8 (锖 Please read the notes on the back before filling this page) r The paper size of the book is applicable to China National Standard (CNS) A4 specifications_ (210X 297mm) '— Qingji Ministry of Central Standards Bureau staff consumer cooperatives 415Q59 'A7 ______________ 5. Description of the Invention (^) The second photoresist layer on the exposed part of the mask, defines the line patterning on the second photoresist layer, and then performs wet development (Wet Development). After exposure A portion of the second photoresist layer is removed to form a wire pattern between the second photoresist layers; the photoresist silicide layer on the first photoresist layer is used as the first mask, and the second dielectric layer is etched to convert the first photoresist layer. The hole pattern in the resist layer is transferred to the second dielectric layer; the photoresist silicide layer on the first photoresist layer is used as the second mask, and the intermediate layer is etched to pores in the first photoresist layer. Pattern transfer into the intermediate layer: the first photoresist layer is etched through the wire pattern of the second photoresist layer, and the wire pattern in the second photoresist layer is converted into the first photoresist layer; the second photoresist layer and the first A wire pattern in a photoresist layer is used as a third mask to etch the first dielectric layer; and then a comprehensive insulating layer is etched to convert the wire pattern in the first photoresist layer into the second dielectric layer to form a wire Trench (Line Trench); at the same time transform the hole pattern in the middle layer to A dielectric layer is formed to form a contact hole; the first photoresist layer and the second photoresist layer are removed, and then metal is deposited in the wire trench and the contact window to form a double embedded structure, and then polished. (Polishing). In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: · Brief description of the drawings: Section 1 Figure 2 shows a conventional semiconductor substrate cross-section view of an uneven multilayer metal structure; Figures 2a to 2b show a conventional semiconductor substrate structure cross-section view before and after flattening a dual embedded structure : 9 paper sizes are in accordance with China National Standards (CNS) A4 specifications (210X297 male dragons) (谙 First read the notes on the back and then fill out this page) One binding Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 415059 A7 B7 Five 3. Description of the invention (2) FIG. 3a is a cross-sectional view of a semiconductor substrate structure after a first photoresist layer is formed according to a preferred embodiment of the present invention; FIG. 3b is a preferred embodiment according to the present invention. 3c is a cross-sectional view of a semiconductor substrate structure defining a hole pattern on the first photoresist layer; FIG. 3c shows a semiconductor after a photoresist silicidation reaction is performed on the first photoresist layer according to a preferred embodiment of the present invention. Cross-sectional view of the bottom structure; FIG. 3d is a cross-sectional view of a semiconductor substrate structure in which a hole pattern is formed in a first photoresist layer according to a preferred embodiment of the present invention; FIG. In the embodiment, a cross-sectional view of a semiconductor substrate structure with a wire defined for the second photoresist layer; FIG. 3f shows a semiconductor substrate structure in which a wire pattern is formed between the second photoresist layers according to a preferred embodiment of the present invention. 3g is a cross-sectional view of a semiconductor substrate structure in which a hole pattern in a first photoresist layer is converted to a first dielectric layer and an intermediate layer according to a preferred embodiment of the present invention; FIG. 3h The drawing is a cross-sectional view of a semiconductor substrate structure in which a conductive pattern in a second photoresist layer is converted into a first photoresist layer according to a preferred embodiment of the present invention; In an embodiment, the wire pattern in the first photoresist layer is converted into the first dielectric layer in the integrated insulation layer to form a wire trench, and the hole pattern in the intermediate layer is converted into the second dielectric layer. To make contact Sectional view of the semiconductor substrate structure of the window; FIG. 3 "shows a double-embedded pattern formed on the integrated insulating layer after removing the first photoresist layer and the second photoresist layer according to a preferred embodiment of the present invention. 10 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this purchase) One pack · -s 415059 A7 B7 V. Sectional view of the semiconductor substrate structure of the invention And FIG. 3k is a cross-sectional view of a semiconductor substrate structure in which a metal is inserted into a wire trench and a contact window to form a dual embedded structure according to a preferred embodiment of the present invention. The Ministry of Economic Affairs, Central Bureau of Standards, Consumer Cooperatives printed component symbols 10 base 12 first insulation layer 14 contact window 16 second metal layer 18 third insulation layer 31 first metal layer 33 barrier layer 35 metal. 41 contact window 60 bottom surface Electrical layer 80 top dielectric layer 91 hole pattern 93 photoresist silicide layer 96 second photoresist layer 100 photomask 107 exposure light 11 element area _ 13 first metal layer 15. first insulating layer. 17 via hole 30 substrate 32 First insulating layer. 34 second insulating layer 40 wire channel 50 substrate 70 intermediate layer 90 first photoresist layer 92 deeper portion of first photoresist layer 95 hole pattern 97 metal wire pattern 105 exposure light 11 n ·-/. F In n I — ^ ϋ HI ^ i · ^ — l J s.-a 1 (t read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 cm) 415059 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (/ 〇 For embodiments, please refer to Figures 3a to 3k. It shows the use of the dual splitting method according to the first preferred embodiment of the present invention. Layer surface imaging process combined with photoresist sanding step, A cross-sectional view of a manufacturing method of a dual embedded structure. Referring to FIG. 3a, there is a comprehensive insulating layer composed of three dielectric materials on a substrate 50, including a bottom dielectric layer 60, an intermediate layer 70, and a top dielectric. Layer 80, the bottom dielectric layer 60 and the top dielectric layer 80 are separated by a middle 靥 70, the first photoresist layer 90 is then formed on the integrated insulating layer, and the first to the photoresist 1790 can be used as photoresist silicidation The formation method of the bottom dielectric layer 60 and the top dielectric layer 80 is, for example, Phoshosilicate GLASS (PSG) formed by plasma chemical vapor deposition (PECVD) in a low pressure environment. The pressure of the chamber is about 0.5-1. 0 Torr, the temperature range is about 300 ~ 500 ° C, and the flow rate range of the reaction gas to cut methane is about 100 ~ 500 standard cubic centimeters per minute (sccm). Conducting gas phosphine PH3, with a flow rate range of 20 ~ 20 Sccm; Tetraethyl orthosilicate (TE0S) oxide can also be used; and the friction between the bottom dielectric layer 60 and the top dielectric layer 80 The range j is about the intermediate layer 70, such as silicon nitride, as an etch stopper. Prevent the formation of via plugs or contact under the integrated insulating layer during the etching step. This paper is sized to the Chinese National Standard (CNS) A4 (210X29? Mm) (Please read the precautions on the back before filling this page). 415059 Central Standards Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperative, Printed Poly A7 87 V. Description of the invention (/ 1) During isolation, the wire pattern above the intermediate layer 70 will be transferred to the lower portion of the intermediate layer 70 due to continued etching (in Figure 3a, The substrate 50 includes a lower layer structure of the element, and a metal layer may be provided thereon. These are not the features of the present invention, and therefore are not described in detail. ). Other materials may also be used as the barrier layer. Silicon nitride is used because silicon nitride can be part of a comprehensive insulating layer, and silicon nitride is more commonly used as silicon dioxide or phosphosilicate glass as an insulating material. It is more difficult to be etched, so silicon nitride can provide a selective etching process corresponding to the different materials below. When using polyinnde as the material, spin-on glass (S0G) and Chemical vapor deposition (CVD) nitrides are also suitable as etch barriers; generally, silicon nitride is mostly used, such as plasma chemical vapor deposition (PECVD), with a thickness range of about 500 ~ 2000A. The thickness depends on the selectivity of oxygen to nitrogen. The top dielectric layer 80 shown in FIG. 3a is ground after being formed, and the top dielectric layer 80 is flattened by a method such as a chemical mechanical honing method, an etch-back method, or a cover method; These technologies must be familiar, especially when the insulating layer covers the metal layer, because the surface may be uneven when it crosses the edge or metal wire line. In addition, even though the top dielectric layer δ0 in Fig. 3a does not show an irregular surface, when the photoresist is covered thereon, the thickness of the photoresist will change at the corners or the part of the wiring, because other areas Is slightly lower than the surface of the wire, so the photoresist above the wire line will be thinner than other areas; therefore, in the lithography process that defines the photoresist, thin areas will be overexposed, and thicker areas Will result in underexpose. This result will cause the photoresist pattern across the line to be wired. 13 This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling in This page) Binding. Ordered by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ 415059 A7 B7 V. Description of the invention (/ z) The change in width, when the step height of the wire approaches the size of the line width, this line width change causes Large error, this error is not allowed in the process. In addition, the standing wave effect (Standing Wave Ef feet) in the thick photoresist layer will reduce the minimum resolution, such as S. Wol f and RN Tauber, iCSilicon Processing for the VLSI Era, 55 vo 1. 1.1, Lattice Instructions mentioned in Press, Sunset Beach, California, 1986, p. 423. Finally, the reflective substrate also reduces the resolution of the thick photoresist. This vertical problem can be improved by using the Multi Layer Resist (MLR) step. The first layer of the multilayer photoresist is thick and flat. The layer is a thin Image Transcribing Layer. Please refer to Wolf ’s description on the same page. In any case, two layers of photoresist must be formed, and the oxide film can also be used as an intermediate layer as Lower etching mask. For the dual-embedded process, the multilayer photoresist must be reused twice to form the connection hole layer and the metal layer; in the present invention, only one photoresist layer is used to form vertical holes and horizontal metal connections at the same time. The line pattern is better than the conventional process that must use two complete photoresist layers. In the present invention, by performing a photoresist silicidation reaction on a photoresist layer, a part of the photoresist surface becomes a glass state as an etching mask; the photoresist silicidation not only provides better resolution, but also provides better resolution. Provide a larger depth of focus, so that the image is only formed on the surface, so the loss of depth of focus and the reflectivity of the underlying substrate are reduced. Here, a glass cover formed by a photoresist silicidation reaction is used to etch the underlying insulating dielectric layer, so there is no need to use an intermediate layer like the traditional process, and the photoresist silicified photoresist thickness is thin, so it has a high thickness. Absorptive properties. _______U____ This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 public expense) (Please read the precautions on the back before filling out this page) " Packing_ 415059 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Co-consumer Cooperative Printing A7 B7 V. Description of the invention (/ 5) In FIG. 3a, the first photoresist layer 90 is covered over the top dielectric layer 80. The components used are, for example, Chemical Amplification Resist (CAR). Photo acid generator (PAG), or Novalac-based photoresist, containing photoacid compound (PAC); Both forms are negative (Negative Type) photoresist, You can also use a positive type photoresist when using a reversed tone mask. The first photoresist layer 90 is shaken to form a vertical hole pattern 91, and CAR is used to replace the conventional photosensitizing agent. For example, when TOK007 in Japan uses a positive or negative photoresist, TOK007 and TOKN908 are used, respectively. Please refer to FIG. 3b. The thickness of the first photoresist layer is about 0.4 ~ 0.8 #m. The photomask 100 is used for exposure 105, and the first photoresist layer 90 is exposed to form a vertical In the hole pattern 91, the exposed light 105 is irradiated on the first photoresist layer 90, so that 卩 80 or? Eight (: becomes acid and then into resin, the exposure is about 20 ~ 200 mJ / cm². Then the first photoresist layer 90 is hard bake, the temperature is about 100 ~ 200 ° C, Cross-linking is formed in the unexposed area of the hole pattern 91. Then, a photoresist silicidation reaction is performed on the exposed area of the first photoresist layer 90. When the temperature of the photoresist silicidation step is about 100 ~ 200 ° C Diffusion of a silylating agent into the exposed area, and by introducing silicon into the organic compound of the photoresist layer, a photoresist silicide layer 93 having a high silicon content is formed. The structure is shown in FIG. 3c; Affects the exposed area 90 without affecting the cross-linked area 91, and the deeper part 92 of the first photoresist layer is not affected; the thickness of the photoresist silicide layer 93 is about 1000 ~ 4000A, which is used for photoresist Better reagent ratio for silicidation_ 15 This paper size is applicable to China National Standards (CNS) Λ4 specification (Ή0 × 297 mm) (闻 Read the notes on the back before filling this page) Order
iJ 經濟部中央標準局員工消費合作社印裝 415059 .... A7 __. _ 87 ___ 五、發明説明（/斗） 如：四甲基二砂氮院（tetra-methyl di-silazane，TMDS)， 其中包括砍；另外六甲基二砂氮院（1^\&11^〖1^1(1丨3丨1&2&116, HMDS.)、矽甲烷也可被使用。 請參照第3d圖，以光阻矽化層93做爲第一罩幕進行蝕 刻，形成孔洞圖案95，形成方式比如在高密度電漿蝕刻系 統中（例如Lam 9400)，以氧氣與二氧化硫氣體進行乾蝕 刻。 接著，請參照第3e圖，在光阻矽化層93上方形成一負 型的第二光阻層96，厚度約爲0.2〜0. δ# m ;之後再形成光 罩101於第二光阻層96上方，進行曝光107，定義出金屬 導線圖案97，曝光量約爲20-200毫焦耳/平方公分，再將 基底置於溫度約爲100~200°(：下進行烘烤，未曝光的部份即 成爲導線圖案，使用的光阻比如：CAR型式的負光阻例如 TOK908，或是Navaloc基礎光阻；當使用到反向色調光幕 時，則需採用正光阻。 之後，請參照第3f圖，進行濕顯影步驟，比如以靜置 顯影（St ream Puddle)技術進行約45〜65秒（相關技術請參 考 S. Wolf and R, N. Tauber, “Silicon Processing for the VLSI Era,” vo1. 1，Lattice Press, Sunset Beach； Califcmiia, 1986, p.443 )，包含孔洞95及導線97的雙 重嵌入式結構即在第一光阻層90與第二光阻層96內形 成。 請參照第3g圖，更進一步的進行乾蝕刻，在高密度電 漿下加入成分包含流速50~150sccm的氬氣，10〜1.50sccm 16 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公浼) {請先閲讀背面之注意事項再填寫本頁) 裝. 訂 415059 經濟部中央標準局負工消费合作社印裝 A7 B7 五、發明説明（/5") 的三氟甲烷’將孔洞圖案95轉換到下方的頂端介電層80 及中間層70。 接著’請參照第3h圖，以另一光阻鈾刻步驟，在高密 度電發餓刻系統中，加入成分包含流速1〇~25sccm的氧氣， 40~80sccm的氯氣，1〇〜g〇SCCffl的二氧化硫，〇~50sccm的四 氟甲烷；在蝕刻第二光阻層96的時候，同時將第二光阻層 96內的導線圖案97轉換到光阻矽化層93 〇 之後’請參照第3i圖，再進行乾蝕刻步驟，在高密度 電漿氧化蝕刻器中，加入成分包含流速50〜150sccm的氬 氣’ 10〜l50sccni的三氟甲烷，〇〜20sccm的丁烯，將第一光 阻層內的導線圖案轉換到頂端介電層內，再將頂端介電層 內的孔洞圖案轉換到底面介電層60內。 接著’請參照第3j圖，去除第二光阻層96、光阻矽化 層93及第一光阻層92,去除方式比如傳統的硏磨或光阻剝 除步驟；之後請參照第3k圖，將金屬塡入導線溝渠及接觸 窗口內’再將多餘的金屬以化學機械硏磨法除去，即完成 雙重嵌入式結構，金屬形成的方式比如電鍍，所用的金屬 比如銅或鋁銅合金。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準·（ CNS ) Λ4規格（210X 297公釐） (請先閲讀背面之注意事項再填窝本")iJ Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 415059 .... A7 __. _ 87 ___ V. Description of the invention (/ bucket) For example: tetra-methyl di-silazane (TMDS), These include chopping; other hexamethyl disaronitrile hospitals (1 ^ \ & 11 ^ 〖1 ^ 1 (1 丨 3 丨 1 & 2 & 116, HMDS.), And silylmethane can also be used. Please refer to section 3d In the figure, the photoresist silicide layer 93 is used as the first mask to etch to form a hole pattern 95. The formation method is, for example, dry etching in a high-density plasma etching system (such as Lam 9400) with oxygen and sulfur dioxide gas. Please refer to FIG. 3e. A negative second photoresist layer 96 is formed on the photoresist silicide layer 93 with a thickness of about 0.2 ~ 0. Δ # m; and then a photomask 101 is formed on the second photoresist layer 96. , Perform exposure 107, define the metal wire pattern 97, the exposure is about 20-200 millijoules / cm2, and then the substrate is baked at a temperature of about 100-200 ° (:, the unexposed part is Become a wire pattern, use a photoresist such as: CAR type negative photoresist such as TOK908, or Navaloc basic photoresist; when using In the case of a reverse-tone light curtain, a positive photoresist is required. After that, please refer to Figure 3f to perform a wet development step, for example, about 45 to 65 seconds with the St Ream Puddle technology (refer to S for related technologies) Wolf and R, N. Tauber, "Silicon Processing for the VLSI Era," vo1. 1, Lattice Press, Sunset Beach; Califcmiia, 1986, p. 443), the dual embedded structure containing holes 95 and wires 97 is in The first photoresist layer 90 and the second photoresist layer 96 are formed. Please refer to FIG. 3g for further dry etching, and add a composition containing argon at a flow rate of 50 to 150 sccm under high density plasma, and 10 to 1.50 sccm. 16 This paper size applies to Chinese National Standard (CNS) A4 (210X297 gong) (Please read the precautions on the back before filling this page). Order 415059 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, printed A7 B7 5. The description of the invention (/ 5 ") of trifluoromethane 'converts the hole pattern 95 to the top dielectric layer 80 and the intermediate layer 70 below. Then' Please refer to Figure 3h for another photo-resistance engraving step at high density Electric haircut system, plus The composition contains oxygen at a flow rate of 10 to 25 sccm, chlorine gas at 40 to 80 sccm, sulfur dioxide at 10 to g0 SCCffl, and tetrafluoromethane at 0 to 50 sccm. When the second photoresist layer 96 is etched, the second photoresist is simultaneously After the conductive pattern 97 in the layer 96 is converted to the photoresist silicide layer 93, please refer to FIG. 3i, and then perform a dry etching step. In a high-density plasma oxidation etcher, add argon containing a flow rate of 50 to 150 sccm. 10 ~ l50sccni trifluoromethane, 0 ~ 20sccm of butene, convert the wire pattern in the first photoresist layer to the top dielectric layer, and then convert the hole pattern in the top dielectric layer to the bottom dielectric layer 60 Inside. Next, please refer to FIG. 3j, remove the second photoresist layer 96, the photoresist silicide layer 93, and the first photoresist layer 92, such as a conventional honing or photoresist stripping step; then refer to FIG. 3k, Put the metal into the wire channel and the contact window, and then remove the excess metal by chemical mechanical honing to complete the dual embedded structure. The metal is formed in a manner such as electroplating, and the metal used is copper or aluminum-copper alloy. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size applies to Chinese national standard (CNS) Λ4 size (210X 297mm) (Please read the precautions on the back before filling the book ")