A7 B7 . doc/005 五、發明説明（I ) 本發明是有關於一種製造一般及特殊極大積體電路 (Ultra Large Scale Integration, ULSI)晶片之方法，且 特別是有關於一種利用單一光阻的步驟形成層間連線，提 供一種改良式的雙重嵌入式（Dual Damascene)金屬導線技 術。 半導體晶片的佈線（Wiring)技術在積體電路層數越來 越多時，對於金屬處理（Metallization)步驟方式的要求越 來越多。傳統的金屬處理方式在蝕刻每一層金屬時，必須 在每一層金屬上形成一層定義的光阻層，藉以形成金屬導 線；金屬層也必須連往半導體基底上的元件區以製作晶 片，同樣的，在基底上形成其他金屬層做爲電路。垂直的 連線透過孔洞（Hole)形成，該些孔洞位於將金屬層分隔開 的絕緣層內；在各層形成孔洞時必須用到個別的光阻步 驟’當金屬處理的層數增加時，需要光阻的步驟也會增加， 如此會增加製作半導體晶片的複雜性。目前在極大積體電 路技術中，如何將單一光阻步驟用在同時對水平溝渠及垂 直孔洞做金屬處理上，如何在高積集度的晶片上以相關的 技術形成層間連線將是一個挑戰。 當技術由超大型積體電路（VLSI)提昇到極大積體電路 (ULSI) ’爲了使其更容易的產生電子遷移，以提昇速度及 操作電腦，半導體工業發展新的方法與技術以生產緊密堆 積的半導體晶片。如熟悉此項技藝者所知，在緊密堆積的 晶片內’較近的元件距離不只是以元件實際的縮短距離來 提供電子訊號較快的傳遞速度，也降低了訊號在媒介傳遞 3 本紙張尺度適用中國固家榡準（CNS ) A4規格（210X297公釐） f .· - (請先閲讀背面之注意事項再填寫本頁) *-* 丁 經濟部中央標準局*:工消費合作社印聚 經濟部中央標率局貝工消费合作社印策 2183twf.doc/005 A7 ___B7 五、發明説明（^ ) 時產生的阻抗；另一方面，緊密的堆積可使極大積體電路 (ULSI)用極小的元件與層間連線製作。層間連線的運作必 須利用減少金屬導線剖面的條紋數，使增加的電阻最小以 傳遞訊號；重要的是必須盡可能的避免阻抗匹配，以及有 利於固態連線。 在半導體晶片上通常包含一或多個導線，這些彼此導線 由一層絕緣層互相分離，或是更進一步的藉著另一絕緣層 與接近半導體表面的元件分離；這些導線彼此互相連接， 且在適當的地方與元件相連，導線連接的方式是在絕緣層 的孔洞中塡入金屬。習知有許多方法可以形成金屬線與層 間連線，這些透過絕緣層使金屬線彼此相連的孔洞（Hole) 稱爲介層洞（Via Hole)，而孔洞通過絕緣層連往位於下方 的元件時則稱爲接觸窗口（Contact Hole)，這些孔洞通常 是於半導體基底上沈積絕緣層後，再進行蝕刻絕緣層而形 成的。之後再覆蓋一層金屬在絕緣層上方，藉以塡滿孔洞， 然後在透過定義（Pat tern)金屬層上的光阻進行蝕刻形成 金屬線。第一層金屬層透過接觸窗與下方的元件做電性接 觸，使金屬可以透過介電絕緣材料往下延伸到元件上；第 二層金屬層以相同的方法形成，且透過介層洞與下方的金 屬層進行金屬層間的接觸。另外，這些孔洞也常分別的被 塡充金屬作爲金屬栓塞（Plug)，再進行平坦化使之對應於 絕緣層的表面，之後再沈積金屬層以形成介層洞栓塞的接 觸，然後蝕刻沈積的金屬層，以形成製程所要求的個別化 導線層。 4 本紙張又度適用中國國家揉準（CNS ) A4坑格（210X297公釐） 、；裝-- /1 (請先閲诊背面之注意事項再填寫本頁) 2183twf. doc/005 B7 _ 五、發明説明（3 ) 爲了在金屬連線接觸或多層導線間介層洞栓塞的接^ 部份提供堅固的接觸區域，通常必須增加金麋連線與 的空間，以掩蓋過平版印刷製程本身產生的覆蓋_/0 (Overlay Error)或製程偏差。這種設計的基本規則會使付 電路尺寸增加，造成元件設計的密度明顯的降低’·因此’ 發展微影技術與製程來改善覆蓋誤差或製程容忍力是1必'須 的。爲了在考量覆蓋容忍以及微影的花費下’將晶片最小 化，自動對準（Self-Aligned)的製程於是發展。 另外，在基底的金屬層間形成接觸也會有一些其他的問 題存在，在蝕刻絕緣層形成接觸窗口時，接觸窗口的側壁 必須傾斜，以確保在金屬層有好的連續性；斜面越陡峭’ 在金屬沈積方面越有可能因接觸窗的角度而造成斷路。然 而，運用緩慢傾斜的側壁以確保金屬導線的連續性會提高 晶片的使用面積，且使接觸窗無法如預期般密集；此外， 使用接觸窗產生不規則且不平坦的表面會使製作隨後的層 間連線變得困難。 經濟部中央標準局員工消费合作社印聚 --------Τ装-- 。請先聞參背面之注意事項存填寫本頁) *1Τ ^ 請參照第1圖，第1圖是習知一種製作半導體元件方法 的示意圖。提供一基底10，其上已定義出元件區11，形成 第一絕緣層12並定義出接觸窗；接著沈積第一金屬層13， 透過接觸窗14連接元件區11。同樣的，第二金屬層16透 過在第二絕緣層15上定義形成的介層洞17,連接第一層金 屬層13，此結構利用第三絕緣層18做爲保護層 (Passivate)。雖然第1圖所描述的結構並非基準，但爲顯 示出非常不規則的表面的一個例子，這種表面不規則的情 5 本紙張尺度逋用中國國家^準（CNS > A4規格（210Χ297公釐) 2183twf,doc/005 A7 B7 經濟部中央梯準局貝工消费合作社印焚 五、發明説明（V·) 形會造成可靠度方面的問題；其中一個問題就是，當兩層 間的絕緣層變薄時，第一金屬靥與第二金屬層間的s區域 會有短路危險’以及當金屬層變薄時，在〇區域會產生電 路斷路的危險。 習知的一種解決上述問題的方法稱爲雙重嵌入式（Dual Damascence)製程，此製程最簡單的形式是在絕緣層上進 行，此絕緣層形成於在基底上’且經過平坦化；對絕緣層 進行定義’水平方向的溝渠與垂直方向的孔洞經由蝕刻絕 緣層同時形成。在基底上’若通過第一絕緣層，那金屬導 線與孔洞會往下連往元件區；假若通過上方的絕緣層，那 就是連接另一層金屬層。接下來沈積金屬在已設有上述結 構的基底上藉以塡滿溝渠與孔洞，以此同時形成金屬導線 及層間連線孔洞。最後，利用化學機械硏磨法（Chemical Mechanical Polish，CMP)使表面平坦，並且準備進行另一 個雙重嵌入式的結構，以完整的將導線嵌入進水平的溝渠 與垂直的孔洞內，此即爲製程的雙重性（Duality)。 請同時參照第2a圖與第2b圖，第2a圖繪示爲進行化 學機械硏磨前的雙重嵌入式結構；第2b圖繪示爲經過化學 機械硏磨的雙重嵌入式結構。兩道微影步驟及兩層絕緣層 分別被一蝕刻阻擋層（Etch Stop Layer)分開’結構敘述如 下：提供表面平坦的基底30，其中有定義圖案的第一金屬 層31，第一絕緣層32被沈積覆蓋在第一金屬層31上，將 第一絕緣層31平坦化後，覆蓋上蝕刻阻擋層33 :利用第一 道微影蝕刻步驟在蝕刻阻擋層33上定義出接觸窗口 ’該處 6 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） ' ,裝-- /IV (請先背面之注^K項再填寫本頁)A7 B7. Doc / 005 V. Description of the Invention (I) The present invention relates to a method for manufacturing general and special Ultra Large Scale Integration (ULSI) chips, and in particular to a method using a single photoresistor. Steps to form interlayer connections provide an improved dual damascene metal wire technology. As the number of integrated circuit layers in semiconductor wafer wiring (Wiring) technology increases, the requirements for metallization (Metallization) steps are increasing. In the traditional metal processing method, when each layer of metal is etched, a defined photoresist layer must be formed on each layer of metal to form a metal wire; the metal layer must also be connected to the element area on the semiconductor substrate to make a wafer. Similarly, Other metal layers are formed on the substrate as a circuit. Vertical lines are formed through holes, which are located in the insulating layer that separates the metal layers; a separate photoresist step must be used when forming holes in each layer. 'When the number of metal processing layers increases, it is necessary to The step of photoresist will also increase, which will increase the complexity of fabricating a semiconductor wafer. At present, in the integrated circuit technology, how to use a single photoresist step for the metal processing of horizontal trenches and vertical holes at the same time, how to form interlayer connections on the high-concentration wafer with related technologies will be a challenge. . When technology is upgraded from very large integrated circuits (VLSI) to very large integrated circuits (ULSI) 'In order to make it easier to generate electron migration to increase speed and operate computers, the semiconductor industry develops new methods and technologies to produce tightly packed Semiconductor wafer. As is known to those skilled in the art, 'closer component distances in tightly packed wafers not only provide faster transmission of electronic signals by the actual shortened distance of the components, but also reduce the signal transmission in the medium. Applicable to China Gujia Standard (CNS) A4 specification (210X297 mm) f ..-(Please read the precautions on the back before filling out this page) *-* Ding Central Bureau of Economic Affairs *: Industrial and Consumer Cooperative Cooperative Economy Ministry of Standards and Standards Bureau, Shellfish Consumer Cooperative, India 2183twf.doc / 005 A7 ___B7 V. Impedance generated during the description of the invention (^); On the other hand, the close-packing can make the extremely integrated circuit (ULSI) use very small components Create with connection between layers. The operation of the interlayer connection must reduce the number of stripes on the cross section of the metal wire to minimize the increased resistance to transmit signals; it is important to avoid impedance matching as much as possible and facilitate solid state connections. Semiconductor wafers usually contain one or more wires, which are separated from each other by an insulating layer, or further separated from components close to the semiconductor surface by another insulating layer; these wires are connected to each other and, where appropriate, It is connected to the component at the place where the wire is connected by inserting metal into the hole of the insulation layer. There are many known methods to form metal lines and interlayer connections. These holes, which connect the metal lines to each other through the insulating layer, are called via holes, and when the hole is connected to the underlying component through the insulating layer They are called contact holes. These holes are usually formed by depositing an insulating layer on a semiconductor substrate and then etching the insulating layer. After that, a layer of metal is covered over the insulating layer to fill the holes, and then a metal line is formed by etching through a photoresist on the metal layer. The first metal layer makes electrical contact with the component below through the contact window, so that the metal can extend down to the component through the dielectric insulating material; the second metal layer is formed in the same way and passes through the hole in the dielectric layer and below The metal layer makes contact between the metal layers. In addition, these holes are often filled with metal as metal plugs, and then planarized to correspond to the surface of the insulating layer, and then a metal layer is deposited to form the contact of the via hole plug, and then the deposited A metal layer to form the individualized wire layers required by the process. 4 This paper is again suitable for China National Standard (CNS) A4 pit (210X297 mm), loaded-/ 1 (Please read the precautions on the back of the consultation before filling this page) 2183twf. Doc / 005 B7 _ 5 3. Description of the invention (3) In order to provide a solid contact area in the connection part of the metal connection or the interlayer hole plug of the multilayer wire, the space of the gold moose connection must be increased to cover the generation of the lithographic process itself. Overlay_ / 0 (Overlay Error) or process deviation. The basic rules of this design will increase the size of the auxiliary circuit and cause a significant reduction in the density of the component design. Therefore, it is necessary to develop lithography technology and processes to improve coverage errors or process tolerance. In order to minimize the wafer's consideration of coverage tolerance and the cost of lithography, a self-aligned process was developed. In addition, there are also some other problems in forming contact between the metal layers of the substrate. When etching the insulating layer to form a contact window, the sidewall of the contact window must be inclined to ensure good continuity in the metal layer; the steeper the slope is Metal deposition is more likely to cause an open circuit due to the angle of the contact window. However, the use of slowly sloping sidewalls to ensure the continuity of the metal leads will increase the area of the chip and make the contact windows not as dense as expected. In addition, the use of contact windows to create an irregular and uneven surface will cause subsequent interlayer fabrication. Connection becomes difficult. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs -------- Τ 装-. Please read the notes on the back of the reference first and fill in this page) * 1Τ ^ Please refer to Figure 1, which is a schematic diagram of a conventional method for manufacturing semiconductor devices. A substrate 10 is provided, on which the element region 11 has been defined, a first insulating layer 12 is formed and a contact window is defined; then a first metal layer 13 is deposited, and the element region 11 is connected through the contact window 14. Similarly, the second metal layer 16 is connected to the first metal layer 13 through a via hole 17 defined and formed on the second insulating layer 15. This structure uses the third insulating layer 18 as a passivate. Although the structure described in Figure 1 is not a benchmark, it is an example of a very irregular surface. This paper has an irregular surface. The size of this paper uses the Chinese national standard (CNS > A4 size (210 × 297) Ii) 2183twf, doc / 005 A7 B7 Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Inc. V. Invention Description (V ·) shape will cause reliability problems; one of the problems is that when the insulation between two layers changes When it is thin, there is a danger of a short circuit in the s region between the first metal gadolinium and the second metal layer, and when the metal layer becomes thin, there is a danger that the circuit will be disconnected in the 0 region. A known method to solve the above problem is called double Embedded (Dual Damascence) process. The simplest form of this process is performed on an insulating layer. This insulating layer is formed on the substrate and flattened. The insulating layer is defined as a horizontal trench and a vertical hole. Simultaneously formed by etching the insulating layer. On the substrate, 'if the first insulating layer is passed, the metal wire and the hole will be connected down to the component area; if it passes through the upper insulating layer, It is to connect another metal layer. Next, deposit metal on the substrate with the above structure to fill the trenches and holes to form metal wires and interlayer connection holes at the same time. Finally, the chemical mechanical honing method is used. Polish (CMP) makes the surface flat and prepares for another double-embedded structure to completely embed the wires into horizontal trenches and vertical holes, which is the duality of the process. Please also refer to Section Figure 2a and Figure 2b, Figure 2a shows the double embedded structure before chemical mechanical honing; Figure 2b shows the double embedded structure after chemical mechanical honing. Two lithographic steps and two layers The insulation layers are separated by an etch stop layer. The structure is described as follows: a flat surface substrate 30 is provided, wherein a first metal layer 31 having a defined pattern is provided, and the first insulation layer 32 is deposited and covered on the first metal layer. 31, after the first insulating layer 31 is planarized, the etch stop layer 33 is covered: a contact is defined on the etch stop layer 33 by using the first lithography etching step. Mouth 'where 6 applies China National Paper-scale quasi-rub (CNS) A4 size (210X297 mm)', fitted - / IV (Please note ^ K back of the item and then fill in the page)
、1T y. 2183twf.doc/005 A7, 1T y. 2183twf.doc / 005 A7
發明説明（f) 經濟部中央梯率局貝工消费合作社印掣 將形成垂直栓塞的層間連線，其中第一絕緣層32的厚度與 栓塞的高度相同。再形成第二絕緣層34於蝕刻阻擋層33 上’此時第一絕緣層32還未被触刻’第二絕緣層34的厚 度與定義後的第二金屬層厚度相同；第二絕緣層34在第二 道微影蝕刻步驟中被蝕刻’定義出導線通道4〇於触刻阻擋 層33之上，其中一些通道40會對準前面步驟於蝕刻阻擋 層33上定義的接觸窗口 41。通道40與接觸窗口 41重疊的 區域，在進行第二道微影蝕刻步驟時，會曝露出接觸窗口， 而繼續蝕刻第一絕緣層32’進而曝露出下方的第—金屬餍 31。接著，在第一絕緣層與第二絕緣層中蝕刻形成的水平 的通道與垂直的孔洞上覆蓋塡滿金屬35 ;最後，利用蝕刻 的方式或化學機械硏磨法去除第二絕緣層34上方多餘的金 屬35，但不要去掉通道40或窗口 41內的金屬，形成如第 2b圖所示之結構。 爲了解決塡充金屬導線孔洞產生的問題，以及伴隨發生 的過度覆蓋容忍力的結果’雙重嵌入式的製程技術將會越 來越受重視。同時，架線工程（Wiring)將會在容忍力的範 圍內遵守最少的基本規則，而且因孔洞周圍薄的金屬或絕 緣層產生的問題也會被避開。但是，很明顯的這種製程是 複雜的，特別是需要用到兩道微影蝕刻製程以形成垂直孔 洞的區域；以此方法，首先需在蝕刻阻擋層形成後進行微 影定義出孔洞，且於後面的蝕刻製程做出孔洞。此外，蝕 刻阻擋層逋常爲氮化矽層；對氮化矽層進行蝕刻的設備必 須額外的增加，這些複雜步驟的加入會導致產率降低，增 請 先 閲 请 意 事 項 再 ί裝 頁 訂 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X297公釐） 2183twf.doc/005 A7 _____B7 五、發明説明（〔） 加元件的密度，以及增加成本。 儘管如此’在習知技藝中雙重嵌入式的製程仍因其優點 而大量的被運用，比如Shoda在美國專利案號5,529,953 中揭露的，一種利用選擇性沈積製造金屬栓（Sud)(垂直 金屬桂塞）及（水平）層間連線的雙重嵌入式結構的方法， 其中選擇性的沈積係透過重複的運用光罩與微影步驟完 成。同樣的，Zheng在美國專利案號5,602 053中揭露的， 一種雙重嵌入式抗鎔化的結構在兩層之間形成。另一種方 式，基於對雙重嵌入式製程中重複運用光罩定義的認可， Avanzino在美國專利案號5,614,765中說明，利用光罩圖 案以同時形成導線與介層洞。 因此，能夠以新的方法取代習知雙重嵌入式製程中複雜 的部份’且能夠有效的運用在製造半導體基底及晶片上， 將會是一個很大的優勢；本發明提供一種在現有的雙重嵌 入式製程中’移除必須使用到兩道光阻步驟的方法，大大 的改善製程β本方法係在雙重嵌入式製程中結合一道修正 過的光阻矽化（Silyation)步驟；也就是說只有一道光阻矽 化的光阻層被用在下面的實施例中，雖然Kim在美國專利 案號5,427,649中揭露了一個方法，有關於利用光阻矽化 反應形成定義圖案’但其方法仍需要用到多層光阻。 因此本發明的主要目的就是，提供一種雙重嵌入式定義 的方法，利用表面成像步驟製造半導體基底與晶片。 本發明的另一主要目的就是，提供一種雙重嵌入式定義 的方法，在雙重嵌入式定義製程中加入光阻矽化的步驟。 零 __ 8 本财關轉率（CNS)从胁（2_1()><297公瘦1 — 2183twf.doc/005 A7 B7 五、發明説明（7 ) 本發明的再另一主要目的就是，提供一種雙重嵌入式定 義的方法，改善在層間連線接觸窗口圖案下方之導線的對 準性。 本發明的再另一主要目的就是，提供一種雙重嵌入式定 義的方法，減少對準容忍力及製程偏差，藉以增加極大積 體電路晶片的積集度。 根據本發明的上述及其他目的，提出一種雙重嵌入式定 義的方法，此方法之簡述如下：提供一基底，其上已形成 有一層綜合絕緣層，該絕緣層包括頂端絕緣層、中間絕緣 層與底面絕緣層，其中頂端絕緣層與底面絕緣層被中間絕 緣層分隔開；形成一層光阻層在綜合絕緣層上方，在光阻 層上進行孔洞圖案的定義，之後將光阻層曝光再進行烘烤 (Bake);在具孔洞圖案的光阻層上再定義出導線圖案，將 光阻層先預烤過，之後再進行光阻矽化反應，以形成具有 孔洞圖案的光阻矽化罩幕；將光阻矽化罩幕上的孔洞圖案 藉蝕刻轉換到綜合絕緣層的頂端絕緣層及中間絕緣層內； 利用蝕刻在光阻層內形成導線圖案，再將導線圖案轉換到 頂端絕緣層，形成導線溝渠，同時將孔洞圖案轉換到底面 絕緣層形成接觸窗口，之後移除光阻層再沈積金屬於導線 溝渠及接觸窗口內，以形成雙重嵌入式的結構，及使綜合 絕緣層的表面變的平坦。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 9 本紙張尺度適用中ΐ固家橾準（CNS ) A4規格（210 X 297公策) _ 2183twf. doc/005 A7 經濟部中央標準局貝工消費合作社印聚 B7 五、發明説明（δ ) 圖式之簡單說明： 第1圖繪示習知的一種不平坦的多層金屬結構之半導 釋i底剖面圓； 第2a圖至第2b圖繪示俗習知的一種雙重嵌入式結_ 平坦化前與平坦化後的半導體基底結構剖面圖； 第3a圖繪示係依照本發明一較佳實施例，在綜合絕緣 .w 層上形成光阻層的半導體基底結構剖面圖； 第3b圖繪示係依照本發明一較佳實施例，在第3a圖所 示的||構上定義孔洞圖案的半導體基底結構剖面圖； 第3c圖繪示係依照本發明一較隹實施例，在光阻層中 形成孔洞圓案的半導體基底結構剖面圖； 第3d圖繪示係依照本發明一較佳實施例，在光阻層上 形成導線圖案的半導體基底結構剖面圖； 第圓繪示係依照本發明一較佳實施例，在進行光阻 矽化反應前先行預烤的半導體基底結構剖面圖； 第3f圖繪示係依照本發明一較佳實施例，在光阻層上 進行光阻矽化反應的半、導體基底結構剖面圖； v第3g圖繪示係依<照本發明一較佳實施例，將光阻層中 的孔洞圖案轉換到頂端絕緣層及中間絕緣屋的半導體基底 結構剖面圖; 第3h圖繪示係依照本發明一較佳實施例，在光阻層中 形成導線圖寨韵半導體基底結構剖面圖； 第3i圖繪示係依照本發明一較佳實施例，將導線圖寒 '— …. 轉換到頂端絕緣層中的半導體基底結構剖面圖； ---------'裝— C (請先閲免背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 25>7公釐） 2183twf. doc/005 A7 B7 經濟部中央標準局男工消費合作社印聚 五、發明说明（f) 第3j圖繪示係依照本發明一較佳實施例，將光阻層移 除後形成雙重嵌入式圖案询半導體基底結構剖面圖；以及 第.3k圖繪示係依照本發明一較佳實施例，在溝渠及窗 口中塡入金屬以形成雙重嵌入式結構的半導體基底結構剖 面圖。 實施例 請同時參照第3a圖至第3k圖，其繪示依照本發明一較 佳實施例，利用單一光阻層結合一道光阻矽化反應的步 驟，形成雙重嵌入式圖案的流程之結構剖面圖。 請參照第3a圖，在基底50上有由三層絕緣材料組成的 綜合絕緣層，包括底面絕緣層60、中間絕緣層70與頂端絕 緣層80,底面絕緣層60與頂端絕緣層80被中間絕緣層70 分隔開；接著在綜合絕緣層上形成光阻層90。其中底面絕 緣層60與頂端絕緣層80的形成方式，比如以電漿化學氣 相沈積法（PECVD)在低壓的環境下形成的磷矽玻璃 (Phosphos i 1 icate Glass，PSG)，沈積室的壓力約爲 〇. 5〜1〇 托爾，溫度範圍約爲300〜600°C，而反應氣體矽甲烷的流速 範圍約爲100~500標準立方公分每分鐘（seem)，其中加入 稀釋劑的傳導氣體磷化氫PH3，流速範圍約爲20〜20〇SCCIn ; 而底面絕緣層60與頂端絕緣層80的厚度範圍約爲〇.3~0.7 jum ° 中間絕緣層70比如氮化矽，做爲一蝕刻阻擋層，藉以 防止在蝕刻步驟蝕刻綜合絕緣層下方，形成介層涧栓塞或 接觸隔離時，中間絕緣層上方的導線圖案被繼續蝕刻。（在 ---------省裝— I /1 《請先閲諱背面之注意事項再填寫本頁)Description of the Invention (f) The printout of the Shell Consumer Cooperative of the Central Ramp Bureau of the Ministry of Economic Affairs will form an interlayer connection of vertical plugs, where the thickness of the first insulating layer 32 is the same as the height of the plug. Then form a second insulating layer 34 on the etch stop layer 33 'At this time, the first insulating layer 32 has not yet been etched' The thickness of the second insulating layer 34 is the same as the thickness of the second metal layer after the definition; the second insulating layer 34 The second photolithographic etching step is etched to define the wire channels 40 above the etch stop layer 33, and some of the channels 40 will be aligned with the contact window 41 defined on the etch stop layer 33 in the previous step. In the area where the channel 40 and the contact window 41 overlap, when the second lithography etching step is performed, the contact window is exposed, and the first insulating layer 32 'is continuously etched to expose the first metal hafnium 31 below. Next, the horizontal channels and the vertical holes formed by etching in the first insulating layer and the second insulating layer are covered with a full metal 35; finally, the excess on the second insulating layer 34 is removed by etching or chemical mechanical honing. Metal 35, but do not remove the metal in the channel 40 or the window 41 to form the structure shown in Figure 2b. In order to solve the problems caused by the holes in the metal-filled wires and the result of the over-tolerance caused by the over-embedding, the dual-embedded process technology will pay more and more attention. At the same time, Wiring will adhere to the minimum basic rules within tolerance, and problems caused by thin metal or insulating layers around the holes will be avoided. However, it is obvious that this process is complicated, especially the area that requires two lithographic etching processes to form vertical holes; in this method, the lithography is required to define the holes after the etch stop layer is formed, and Holes are made in the subsequent etching process. In addition, the etching barrier layer is usually a silicon nitride layer; the equipment for etching the silicon nitride layer must be additionally added. The addition of these complex steps will lead to a reduction in productivity. Please read the notice before you add the page binding This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 2183twf.doc / 005 A7 _____B7 V. Description of the invention ([) Adding component density and increasing cost. Nevertheless, the dual-embedded process is still widely used for its advantages, such as disclosed by Shoda in US Patent No. 5,529,953. (Plug) and (horizontal) layer-to-layer interconnect method, in which selective deposition is performed by repeated use of photomask and lithography steps. Similarly, as disclosed in US Patent No. 5,602,053 by Zheng, a double embedded anti-crusting structure is formed between two layers. Another approach, based on the recognition of repetitive mask definitions in dual embedded processes, Avanzino, in US Patent No. 5,614,765, describes the use of a mask pattern to form both wires and vias. Therefore, it can be a great advantage to replace the complex part of the conventional dual embedded process with a new method and to effectively use it in manufacturing semiconductor substrates and wafers. The present invention provides a In the embedded process, the method of removing two photoresist steps must be used, which greatly improves the process β. This method combines a modified photoresist silification step in a dual embedded process; that is, there is only one light The silicified photoresist layer is used in the following examples. Although Kim disclosed a method in U.S. Patent No. 5,427,649 regarding the use of photoresist silicidation to form a defined pattern, the method still requires a multilayer photoresist. . Therefore, the main object of the present invention is to provide a method of dual embedded definition, which uses a surface imaging step to manufacture semiconductor substrates and wafers. Another main object of the present invention is to provide a method of dual embedded definition, and add a photoresist silicification step in the dual embedded definition process. Zero __ 8 Turnover rate (CNS) of this financial institution (2_1 () > < 297 public thin 1-2183twf.doc / 005 A7 B7 V. Description of the invention (7) Another main purpose of the present invention is Provide a method of dual embedded definition to improve the alignment of the wires under the contact window pattern of the interlayer connection. Yet another main object of the present invention is to provide a method of dual embedded definition to reduce alignment tolerance. According to the above and other objectives of the present invention, a method of dual embedded definition is proposed. The method is briefly described as follows: a substrate is provided on which a substrate is formed. A layer of integrated insulating layer, which includes a top insulating layer, an intermediate insulating layer and a bottom insulating layer, wherein the top insulating layer and the bottom insulating layer are separated by the intermediate insulating layer; a photoresist layer is formed above the integrated insulating layer, and Define the hole pattern on the resist layer, then expose the photoresist layer and then bake; define the wire pattern on the photoresist layer with the hole pattern, and pre-bake the photoresist layer Then, a photoresist silicidation reaction is performed to form a photoresist silicidation mask with a hole pattern; the hole patterns on the photoresist silicidation mask are converted to the top insulation layer and the middle insulation layer of the integrated insulation layer by etching; A wire pattern is formed in the photoresist layer, and the wire pattern is converted to the top insulation layer to form a wire trench. At the same time, the hole pattern is converted to the bottom insulation layer to form a contact window. After that, the photoresist layer is removed and then metal is deposited on the wire trench and the contact window. In order to form a double embedded structure and flatten the surface of the integrated insulation layer. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below and cooperated with The attached drawings are described in detail as follows: 9 This paper size is applicable to the China Standard for Household Standards (CNS) A4 (210 X 297) _ 2183twf. Doc / 005 A7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Poly B7 5. Brief description of the invention (δ) diagram: Figure 1 shows the semi-conducting i-shaped bottom circle of a conventional uneven multi-layer metal structure; Section 2a Figure 2b shows a conventional double-embedded junction _ cross-sectional view of a semiconductor substrate structure before and after planarization; Figure 3a shows a comprehensive insulation according to a preferred embodiment of the present invention.w A cross-sectional view of a semiconductor base structure forming a photoresist layer on the layer; FIG. 3b is a cross-sectional view of a semiconductor base structure defining a hole pattern on the || structure shown in FIG. 3a according to a preferred embodiment of the present invention; Figure 3c is a cross-sectional view of a semiconductor substrate structure in which a hole pattern is formed in a photoresist layer according to a comparative embodiment of the present invention. Figure 3d is a photoresist layer according to a preferred embodiment of the present invention. A cross-sectional view of a semiconductor substrate structure forming a wire pattern; a first circle drawing is a cross-sectional view of a semiconductor substrate structure pre-baked before a photoresist silicidation reaction is performed according to a preferred embodiment of the present invention; A preferred embodiment is a cross-sectional view of a semi-conductive substrate structure for performing a photoresist silicidation reaction on a photoresist layer; FIG. 3g is a diagram showing the photoresist layer in accordance with a preferred embodiment of the present invention. Hole pattern to top Sectional view of the semiconductor substrate structure of the end insulation layer and the intermediate insulation house; FIG. 3h is a cross-sectional view of a semiconductor substrate structure formed by forming a conductive line in a photoresist layer according to a preferred embodiment of the present invention; In accordance with a preferred embodiment of the present invention, a cross-sectional view of a semiconductor substrate structure that converts a conductor pattern to a top insulation layer; --------- '装 — C (please read the free back first Note: Please fill in this page again.) The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 25 > 7 mm) 2183twf. Doc / 005 A7 B7 Male Workers Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Description of the invention (f) FIG. 3j is a cross-sectional view of a semiconductor substrate structure formed by removing a photoresist layer to form a dual embedded pattern after removing the photoresist layer according to a preferred embodiment of the present invention; and FIG. 3k is a diagram according to the present invention In a preferred embodiment, a cross-sectional view of a semiconductor substrate structure in which metal is inserted into the trench and the window to form a dual embedded structure. Please refer to FIG. 3a to FIG. 3k at the same time for the embodiment, which shows a structural cross-sectional view of a process of forming a dual embedded pattern by using a single photoresist layer combined with a photoresist silicidation step according to a preferred embodiment of the present invention . Please refer to FIG. 3a. On the substrate 50, there is a comprehensive insulating layer composed of three insulating materials, including a bottom insulating layer 60, an intermediate insulating layer 70, and a top insulating layer 80. The bottom insulating layer 60 and the top insulating layer 80 are insulated by the middle. The layers 70 are separated; a photoresist layer 90 is then formed on the integrated insulating layer. The formation method of the bottom insulating layer 60 and the top insulating layer 80, for example, Phosphos i 1 icate Glass (PSG) formed by plasma chemical vapor deposition (PECVD) under a low pressure environment, and the pressure of the deposition chamber About 0.5 ~ 10 Torr, the temperature range is about 300 ~ 600 ° C, and the flow rate range of the reaction gas silane is about 100 ~ 500 standard cubic centimeters per minute (seem), in which the conductive gas with the diluent is added Phosphine PH3, the flow rate range is about 20 ~ 20 SCCIn; and the thickness of the bottom insulation layer 60 and the top insulation layer 80 is about 0.3 ~ 0.7 jum ° The middle insulation layer 70 such as silicon nitride is used as an etch The barrier layer prevents the wiring pattern above the intermediate insulating layer from being etched further when the interlayer 涧 plug or contact isolation is formed under the integrated insulating layer by the etching step. (In --------- Provincial Installation — I / 1 "Please read the precautions on the back before filling this page)
、1T 本紙張尺度適用中國國家標準（CNS > A4規格（21〇X29*7公釐） 2183twf.doc/005 A7 B7 經濟部中央梂隼局貝工消費合作社印^ 五、發明説明（/<?) 第3a圖中’基底50內包括元件的下層結構，其上可能已 設有金屬層，這些並非本發明的特徵’故不詳細敘述。）其 他的材料也可能用來當作阻擋層，使用氮化矽是因爲氮化 矽可以成爲綜合絕緣層的一部份，且氮化矽較用來做爲絕 緣材料的矽化物有不同的蝕刻特性，可被用來做爲抗反射 層。因此氮化矽對應於下方材料的不同，可以提供選擇性 的蝕刻製程’且可以降低入射光線的反射；當以聚亞醯胺 (Polyimide)做爲材料時’旋塗式玻璃（Spin 〇n Glass, SOG) 及化學氣相沈積的氮化物也適合做爲蝕刻阻擋層；一般來 說大多使用氮化矽’形成方式比如電漿化學氣相沈積法， 厚度範圍約爲500〜2000A’實際厚度要取決於氧氣對氮氣 的選擇性。 在第3a圖中所不的頂端絕緣層go在形成後會被磨 平’進行方式比如化學機械硏磨法，回蝕法或利用覆蓋的 方式使使頂端絕緣層80變的平坦；然後形成光阻層9〇於 以磷砂玻璃爲材料的頂端絕緣層80上，光阻層的材料比如 化學倍增光阻劑（Chemical Amplificatic)n Resist，CAR)， 且爲一正型光阻；CAR含有感光酸性反應物（ph〇t〇 Acid .Generator, PAG) ’被用來取代傳統的感光試劑，比如在日 本的T0K使用正型或負型光阻時，分別使用τ〇Κ〇〇7及 TOKN908。 第3a圖中所繪示的光阻層其厚度範圍約爲0.5~0.9私 m。請參照第3b圖，暗底光罩（Dark Field Mask)l00被用 來曝露出光阻層90，以形成垂直的孔洞圖案91。在這裡必 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） --------}裝-- /V- (讀先閲^背面之注意事項再填寫本頁)、 1T This paper size applies to Chinese national standards (CNS > A4 size (21 × 29 * 7mm) 2183twf.doc / 005 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs ^ V. Description of the invention (/ <?) In Fig. 3a, "the substrate 50 includes a lower layer structure of the element, and a metal layer may be provided thereon, these are not the features of the present invention," so it is not described in detail.) Other materials may also be used as the barrier layer. The use of silicon nitride is because silicon nitride can be part of a comprehensive insulation layer, and silicon nitride has different etching characteristics than silicides used as insulation materials, and can be used as an anti-reflection layer. Therefore, silicon nitride corresponds to the difference of the underlying materials, can provide a selective etching process and can reduce the reflection of incident light; when using polyimide as the material, spin-on glass (Spin ON Glass) , SOG) and chemical vapor deposited nitrides are also suitable as etch barriers; generally, silicon nitride is used for formation methods such as plasma chemical vapor deposition, and the thickness range is about 500 ~ 2000A. Depends on the selectivity of oxygen to nitrogen. The top insulating layer go, which is not shown in Fig. 3a, will be flattened after formation, such as a chemical mechanical honing method, an etch-back method, or a cover method to flatten the top insulating layer 80; then, light is formed. The resist layer 90 is on the top insulating layer 80 made of phosphate sand glass. The material of the photoresist layer is, for example, Chemical Amplificatic n Resist (CAR), and it is a positive type photoresist. Acid reactants (ph〇t〇Acid.Generator, PAG) 'is used to replace traditional photosensitizers. For example, when TOK in Japan uses positive or negative photoresist, τ〇Κ〇07 and TOKN908 are used. The thickness of the photoresist layer shown in Figure 3a is about 0.5 to 0.9 μm. Referring to FIG. 3b, a dark field mask 100 is used to expose the photoresist layer 90 to form a vertical hole pattern 91. Here the paper size must be in accordance with Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) --------} installed-/ V- (read the precautions on the back ^ before filling this page )
、1T 2183twf.doc/005 A7 B7 經濟部中央標隼局員工消費合作社印製 五、發明説明（// ) 須注意到，在光罩已定義的區域91之外的部份或場區 (Field)90是不透明的，如第3b圖所示，用以做爲一”暗底” 光幕，使被定義的圖案可以與光線作用；而另一方面”明底” 光罩（Clear Field Mask)則在稍後的步驟中被使用，使光 線照射在光罩覆蓋的區域，而不會照射到定義的圖案，運 作的方式與暗底光罩相反。因此，曝光的光線105照射在 孔洞圖案91上，使PAG產生酸進而轉換成樹脂，曝光量約 爲20〜200毫焦耳/平方公分。 接下來，請參照第3c圖，在曝光後進行一道烘烤的步 驟，溫度約在80~100°C，這是因爲化學倍增光阻劑必須繼 續保持足夠的敏感度，藉以在第二道曝光步驟中，使光阻 層得以在孔洞圖案上形成導線圖案。習知曝光定義出導線 圖案的方法，無論如何必須先以傳統的濕式顯影（Wet Development)步驟形成孔洞91’，以靜置顯影（Stream Puddle)技術（使用濃度2.8%的顯影劑TMAH)，如S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era，” vol, 1，Lat t i ce Press，Sunset Beach, California, 1986，p.443中所提到的說明。 請參照第3d圖，根據本發明的主要特徵，以同一層光 阻層90透過一亮底光罩進行第二次曝光，藉以使導線圖案 92成像在孔洞91’周圍。光線107透過亮底光罩101使光 阻層90的部份區域曝光，使光阻層內的PAG產生酸轉換成 樹脂，曝光量約爲20〜200毫焦耳/平方公分。 接著，請參照第3e圖，未曝光的導線圖案92在進行光 (請先閲讀背面之注意事項再填寫本頁) *-*·1T 2183twf.doc / 005 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (//) It should be noted that the part or field outside the area 91 defined by the photomask (Field ) 90 is opaque. As shown in Figure 3b, it is used as a "dark background" light curtain, so that the defined pattern can interact with light. On the other hand, a "clear field mask" It is used in a later step, so that the light shines on the area covered by the mask without illuminating the defined pattern, and works in the opposite way to the dark-bottom mask. Therefore, the exposure light 105 is irradiated on the hole pattern 91, so that the PAG generates an acid and is converted into a resin. The exposure amount is about 20 to 200 mJ / cm2. Next, please refer to Figure 3c. After the exposure, a baking step is performed. The temperature is about 80 ~ 100 ° C. This is because the chemical multiplier photoresist must continue to maintain sufficient sensitivity for the second exposure. In the step, the photoresist layer can form a wire pattern on the hole pattern. Conventional exposure defines the method of the wire pattern. In any case, the holes 91 'must be formed by the traditional Wet Development step, and the Stream Puddle technology (using the developer TMAH at a concentration of 2.8%), As described in S. Wolf and RN Tauber, "Silicon Processing for the VLSI Era," vol, 1, Lat Technology Press, Sunset Beach, California, 1986, p. 443. Referring to FIG. 3d, according to the main feature of the present invention, the same photoresist layer 90 is used for a second exposure through a bright bottom mask, so that the wire pattern 92 is imaged around the hole 91 '. The light 107 passes through the bright bottom mask 101 to expose a part of the photoresist layer 90, so that the PAG in the photoresist layer generates an acid and converts it into a resin, and the exposure amount is about 20 to 200 millijoules / cm2. Next, please refer to Figure 3e, the unexposed lead pattern 92 is being illuminated (please read the precautions on the back before filling this page) *-* ·
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 2183twf,doc/005 A7 B7 五、發明説明（/>) 阻矽化反應前的烘烤步驟中會形成交連（Cross-link)，烘 烤溫度約爲130~180°C。 之後’請參照第3f圖，接著在光阻層90曝露出來的區 域進行光阻矽化反應’光阻矽化的步驟在溫度範圍約爲 140~210°C時，將一種甲矽烷基試劑擴散進曝光的區域，藉 著將矽導入光阻層的有機化合物中，形成含矽量高的光阻 砂化層94’如第3f圖所不之結構，厚度約爲1〇〇〇〜4〇〇〇 A， 而光阻層90較深層的部份93則不受影饗；用來進行光阻 矽化反應的較佳試劑比如：四甲基二矽氮烷（tetra-methyl di-silazane，TMDS)，其中包括矽，另外六甲基二矽氮院 (hexamethyl disilazane, HMDS)、砍甲院也可被使用。 接著，請參照第3g圖，將光阻層90中的孔洞圖案91， 轉換到頂端絕緣層80中，在高密度電漿氧化物蝕刻器中， 利用一種乾蝕刻氧化物製程包括流速50〜150sccm的氬氣， 10~50sccm的三氟甲烷，0〜22sccm的丁烯；接著以一種氮 化矽蝕刻製程包括：流速約爲〇~l〇〇SCCm的三氟甲烷、流 速約爲0〜50的四氟甲烷、流速約爲50~150sccm的氬氣蝕 刻中間絕緣層70。 之後，請參照第3h圖，在形成交連的部份92進行非等 向性蝕刻，以在光阻層90內形成導線圖案92’，並移去前 一個蝕刻步驟殘留在孔洞內的光阻，使用的光阻蝕刻製程 包括氧氣、氦氣、二氧化矽及四氟甲烷，其個別的流速約 爲 10〜250、40~80、10~80、0~50sccm。 接著，請參照第31圖，以光阻矽化層94做爲罩幕’以 本纸張尺度逋用中國國家揉準（CNS ) Λ4規格（210X297公釐） I--------〇 裝------訂-----'.線 * i W (請先閎讀背面之注$項再填寫本頁)· . 經濟部中央樣率局貝工消费合作社印氧 2183twf.doc/005 A7 B7_ 五、發明説明（”） ^ 對氮化矽有高選擇性的蝕刻製程，以氮化矽做爲一阻擒 層’將導線圖案由光阻層轉換到頂端絕緣層80，反應係在 高密度電漿氧化物蝕刻器中進行，加入一蝕刻製程包栝： 氬氣、三氟甲烷、丁烯，流速分別約爲5〇~15〇、1〇〜15〇、 0〜20sccm ;當導線圖案蝕刻到氮化矽層7〇終止時，孔洞阖 案則蝕刻到基底50 » 之後，請參照第3j圖，移除光阻層，以單一光阻層形 成的雙重嵌入式結構包括有導線溝渠92,及垂直的接觸窗 口 91 ’光阻層係先以氧氣電駿進行灰化處理（Ashing)，再 以硫酸、過氧化氫、氫氧化氨的溶液進行濕式剝餘（Wet Strip)。 接著’請參照第3k圖，將金屬沈積在綜合絕緣層中水 平的導線溝渠與垂直的接觸窗口內，再將多餘的金屬去除 使表面平坦，即完成雙重嵌入式結構。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 • · 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ---------(ά------訂-----1( j線 * % 》· (請先聞讀背面之注f項再填寫本頁. 經 濟 部 中 央 標 準 貝 工 費 合 作 社 印 裝 本纸張尺度適用中困國家標準（CNS ) A4规格（210X297公釐）This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 2183twf, doc / 005 A7 B7 5. Description of the invention (/ >) Cross-linking will be formed during the baking step before the silicidation reaction (Cross-link) , The baking temperature is about 130 ~ 180 ° C. Afterwards, please refer to FIG. 3f, and then perform a photoresist silicidation reaction on the exposed area of the photoresist layer 90. The photoresist silicidation step diffuses a silyl reagent into the exposure at a temperature range of about 140 to 210 ° C. In the region of the photoresist layer, silicon is introduced into the organic compound of the photoresist layer to form a photoresist sanding layer 94 ′ having a high silicon content, as shown in FIG. 3f, and has a thickness of about 1,000 to 4,000. A, while the deeper part 93 of the photoresist layer 90 is not affected; a better reagent for photoresist silicidation reaction is tetra-methyl di-silazane (TMDS), This includes silicon, as well as hexamethyl disilazane (HMDS) and armour-cutting homes. Next, referring to FIG. 3g, the hole pattern 91 in the photoresist layer 90 is transferred to the top insulating layer 80. In a high-density plasma oxide etcher, a dry etching oxide process is used to include a flow rate of 50 to 150 sccm. Argon, 10-50 sccm trifluoromethane, 0-22 sccm butene; then a silicon nitride etching process includes: trifluoromethane with a flow rate of about 0 to 100 SCCm, and a flow rate of about 0 to 50 The intermediate insulating layer 70 is etched by tetrafluoromethane and argon at a flow rate of about 50 to 150 sccm. After that, referring to FIG. 3h, anisotropic etching is performed on the cross-linked portion 92 to form a wire pattern 92 'in the photoresist layer 90, and the photoresist remaining in the hole in the previous etching step is removed. The photoresist etching process used includes oxygen, helium, silicon dioxide, and tetrafluoromethane, and the individual flow rates are about 10 ~ 250, 40 ~ 80, 10 ~ 80, 0 ~ 50sccm. Next, please refer to Figure 31, using the photoresist silicide layer 94 as a mask 'using the Chinese paper standard (CNS) Λ4 specification (210X297 mm) at this paper size I -------- 〇 Install ------ order ----- '. Line * i W (please read the note $ on the back before filling out this page).. Central Sample Rate Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperative, India 2183twf. doc / 005 A7 B7_ V. Description of the invention (") ^ Highly selective etching process for silicon nitride, using silicon nitride as a barrier layer 'to convert the wire pattern from the photoresist layer to the top insulating layer 80, The reaction is performed in a high-density plasma oxide etcher, and an etching process is added: argon, trifluoromethane, butene, and the flow rates are about 50 ~ 150, 10 ~ 15, and 0 ~ 20sccm, respectively. ; When the wire pattern is etched to the silicon nitride layer 70, the hole pattern is etched to the substrate 50 »After that, please refer to Figure 3j to remove the photoresist layer. The double embedded structure formed with a single photoresist layer includes: There is a wire channel 92 and a vertical contact window 91. The photoresist layer is firstly ashed with oxygen gas, and then sulfuric acid, hydrogen peroxide, and hydroxide Ammonia solution is wet stripped (Wet Strip). Then 'Please refer to Figure 3k, deposit metal in the horizontal wire trench and vertical contact window in the integrated insulation layer, and then remove the excess metal to make the surface flat, That is, the dual embedded structure is completed. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention to 'any person skilled in the art without departing from the spirit and scope of the present invention'. Various modifications and retouchings are made, so the protection scope of the present invention shall be determined by the scope of the appended patent application. --------- (ά ------ 订 ----- 1 (j line *%》 · (Please read the note f on the back before filling out this page. The central standard of the Ministry of Economic Affairs and Cooperatives Cooperatives printed on this paper applies the National Standards (CNS) A4 specifications (210X297 mm) )