574745 A7 _ B7 五、發明説明（） lijgj頁域 (請先閲讀背面之注意事項再填寫本頁) 本發明是有關於一種半導體積體電路製程，且特別是 有關於一種應用多孔低介電常數材料（porous low-k dielectric)之金屬雙鑲嵌（dual damascene)製程。 登-塑背景 隨著半導體製程往縮小體積與提高集積度的方向發 展，半導體元件的尺寸亦跟著縮小，使得金屬線之間的寄 生電容（Parasitic Capacitor)也越來越大。結果電阻-電容時 間延遲（Resistance Capacitance Time Delay ; RC delay)、訊 號間的相互干擾以及能量損耗等問題益顯突出。為了解決 電阻-電容時間延遲的問題，在電阻方面可以使用低電阻的 金屬導線，而在降低寄生電容方面則是讓多重金屬内連線 之間的介電層使用低介電常數的介電材料。 在降低金屬導線電阻方面，若以銅導線來取代鋁導 線，可以使電阻-電容時間延遲減少約35%。在降低介電層 的介電常數方面，若能使用空氣（介電常數為1·〇)做為介 電層的材料，則可以將電阻-電容時間延遲減少約乃％ ’所 以多孔低介電常數材料的運用就成為近年來的趨勢。 經濟部智慧財產局員工消費合作社印製 第1A - 1D圖係繪示習知應用低介電常數材料之金屬 雙鑲嵌的製造流程剖面示意圖。請參照第1A圖，在基底（圖 上未示出）上依序形成金屬線路層100，氮化矽層110、多 孔介電層120、氮氧化矽層130與光阻層（圖上未示出）。接 著進行微影蝕刻製程，依序蝕刻氮氧化矽層130與多孔介 2 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 574745 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 電層120，停在阻障層110之上，形成介層窗（via) 140,然 後去除光阻層。 在第1B圖中，再塗佈一層光阻15〇於基底上，介層窗 140中亦會填入光阻15〇。然後進行微影製程，在光阻15〇 中形成開口 160。在第ic圖中，以光阻15〇為蝕刻罩幕， 依序蝕刻氮氧化矽層130與部分之多孔介電層12〇，形成溝 渠二70,再去除光阻15〇。在第1D圖中，蝕刻被介層窗14〇 暴露出之氮化矽層110,形成氮化矽層u〇a，讓金屬層1〇〇 的表面暴露出來。然後形成氮化鈕阻障層（圖上未示出）覆蓋 在溝渠170與介層窗丨4〇的表面，再填入銅金屬於介層窗 140與溝渠170中，形成金屬雙鑲嵌結構（圖上未示出）。 由上述可知，溝渠170底部表面在去除暴露出之氮化 夕層110時，還會被钱刻電聚侵姓一次。因為多孔介電層 120本身之多孔結構問題，會使溝渠170底部表面180十分 粗縫如溝渠170之局部放大圖所示。而且在溝渠170邊 緣之處，還會因為蝕刻電漿撞擊頻率較高，而產生微溝渠 (rmcro trench) 190。這些種種問題都會影響到後續之金屬化 (metallization)製程，使所沈積出之氮化钽阻障層品質不 佳，而可能導致銅金屬在經過熱製程之後會擴散至多孔介 電層120之中，造成短路的問題。或是使得氮化钽阻障層 與多孔介電層12〇之間會產生空洞，因而降低線路 賴度（reliability)。 ° 驾头的解决方法之一為在多孔介電層120的中間多开^ 成一層蝕刻終止層，例如氮化矽層。但是此舉會造成金屬 3 本紙張尺度適财國g家標準(CNs)A4規格⑽乂撕公 ''- (請先閲讀背面之注意事項再填寫本頁) 參 •訂.........線， ......................... 574745574745 A7 _ B7 V. Description of the invention () Lijgj page domain (please read the notes on the back before filling this page) The present invention relates to a semiconductor integrated circuit manufacturing process, and in particular to an application of a porous low dielectric constant Material (porous low-k dielectric) metal dual damascene process. Boarding-Plastic Background As the semiconductor process progresses in the direction of reducing the volume and increasing the degree of integration, the size of semiconductor components has also been reduced, making the parasitic capacitance between metal lines larger and larger. As a result, the problems of Resistance Capacitance Time Delay (RC delay), mutual interference between signals, and energy loss are prominent. In order to solve the problem of resistance-capacitance time delay, a low-resistance metal wire can be used in terms of resistance, and a low-constant dielectric material can be used in the dielectric layer between multiple metal interconnects to reduce parasitic capacitance. . In terms of reducing the resistance of metal wires, replacing copper wires with aluminum wires can reduce the resistance-capacitance time delay by about 35%. In terms of reducing the dielectric constant of the dielectric layer, if air (with a dielectric constant of 1 · 0) can be used as the material of the dielectric layer, the resistance-capacitance time delay can be reduced by about 10%. The use of constant materials has become a trend in recent years. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figures 1A-1D are schematic cross-sectional diagrams showing the manufacturing process of metal dual inlays that are conventionally applied with low dielectric constant materials. Referring to FIG. 1A, a metal circuit layer 100, a silicon nitride layer 110, a porous dielectric layer 120, a silicon oxynitride layer 130, and a photoresist layer (not shown in the figure) are sequentially formed on a substrate (not shown). Out). Next, the lithography etching process is performed, and the silicon oxynitride layer 130 and the porous substrate 2 are sequentially etched. This paper size applies the Chinese National Standard (CNS) A4 specification (210x297 mm) 574745 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Explanation of the invention () The electrical layer 120 stops on the barrier layer 110 to form a via 140, and then removes the photoresist layer. In FIG. 1B, a layer of photoresist 150 is coated on the substrate, and the photoresist 150 is also filled in the interlayer window 140. Then, a lithography process is performed to form an opening 160 in the photoresist 15. In FIG. Ic, the photoresist 150 is used as an etching mask, and the silicon oxynitride layer 130 and a part of the porous dielectric layer 120 are sequentially etched to form a trench 70, and the photoresist 15 is removed. In FIG. 1D, the silicon nitride layer 110 exposed by the via window 14 is etched to form a silicon nitride layer u0a, so that the surface of the metal layer 100 is exposed. Then, a nitride button barrier layer (not shown in the figure) is formed to cover the surfaces of the trench 170 and the interlayer window 4 40, and then copper metal is filled in the interlayer window 140 and the trench 170 to form a metal dual damascene structure ( (Not shown). From the above, it can be known that when the exposed bottom nitride layer 110 is removed from the bottom surface of the trench 170, it will be invaded by money and electricity. Because of the porous structure of the porous dielectric layer 120 itself, the bottom surface 180 of the trench 170 is very thick, as shown in a partially enlarged view of the trench 170. In addition, at the edge of the trench 170, a rmcro trench 190 is generated due to the high frequency of the etching plasma impact. These various problems will affect the subsequent metallization process, making the deposited tantalum nitride barrier layer of poor quality, and may cause copper metal to diffuse into the porous dielectric layer 120 after the thermal process. , Cause the problem of short circuit. Or, a void may be generated between the tantalum nitride barrier layer and the porous dielectric layer 120, thereby reducing the circuit reliability. ° One of the solutions is to form an additional stop layer in the middle of the porous dielectric layer 120, such as a silicon nitride layer. However, this will cause the metal 3 paper size to meet the national standards (CNs) A4 specifications of the wealthy country ''-(Please read the precautions on the back before filling this page) See the order ... ... line, ......... 574745
五、發明説明( (請先閲讀背面之注意事項再場寫本頁) 二]"電層的整體介電常數提升，增加積體電路的電阻_電 容時間延遲。此外，因為氮切^ 11G之關電漿的反應 氣體配方’通常為 CF4、CHF3、CH2F2、CH3l^N2、〇2、 等氣體搭配之。若調整氮切層110之㈣電浆的反應 =體配方，使#刻過程產生較多的含氟聚合物來保護多孔 =電層120的表面，則金屬線路層謂的表面亦會沈積有 含氟聚合物’造成後續填人金屬時之困擾。若要以灰化 (ashing)的方法來清除此含氟聚合物，又會使金屬線路層 1〇〇的表面與含氟中間產物發生反應，造成電阻上升的問 題0 登j月目的輿概沭 因此本發明的目的就是在提供一種應用多孔低介電常 數材料之金屬雙鑲嵌製程，使在多孔低介電常數材料中形 成之雙鑲嵌開口的溝渠底部不會有粗糙的表面。 本發明的另一目的是在提供一種應用多孔低介電常數 材料之金屬雙鑲嵌製程，使在多孔低介電常數材料中形成 之雙鑲嵌開口的溝渠底部，不會再受到其他蝕刻電漿的侵 餘。 經濟部智慧財產局員工消費合作社印製 根據本發明之上述目的，提出一種應用多孔低介電常 數材料之金屬雙鑲嵌製程。先在基底上依序形成阻障層、 具有低介電常數之多孔介電層與抗反射層，此基底上已形 成有金屬線路層。然後形成圖案化之第一光阻層於抗反射 層上，再以第一光阻層為蝕刻罩幕，依序蝕刻暴露出之抗 4 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) 574745 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（ 反射層、多孔介電層與阻障層，以形成介層窗暴露出金屬 線路層。接著去除第一光阻層，再通入碳氫化合物，用化 學氣相沈積法沈積碳氫聚合物於介層窗之底部，以保護暴 路出之金屬線路層。形成圖案化之第二光阻層於抗反射層 上與介層窗中，暴露出介層窗周圍之抗反射層。然後以第 二光阻層為蝕刻罩幕，依序蝕刻暴露出之抗反射層與多孔 介電層至一定的深度，以使溝渠與介層窗形成雙鑲嵌開 口 接者去除第一光阻層與碳氫聚合物，再填入金屬於雙 鑲嵌開口中。 、 、 依照本發明一較佳實施例，其中上述之阻障層之材質 可為氮化矽或碳化矽，抗反射層之材質可為氮氧化矽，而 碳氫化合物可為乙烯或乙炔。 由上述可知，本發明先蝕刻阻障層暴露出金屬線路 層，然後形成碳氫聚合物覆蓋在金屬線路層之上，保護金 屬線路層的表面。最後才蝕刻抗反射層與多孔介電層形成 雙镶嵌開口的溝渠，如此多孔介電層之溝渠底部表面才不 會因為受到兩次的蝕刻作用而變得表面粗糙，甚至形成微 溝渠’影響後續金屬化製程。 圖式之簡 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易is，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1A 1D圖係緣示習知應用低介電常數材料之金屬 %‘ 訂 ----線#_ (請先閲讀背面之注意事項再場寫本頁)V. Description of the invention ((Please read the precautions on the back before writing this page) 2.] The overall dielectric constant of the electrical layer is increased, increasing the resistance_capacitance time delay of the integrated circuit. In addition, because of nitrogen cut ^ 11G The reaction gas formula of the plasma is usually combined with CF4, CHF3, CH2F2, CH3l ^ N2, 02, and other gases. If the reaction of the plasma is adjusted with the nitrogen cutting layer 110, the plasma formula is used to make the # 刻 process produce More fluoropolymers are used to protect the surface of the porous = electric layer 120, and the fluoropolymers will also be deposited on the surface of the metal circuit layer, which will cause troubles in the subsequent filling of metal. If you want to use ashing Method to remove this fluorinated polymer, and will cause the surface of the metal circuit layer 100 to react with the fluorinated intermediate product, causing the problem of increased resistance. Therefore, the purpose of the present invention is to provide A metal dual damascene process using a porous low dielectric constant material, so that the bottom of the trench with double damascene openings formed in the porous low dielectric constant material does not have a rough surface. Another object of the present invention is to provide a porous application low The metal dual-inlaying process of the dielectric constant material prevents the bottom of the trench with the double-inlaying opening formed in the porous low dielectric constant material from being invaded by other etching plasma. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the above object of the present invention, a metal dual damascene process using a porous low dielectric constant material is proposed. A barrier layer, a porous dielectric layer with a low dielectric constant, and an anti-reflection layer are sequentially formed on a substrate. A metal circuit layer has been formed thereon, and then a patterned first photoresist layer is formed on the anti-reflection layer, and then the first photoresist layer is used as an etching mask to sequentially etch the exposed resistance. 4 This paper size is applicable to China Standard (CNS) A4 specification (210X297 Gongchu) 574745 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (Reflective layer, porous dielectric layer and barrier layer to form a dielectric window to expose metal lines Then, the first photoresist layer is removed, and then a hydrocarbon is passed in, and a hydrocarbon polymer is deposited on the bottom of the interlayer window by a chemical vapor deposition method to protect the metal from the storm. Road layer. A patterned second photoresist layer is formed on the anti-reflection layer and the via window to expose the anti-reflection layer around the via window. Then the second photoresist layer is used as an etching mask to sequentially etch and expose The anti-reflection layer and the porous dielectric layer are formed to a certain depth, so that the trench and the interlayer window form a dual mosaic opening. The first photoresist layer and the hydrocarbon polymer are removed, and then the metal is filled in the dual mosaic opening. According to a preferred embodiment of the present invention, the material of the above barrier layer may be silicon nitride or silicon carbide, the material of the anti-reflection layer may be silicon oxynitride, and the hydrocarbon may be ethylene or acetylene. It can be known from the foregoing that, in the present invention, the barrier layer is etched to expose the metal circuit layer, and then a hydrocarbon polymer is formed to cover the metal circuit layer to protect the surface of the metal circuit layer. Finally, the anti-reflection layer and the porous dielectric layer are etched to form trenches with double damascene openings. In this way, the bottom surface of the trenches of the porous dielectric layer will not be roughened due to two etchings, and even micro trenches will be formed. Metallization process. In order to make the above and other objects, features, and advantages of the present invention more obvious, the following is a detailed description of a preferred embodiment and the accompanying drawings, as follows: 1A 1D Familiar with the metal% 'of applying low dielectric constant materials. Order ---- line #_ (Please read the precautions on the back before writing this page)
574745 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 雙鑲嵌的製造流程剖面示意圖。 第2 A - 2D圖係繪示依照本發明一較佳實施例的一種 應用低介電常數材料之金屬雙鑲嵌的製造流程剖面示意 圖。 圖式之標記說明 100、200 :金屬線路層 110、110a :氮化矽層 120、220 :多孔介電層 130 :氮氧化矽層 140、240 :介層窗 150、260 :光阻 160 、 270 :開口 170、280 :溝渠 180 :底部表面 190 :微溝渠 210、210a :阻障層 230 :抗反射層 250 :碳氫聚合物 發明之詳細說明 如上所述，本發明提供一種應用多孔低介電常數材料 之金屬雙鑲嵌製程，使在多孔低介電常數材料中形成之雙 鑲嵌開口的溝渠底部’不會再受到其他钱刻電漿的侵餘。 — — — — — — — — — — — — —'I ί — — — — — — — — — — — — — — — — I (請先閲讀背面之注意事項再填寫本頁)574745 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () A cross-sectional schematic diagram of the manufacturing process of double mosaic. Figures 2A-2D are schematic cross-sectional views showing a manufacturing process of a metal dual damascene using a low dielectric constant material according to a preferred embodiment of the present invention. 100, 200: metal circuit layer 110, 110a: silicon nitride layer 120, 220: porous dielectric layer 130: silicon oxynitride layer 140, 240: dielectric window 150, 260: photoresistor 160, 270 : Openings 170, 280: trench 180: bottom surface 190: micro trench 210, 210a: barrier layer 230: antireflection layer 250: detailed description of the hydrocarbon polymer invention As described above, the present invention provides an application of porous low dielectric The process of metal dual damascene of constant material prevents the bottom of the trench with double damascene openings formed in the porous low dielectric constant material from being invaded by other money-carved plasmas. — — — — — — — — — — — — — 'I ί — — — — — — — — — — — — — — — I (Please read the notes on the back before filling out this page)
574745 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 如此溝渠底部的表面就不會粗糙，以免造成後續金屬化製 程之線路短路與降低可信賴度的問題。 請參照第2A - 2D圖，其繪示依照本發明一較佳實施 例的一種應用低介電常數材料之金屬雙鑲嵌的製造流程剖 面示意圖。請參照第2A圖，在基底（圖上未示出）上依序形 成金屬線路層200，阻障層210、多孔介電層220、抗反射 層230與光阻層（圖上未示出）。接著進行微影製程以圖案化 光阻層，再以圖案化之光阻層為蝕刻罩幕來依序蝕刻抗反 射層230與多孔介電層220，停在阻障層210之上，形成介 層窗（via) 140，然後去除光阻層。 其中上述之阻障層210的材質例如可為氮化矽或碳化 矽，其形成方法例如可為化學氣相沈積法。多孔介電層220 的材質可為各種有機或無機之多孔低介電常數材料，例如 含氫的石夕酸鹽類（hydrogen silsesquioxane ; HSQ)、含甲基的 石夕酸鹽類（methyl sequioxane ; MSQ)、JSR公司的LKD商品 或多孔之SiLK等等。抗反射層230的材質為無機抗反射材 料，例如氮氧化矽，其形成方法例如可為化學氣相沈積法。 因為目前深次微米的半導體製程中，多重金屬内連線 所用的金屬多為銅金屬，所以需要在金屬線路層200之上 方先形成阻障層210，防止銅金屬擴散至多孔介電層220 中而造成漏電甚至短路的問題。同時，在蝕刻多孔介電層 220時，阻障層210也可以保護金屬線路層200，使其表面 不會和蝕刻電漿進行反應，造成電阻升高的問題。 請參照第2B圖，以抗反射層230為蝕刻罩幕，蝕刻介 7 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） » — — — — — — — — — — — — —-1 ί — — — — — — — — — — — — — — — — I — (請先閲讀背面之注意事項再填寫本頁) 574745 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 層窗240所暴露出之阻障層210，形成抗反射層230a與阻 障層210a。因為是以抗反射層230作為蝕刻罩幕來蝕刻阻 障層210，所以在蝕刻完成之後，抗反射層230a的厚度會 比原先之抗反射層230的厚度要小。 請參照第2C圖，以碳氫化合物為反應氣體源，利用電 漿增強式化學氣相沈積法在暴露出之金屬線路層200之表 面沈積碳氫聚合物250，以保護金屬線路層200。其中上述 之碳氫化合物例如可為乙烯或乙炔等等氣體。接著，在基 底上塗佈光阻260，介層窗240中亦會填入光阻260。然後 進行微影製程，在光阻層260中形成開口 270。 請參照第2D圖，以光阻層260為蝕刻罩幕，蝕刻暴露 出之抗反射層23〇a與其下之多孔介電層220,形成溝渠 280。因此，介層窗240與溝渠280組成雙鑲嵌開口。接著， 去除光阻260與碳氫化合物250，暴露出金屬線路層200 的表面，再去除抗反射層230a。在此，因為碳敷聚合物250 不含氟或其他鹵素，所以在以電漿去除碳氫聚合物250時， 不會產生含氟或鹵素的中間產物而與金屬線路層200的表 面進行反應，因而提升金屬線路層的電阻值。 接著，在多孔介電層220與金屬線路層200的表面形 成一層共形（conformal)的黏著阻障層（圖上未示出），再填入 金屬於介層窗240與溝渠270中，完成金屬雙鑲嵌結構（圖 上未示出）。後續之製程，為熟知此技藝之人所熟知，因此 不再贅述。 由上述本發明較佳實施例可知，先蝕刻阻障層暴露出 8 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） — — — — — — — — — — — II ΙΪ ill — — — — — — — — — — — — — — I — (請先閲讀背面之注意事項再填寫本頁) 574745 A7 B7 五、發明説明（） 金屬線路層’然後形成不含氟或其他鹵素的碳氫聚合物覆 蓋在金屬層之上，來保護金屬層的表面。最後才姓刻抗反 射層與多孔介電層形成雙鑲极開口中的溝渠，如此多孔介 f層之溝渠底部表面才不會因為受到兩次的蝕刻作用而變 得表面粗糙，甚至形成微溝渠，影響後續金屬化製程。 、雖然本發明已以一較佳實施例揭露如上，然其並非用 以限疋本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明 護範圍當視後附之申請專利範圍所界定者為準。 /、 ......................、一叮....... (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製574745 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The surface of the bottom of the trench will not be rough, so as to avoid the problems of short circuit of the metallization process and reduced reliability. Please refer to FIGS. 2A to 2D, which are schematic cross-sectional views illustrating a manufacturing process of a metal dual damascene using a low dielectric constant material according to a preferred embodiment of the present invention. Referring to FIG. 2A, a metal circuit layer 200, a barrier layer 210, a porous dielectric layer 220, an anti-reflection layer 230, and a photoresist layer (not shown in the figure) are sequentially formed on a substrate (not shown in the figure). . Next, a lithography process is performed to pattern the photoresist layer, and then the patterned photoresist layer is used as an etching mask to sequentially etch the anti-reflection layer 230 and the porous dielectric layer 220, and stop on the barrier layer 210 to form a dielectric. Layer window (via) 140, and then remove the photoresist layer. The material of the above-mentioned barrier layer 210 may be, for example, silicon nitride or silicon carbide, and a method of forming the barrier layer 210 may be, for example, a chemical vapor deposition method. The material of the porous dielectric layer 220 may be various organic or inorganic porous low dielectric constant materials, such as hydrogen silsesquioxane (HSQ) and methyl sequioxane; MSQ), JSR's LKD products or porous SiLK, etc. The material of the anti-reflection layer 230 is an inorganic anti-reflection material, such as silicon oxynitride, and the formation method thereof may be, for example, a chemical vapor deposition method. Because in the current deep sub-micron semiconductor manufacturing process, most of the metal used for multi-metal interconnects is copper metal, it is necessary to form a barrier layer 210 above the metal circuit layer 200 to prevent copper metal from diffusing into the porous dielectric layer 220. And cause the problem of leakage or even short circuit. At the same time, when the porous dielectric layer 220 is etched, the barrier layer 210 can also protect the metal circuit layer 200 so that its surface does not react with the etching plasma, causing a problem of increased resistance. Please refer to Figure 2B, with the anti-reflection layer 230 as the etching mask, and the etching medium 7 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) »— — — — — — — — — — — — — -1 ί — — — — — — — — — — — — — — — — I — (Please read the notes on the back before filling out this page) 574745 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Note that the barrier layer 210 exposed by the layer window 240 forms an anti-reflection layer 230a and a barrier layer 210a. Since the anti-reflection layer 230 is used as an etching mask to etch the barrier layer 210, after the etching is completed, the thickness of the anti-reflection layer 230a will be smaller than that of the original anti-reflection layer 230. Referring to FIG. 2C, a hydrocarbon polymer 250 is deposited on the surface of the exposed metal circuit layer 200 using a plasma enhanced chemical vapor deposition method using a hydrocarbon as a reactive gas source to protect the metal circuit layer 200. The above-mentioned hydrocarbons may be, for example, gases such as ethylene or acetylene. Then, a photoresist 260 is coated on the substrate, and the photoresist 260 is also filled in the via 240. Then, a lithography process is performed to form an opening 270 in the photoresist layer 260. Referring to FIG. 2D, with the photoresist layer 260 as an etching mask, the exposed anti-reflection layer 23a and the porous dielectric layer 220 under it are etched to form a trench 280. Therefore, the via window 240 and the trench 280 constitute a dual-mosaic opening. Next, the photoresist 260 and the hydrocarbon 250 are removed, the surface of the metal circuit layer 200 is exposed, and then the anti-reflection layer 230a is removed. Here, because the carbon coating polymer 250 does not contain fluorine or other halogens, when the hydrocarbon polymer 250 is removed by plasma, no intermediate products containing fluorine or halogen are generated and react with the surface of the metal circuit layer 200. Therefore, the resistance value of the metal wiring layer is increased. Next, a conformal adhesive barrier layer (not shown in the figure) is formed on the surface of the porous dielectric layer 220 and the metal circuit layer 200, and then metal is filled in the dielectric window 240 and the trench 270 to complete the process. Metal dual damascene structure (not shown). The subsequent process is well known to those who are familiar with this technique, so it will not be repeated here. According to the above-mentioned preferred embodiments of the present invention, the etching of the barrier layer first exposes 8 paper sizes that are applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) — — — — — — — — — — — II ΙΪ ill — — — — — — — — — — — — — — — I — (Please read the precautions on the back before filling out this page) 574745 A7 B7 V. Description of the invention () Metal circuit layer 'Then form a fluorine-free or other halogen-free Hydrocarbon polymer covers the metal layer to protect the surface of the metal layer. Finally, the anti-reflection layer and the porous dielectric layer were engraved to form a trench in the double-electrode opening, so that the bottom surface of the trench of the porous dielectric layer would not be roughened due to two etchings, or even a micro trench , Affecting subsequent metallization processes. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. / 、 ............ 、 Yingding ............ (Please read the notes on the back before filling this page} Ministry of Economy Wisdom Printed by the Property Agency Staff Consumer Cooperative