40523^ 3 I 84TWF.DOC/006 A7 __；______B7_ 五、發明説明（/ ) 本發明是有關於一種金屬內連線（metal intercon-nects)的製造方法，且特別是有關於一種可應用於銅硏磨 (Cu-CMP)之銅導線，其可適用於雙重嵌金製程（dual dam-ascene process ) ° 目前在超大型積體電路（VLSI)製程中，許多高積集度 (high integration)的半導體元件，都具有兩層以上的內 連線金屬層，稱爲多重金屬內連線（multilevel interconnects)，其目的是用以適應元件密度的增加而形 成的立體配線結構（wiring line structures)^第一層的 金屬配線可爲多晶矽層或是金屬層，透過介層窗（via)以 電性連接基底中元件的源極/汲極區。而更多在元件之間 彼此的連線則可經由第二層或以上的金屬配線來完成。若 是積集度不斷增加，會使得金屬線中的電容效應會變大， 而導致介層窗中相對的RC遲延（RC delay)和交互聯繫 (cross talk)的情形增加。如此一來，金屬線之間的導電 速度會變慢。 目前正在開發一種新的金屬內連線材料，例如銅，其 具有電阻低的優點，再配合，可以提供品質更好的金屬內 連線結構。雙重嵌金法的特徵在於可同時蝕刻形成金屬配 線與介層窗結構，請參照第1A圖到第1D圖’首先，在半 導體基底10上沈積一絕緣層12，例如二氧化砂。然後’ 如第1B圖所示，進行微影與非等向性蝕刻製程，在絕緣 層12中蝕刻出一溝渠14a，其位置對應於後續欲形成金屬 配線的地方，且溝渠14a的深度並未貫穿絕緣層。接著’ 3 本紙張尺度i€用中固國家標準（CNS ) A4規格（210X297公釐） (諳先閲讀背面之注意事項再填寫本頁) 訂 線 好方·部中央"卑而只-τ消资合作社印絮 40S^^.b〇C/006 A7 _B7_ 五、發明説明（1 ) 如第1C圖昧示，進行微影與非等向性蝕刻製程，繼續在 溝渠14a中進行微影與蝕刻步驟，在絕緣層12中蝕刻出 —介層窗開口 14b(contact opening)，露出其下的半導體 基底10。之後，再於介層窗開口 14b與溝渠14a中沈積阻 障層16(barrier layer)，其材料例如爲金屬鉬（Ta)、氮 化鉬（TaN)或是其他難熔金屬（refractory metal) ’可用 以增加金屬配線層18a與絕緣層12的黏著力以及避免後 續金屬層之擴散。然後，如第1D圖所示，於介層窗開口 14b與溝渠14a中沈積金屬層，例如金屬銅，用以塡滿介 層窗開口與溝渠。然後，進行化學機械硏磨法（Chemical Mechanical Polishing ; CMP)，將超出溝渠 14a 表面的多 餘金屬去除，於是形成金屬配線層18a與介層窗18b，而 此金屬配線層18a可以透過介層窗18b以電性連接下方之 金屬配線層（未顯示）。 此種習知雙重嵌金結構的缺點在於，在金屬配線層 18a的表面，因爲經過銅硏磨的步驟，當硏磨到阻障層16 時，因爲其材料與金屬銅的硏磨率不同，例如金屬銅對氮 化鉅（TaN)的選擇性（selectivity)在8-16之間，或是甚 至差別更大，例如銅對金屬钽（Ta)的選擇性在12-20之 間。所以，當進行硏磨時，容易在金屬配線層18a的表面 產生中央凹陷的情況（dishing)，而形成不平坦的凹陷表 面19，如第1D圖所示。此凹陷表面19會造成後續沈積品 質不良的情形。嚴重時，甚至會產生氧化層侵飩（erosion) 的現象，使得金屬銅之阻値升高。此外，由於部分阻障層 16的表面硏磨不乾淨，易造成阻障層16殘留的現象，所 4 本紙乐尺度適用家梯準（CNS ΰ4現格（210X297公釐） ~ -------------^裝-----Μ—訂-------—線 - - - (請先閱讀背面之注f項再填寫本頁) 好济部中央榀準而只工消於合作私印" 40523£ A7 3 1 84TWF.DOC/006 A/ B7 _ 五、發明说明（>) 的表面硏磨不乾淨，易造成阻障層16殘留的現象，所以 容易產生不必要的短路與橋接（bridge)現象》 習知並無有效克服上述問題的方法，大抵上只是利用 多重硏磨的步驟（multiple polish step)，利用不同的硏 漿（slurry)和不同的硏磨墊（polish pad)來減低高選擇比 的問題。如此一來，製程中需要增加重作（rework)的次 數，提高製程的花費。 有鑑於此，本發明的主要目的就是在提供一種銅導線 製程，可以應用於雙重嵌金製程中，避免於硏磨金屬銅 時，因銅對其下之阻障層的硏磨選擇比不同，而造成嚴重 的凹陷與氧化層侵蝕的現象，影響銅的阻値及平坦度。 本發明的另一目的是在提供一種銅導線製程，可以避 免殘留金屬產生的短路與橋接現象，且不需要增加重作的 次數，可以節省製程的步驟與花費。 爲達成上述之目的，本發明提出一種銅導線製程，可 應用於雙重嵌金製程中，其步驟包括：首先提供一半導體 基底，在半導體基底上形成一絕緣層，其材料例如爲二氧 化矽。然後，在絕緣層中依序形成一溝渠與一介層窗開 口，介層窗開口位於溝渠下方，且介層窗開口底部露出半 導體基底。溝渠的形成方式包括微影與非等向性蝕刻步 驟，以時間長短或終止點（end point)的形式來控制蝕刻 的深度。介層窗開口的形成方式包括微影與非等向性蝕刻 步驟。接著，在溝渠與介層窗開口中依序形成一第一阻障 層與一第二阻障層，第二阻障層位於第一阻障層上。其 中’第一阻障層的材料例如爲鉬（Ta)，第二阻障層的材料 5 本紙張尺度ϋ月rt固國家揉率（CNS )八4胁（210X297公釐） " ----------_^裝-ί— I--；---^訂---·---- r 線 - > . (請先閲讀背面之注^•項再填寫本頁) _ 好"部中央坏準而妇^消费合作赵印衆 3 1表9為發暴^)〇6 A7 __________B7_ 五、‘發明説明（f ) 一阻障層的材料例如爲鉬（Ta)，第二阻障層的材料例如爲 氮化iS(TaN)。然後，進行微影與蝕刻製程，去除在溝渠 周緣的第一阻障層與第二阻障層，暴露出絕緣層，留下在 溝渠與介層窗開口中的第一阻障層與第二阻障層。接著， 在第二阻障層與絕緣層上形成一金屬銅層，用以塡滿溝渠 與介層窗開口。再進行硏磨步驟，例如化學機械硏磨法 (CMP)，去除在絕緣層上多餘的金屬銅層，於是在溝渠中 形成一金屬配線層，以及在介層窗開口中形成一介層窗。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖到第1D圖，其所繪示的爲習知一種雙重嵌金 製程步驟的剖面示意圖；以及 第2A圖到第2F圖，其所繪示的是根據本發明之一較 佳實施例，一種銅導線製程步驟的剖面示意圖。 其中，各圖示之標號所代表的元件結構如下： 10,20 :半導體基底 12，22 :絕緣層 14a :金屬溝渠 14b :介層窗開口 16,28,28a，30,30a :阻障層 18a，34a :金屬配線層 18b :介層窗 6 ---Κ--：---'ί 菸 l·----L---訂------<線 (请先閲讀背面之注意事項再填寫本頁) 本&張尺度通用中國國家栋準（CNS } A4規格（210X297公~ 好淤部十戎榀準而只J..消贽合作社印聚 /006 A7 _____ B7 五、發明説明（f) 19 :凹陷表面 24 :介層窗開口 26 :金屬溝渠 32 :光阻層 34 :金屬層 實施例 本發明提出一種銅導線製程，可以應用於雙重嵌金製 程中銅硏磨（Cu-CMP)的步驟，避免於硏磨金屬銅時，因銅 對其下之阻障層的硏磨選擇比不同，而造成嚴重的凹陷與 氧化層侵蝕的現象，影響銅的阻値及平坦度。此外，本發 明可以避免殘留阻障層金屬（barrier layer)易產生的短 路與橋接（bridge)現象，且不需要增加製程中重作（rework) 的次數 ，所以可以節省製程的步驟與花費。 請參照第2A圖到第2G圖，其所繪示的是根據本發明 之一較佳實施例，一種銅導線製程步驟剖面示意圖。首 先，請參照第2A圖，提供一半導體基底20，在其上已形 成有第一金屬配線層或是電晶體結構（未顯示）。然後，在 半導體基底20上形成絕緣層22，其材料例如爲二氧化矽 層（Si〇2)、硼磷矽玻璃（BPSG)或是磷矽玻璃（PSG)等矽化 物，且其形成方式例如爲化學氣相沈積法（CVD)，沈積一 層厚度例如在約7000埃到約10000埃之間的二氧化矽 層。絕緣層22的表面通常會經過平坦化（planarization) 的處理。平坦化步驟例如可以利用回蝕刻步驟（etch back)，或是利用化學機械硏磨法（CMP”接著，在絕緣層 22中依序形成溝渠26(trench)與介層窗開口 24(via 7 本紙張尺度通用肀囷國家標準（CNS ) A4規格（2丨0X297公釐） ------------裝----„----訂------- 1 線 * - -(誚先閱讀背面之注意事項再填寫本頁) . 40523ί 3184TWF.DOC/006 Α7 _ Β7 五、發明説明（G) 形成溝渠26(trench)與介層窗開口 24(via opening)。其 中，溝渠26的寬度通常比介層窗開口 24的寬度大。溝渠 26的形成方式例如爲微影（photο 1 i thography)與非等向 性倉虫刻（anisotropic etching)步驟，以進行的時間長短 或終止點（end point)的形式來控制蝕刻的深度。其位置 對應於後續欲形成金屬配線的地方，且溝渠26的深度並 未貫穿絕緣層22。溝渠26的深度可以配合金屬配線所需 的厚度，而作適當的調整。而介層窗開口 24的形成方式 爲繼續在溝渠26中，進行例如微影與非等向性蝕刻步驟， 在溝渠26下蝕刻出介層窗開口 24，露出半導體基底20。 接著，請參照第2B圖，在絕緣層22上，溝渠26與介 層窗開口 24中，覆蓋一層薄的第一阻障層28。第一阻障 層28的形成方式例如爲化學氣相沈積法（CVD)，沈積例如 金屬鉅（Ta)、金屬鈦（Ti)或是其他難熔金屬材料，其厚度 約在數百A左右，例如在約300A到約500A之間。然後， 在第一阻障層28上形成第二阻障層30。第二阻障層30的 形成方式例如爲化學氣相沈積法（CVD)，沈積例如氮化鉅 (TaN)、氮化鈦（TiN)或是其他難熔金屬材料，其厚度約在 數百A左右，例如在約300A到約500A之間。第一阻障 層28與第二阻障層30互相搭配，例如Ta/TaN，其功能可 以接觸窗的阻値，增加絕緣層22與後續金屬銅之間的黏 著力，以及阻擋後續金屬銅的擴散。 接著，請參照第2C圖，進行微影步驟，在第二阻障 層30上形成光阻層32，並定義光阻層32的圖案，暴露出 8 ---^---^------------κ--* 訂-----^ 1線 ' - {請先閲讀背面之注$項再填寫本頁) 本紙張尺度边用中國國家標準（〇沏）八4规格（210><297公釐） 經Μ部中央if-1-A^.t.消汝合竹ii印裝 40523£ 3U4TWF.DOC/006 A7 ------------Β7 五、發明説明（7 ) ~~~-— " 在溝渠26周緣的第二阻障層30。然後，以光阻層32爲罩 幕（mask)進行蝕刻步驟，較佳的是非等向性餓刻製程， 蝕刻去除在溝渠26周緣的第一阻障層28與第二阻障層 ,30，暴路出絕緣層22。此微影與蝕刻製程爲本發明的特 徵，其可用以去除在絕緣層22上多餘的第一阻障層28與 第一阻障層30，使得後續在硏磨金屬銅時，不會因金屬銅 與第二阻障® 3〇的硏磨率（polish rate)不同，或是金屬 銅對第一阻障餍30的硏磨選擇比差異太大，而造成硏磨 不均勻的情況。因此可以避免金屬銅表面產生凹陷的現 象，以及減少氧化層22侵蝕的現象。 接著’請參照第2D圖’去除光阻層32，去除方式例 如爲含氧電漿處理。留下在溝渠26與介層窗開口 24中的 第一阻障層28a與第二阻障層30a。 接著’請參照第2E圖，在第二阻障層30a與絕緣層 22上形成金屬層34，較佳的是金屬銅，用以塡滿溝渠26 與介層窗開口 24。金屬層34的形成方式可以爲化學氣相 沈積法（CVD)或是物理氣相沈積法（pvD)，例如濺鍍法 (sputtering)。或是亦可以爲電化學沈積法（Electr〇_40523 ^ 3 I 84TWF.DOC / 006 A7 __; ______B7_ V. Description of the Invention (/) The present invention relates to a method for manufacturing metal intercon-nects, and in particular to a method that can be applied to copper Cu-CMP copper wires are suitable for dual dam-ascene process ° At present, in the VLSI process, many high integration (high integration) Semiconductor devices have more than two metal interconnect layers, called multilevel interconnects. The purpose is to provide three-dimensional wiring line structures (wiring line structures) to accommodate the increase in device density. A layer of metal wiring may be a polycrystalline silicon layer or a metal layer, and the source / drain regions of the components in the substrate are electrically connected through a via. And more connections between the components can be completed through the second layer or more metal wiring. If the accumulation degree is continuously increased, the capacitance effect in the metal line will become larger, and the relative RC delay and cross talk in the via window will increase. As a result, the conduction speed between the metal wires becomes slower. Currently, a new metal interconnect material, such as copper, is being developed, which has the advantage of low resistance. When combined, it can provide a better quality metal interconnect structure. The double gold insert method is characterized in that metal wiring and via window structures can be formed by etching at the same time. Please refer to FIG. 1A to FIG. 1D ′. Then, as shown in FIG. 1B, a lithography and anisotropic etching process is performed, and a trench 14a is etched in the insulating layer 12 at a position corresponding to the subsequent place where metal wiring is to be formed, and the depth of the trench 14a is not Through insulation. Then '3 paper sizes i use the China National Standard (CNS) A4 size (210X297 mm) (谙 Please read the precautions on the back before filling in this page). Consumers cooperative printing 40S ^^. B〇C / 006 A7 _B7_ V. Description of the invention (1) As shown in Figure 1C, the lithography and anisotropic etching processes are performed, and the lithography and the lithography in the trench 14a are continued. In the etching step, an interlayer window opening 14b (contact opening) is etched in the insulating layer 12 to expose the semiconductor substrate 10 thereunder. After that, a barrier layer 16 is deposited in the via window opening 14b and the trench 14a. The barrier layer 16 is made of, for example, metal molybdenum (Ta), molybdenum nitride (TaN), or other refractory metal. It can be used to increase the adhesion between the metal wiring layer 18a and the insulating layer 12 and to prevent the subsequent metal layer from diffusing. Then, as shown in FIG. 1D, a metal layer, such as metallic copper, is deposited in the via window opening 14b and the trench 14a to fill the via window opening and the trench. Then, a chemical mechanical honing method (Chemical Mechanical Polishing; CMP) is performed to remove excess metal beyond the surface of the trench 14a, so that a metal wiring layer 18a and an interlayer window 18b are formed, and the metal wiring layer 18a can pass through the interlayer window 18b. Electrically connect the underlying metal wiring layer (not shown). The disadvantage of this conventional double gold-embedded structure is that, on the surface of the metal wiring layer 18a, because the copper honing step is performed, when the barrier layer 16 is honed, the material and the copper copper have different honing rates. For example, the selectivity of metal copper to nitride (TaN) is between 8-16, or even greater. For example, the selectivity of copper to metal tantalum (Ta) is between 12-20. Therefore, when honing is performed, it is easy to cause a central depression on the surface of the metal wiring layer 18a, and an uneven depression surface 19 is formed, as shown in FIG. 1D. This recessed surface 19 may cause poor quality of subsequent deposition. In severe cases, even the phenomenon of erosion of the oxide layer may occur, making the resistance of metallic copper higher. In addition, because the surface of part of the barrier layer 16 is not honing, it is easy to cause the phenomenon that the barrier layer 16 remains, so the paper scale is applicable to the home ladder standard (CNS ΰ4 is now (210X297 mm) ~ ----- -------- ^ 装 ----- Μ—Order --------- line---(Please read the note f on the back before filling this page) However, it is only necessary to co-operate in private printing " 40523 £ A7 3 1 84TWF.DOC / 006 A / B7 _ 5. The surface honing of the description of the invention (>) is not clean, and it is easy to cause the phenomenon that the barrier layer 16 remains, so It is easy to produce unnecessary short-circuits and bridges. ”There is no effective way to overcome the above problems. It is probably just using multiple polish steps, using different slurries and different A polishing pad is used to reduce the problem of high selection ratio. In this way, the number of rework needs to be increased in the process to increase the cost of the process. In view of this, the main purpose of the present invention is to provide a copper The wire process can be used in the double gold inlay process to avoid the obstacles caused by copper when honing metal copper. The different honing selection ratios of the layers cause severe depression and oxide erosion, which affect the resistance and flatness of copper. Another object of the present invention is to provide a copper wire manufacturing process that can avoid short circuits caused by residual metals. And bridging phenomenon, and it is not necessary to increase the number of repetitions, which can save the steps and costs of the process. In order to achieve the above purpose, the present invention proposes a copper wire process that can be applied to the double gold embedding process. The steps include: first providing A semiconductor substrate is formed on the semiconductor substrate with an insulating layer made of, for example, silicon dioxide. Then, a trench and a via window opening are sequentially formed in the insulating layer, the via window opening is located below the trench, and the via window is formed. The semiconductor substrate is exposed at the bottom of the opening. The trench is formed by lithography and anisotropic etching steps to control the depth of the etch in the form of time length or end point. The formation of the interstitial window opening includes lithography and Anisotropic etching step. Next, a first barrier layer and a second barrier layer are sequentially formed in the trench and the opening of the via. Layer, the second barrier layer is located on the first barrier layer. Among them, the material of the first barrier layer is, for example, molybdenum (Ta), and the material of the second barrier layer. CNS) 8 4 threats (210X297 mm) " ----------_ ^ 装 -ί— I--; --- ^ subscribe --- · ---- r line-> (Please read the note on the back ^ • item before filling out this page) _Good " The Ministry of Justice and Consumers ^ Consumer Cooperation Zhao Yinzhong 3 1 Table 9 is an outbreak ^) 〇6 A7 __________B7_ V. 'Explanation of the invention (F) The material of one barrier layer is, for example, molybdenum (Ta), and the material of the second barrier layer is, for example, nitrided iS (TaN). Then, a lithography and etching process is performed to remove the first barrier layer and the second barrier layer on the periphery of the trench, exposing the insulating layer, and leaving the first barrier layer and the second barrier layer in the trench and the via window opening. Barrier layer. Next, a metal copper layer is formed on the second barrier layer and the insulating layer, so as to fill the trench and the via opening. A honing step is performed, such as a chemical mechanical honing method (CMP), to remove the excess metal copper layer on the insulating layer, so a metal wiring layer is formed in the trench, and a via window is formed in the via window opening. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A FIG. 1D is a schematic cross-sectional view showing the steps of a known double gold inlaying process; and FIGS. 2A to 2F are a schematic view of a copper according to a preferred embodiment of the present invention. A schematic cross-sectional view of a wire manufacturing process. Wherein, the element structures represented by the symbols shown in the figures are as follows: 10, 20: semiconductor substrates 12, 22: insulation layer 14a: metal trench 14b: via window openings 16, 28, 28a, 30, 30a: barrier layer 18a , 34a: metal wiring layer 18b: interlayer window 6 --- Κ--:-'' smoke l · ---- L --- order ------ < line (please read the back first Please fill in this page for the matters needing attention) This & Zhang Dimension GM China National Building Standard (CNS) A4 Specification (210X297 Gong ~ Haoyu Department Shi Rongzheng Standard and only J .. Consumer Cooperative Cooperative Print / 006 A7 _____ B7 5 Description of the invention (f) 19: recessed surface 24: interstitial window opening 26: metal trench 32: photoresist layer 34: metal layer Example The present invention proposes a copper wire process, which can be applied to copper honing in the double gold inlay process (Cu-CMP) step. When honing metal copper, due to the different honing selection ratio of copper to the barrier layer underneath, it causes serious depression and oxide layer erosion, which affects the copper resistance and Flatness. In addition, the present invention can avoid the short-circuit and bridge phenomena easily caused by the residual barrier layer metal, and does not need to increase the weight in the process. The number of rework steps can save process steps and costs. Please refer to FIG. 2A to FIG. 2G, which are schematic cross-sectional views of a copper wire process step according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a semiconductor substrate 20 is provided, on which a first metal wiring layer or a transistor structure (not shown) has been formed. Then, an insulating layer 22 is formed on the semiconductor substrate 20, and a material such as It is a silicide such as silicon dioxide (SiO2), borophosphosilicate glass (BPSG), or phosphosilicate glass (PSG), and the formation method is, for example, chemical vapor deposition (CVD). A silicon dioxide layer between about 7000 angstroms and about 10,000 angstroms. The surface of the insulating layer 22 is usually subjected to a planarization process. The planarization step can be, for example, an etch back step or a chemical mechanical Honing method (CMP) Next, trenches 26 (trench) and interstitial window openings 24 (via 7) are formed in the insulating layer 22 in order. Common paper standard (CNS) A4 size (2 丨 0X297 mm) --------- --- Installation ---- „---- Order ------- 1 line *--(诮 Please read the precautions on the back before filling this page). 40523ί 3184TWF.DOC / 006 Α7 _ Β7 5 2. Description of the invention (G) A trench 26 (trench) and a via opening 24 are formed. Among them, the width of the trench 26 is generally larger than the width of the via 24. The method of forming the trench 26 is, for example, a photography and anisotropic etching step, and the depth of the etching is controlled in the form of a time duration or an end point. Its position corresponds to the place where the metal wiring is to be formed later, and the depth of the trench 26 does not penetrate the insulating layer 22. The depth of the trench 26 can be appropriately adjusted in accordance with the thickness required for the metal wiring. The formation of the via window opening 24 is to continue in the trench 26 by, for example, lithography and anisotropic etching steps. The via window 24 is etched under the trench 26 to expose the semiconductor substrate 20. Next, referring to FIG. 2B, a thin first barrier layer 28 is covered on the insulating layer 22, the trench 26 and the dielectric window opening 24. The first barrier layer 28 is formed by, for example, a chemical vapor deposition (CVD) method, such as deposition of metal giant (Ta), metal titanium (Ti), or other refractory metal materials, and its thickness is about several hundred A. For example between about 300A and about 500A. Then, a second barrier layer 30 is formed on the first barrier layer 28. The second barrier layer 30 is formed by, for example, a chemical vapor deposition (CVD) method, such as deposition of giant nitride (TaN), titanium nitride (TiN), or other refractory metal materials, and its thickness is about several hundred A. Around, for example, between about 300A and about 500A. The first barrier layer 28 and the second barrier layer 30 are matched with each other, such as Ta / TaN. Its function can contact the resistance of the window, increase the adhesion between the insulating layer 22 and the subsequent metal copper, and block the subsequent metal copper. diffusion. Next, referring to FIG. 2C, a lithography step is performed, a photoresist layer 32 is formed on the second barrier layer 30, and a pattern of the photoresist layer 32 is defined, exposing 8 --- ^ --- ^ --- --------- κ-* Order ----- ^ 1 line '-{Please read the note on the back before filling in this page) This paper uses the Chinese national standard (〇Maker) 8 size 4 (210 > < 297 mm) printed by the center of the M Department if-1-A ^ .t. Xiaoru Hezhu ii printed 40523 £ 3U4TWF.DOC / 006 A7 ---------- --B7 V. Description of the invention (7) ~~~ --- " The second barrier layer 30 on the periphery of the trench 26. Then, the photoresist layer 32 is used as a mask to perform an etching step, preferably an anisotropic starving process, and the first barrier layer 28 and the second barrier layer 30 on the periphery of the trench 26 are removed by etching.暴 路 出 空气 层 22。 Insulation layer 22. This lithography and etching process is a feature of the present invention. It can be used to remove the excess first barrier layer 28 and the first barrier layer 30 on the insulating layer 22, so that when the metal copper is subsequently honed, it will not be affected by metal. The honing rate of copper is different from that of the second barrier ® 30, or the honing selection ratio of metallic copper to the first barrier 餍 30 is too large, resulting in uneven honing. Therefore, it is possible to avoid the occurrence of depressions on the surface of the copper metal and reduce the phenomenon of erosion of the oxide layer 22. Next, "please refer to Fig. 2D" to remove the photoresist layer 32, and the removal method is, for example, an oxygen-containing plasma treatment. The first barrier layer 28a and the second barrier layer 30a remain in the trench 26 and the via window opening 24. Next, referring to FIG. 2E, a metal layer 34, preferably metal copper, is formed on the second barrier layer 30a and the insulating layer 22 to fill the trench 26 and the via window 24. The metal layer 34 may be formed by a chemical vapor deposition (CVD) method or a physical vapor deposition (pvD) method, such as sputtering. Or it can also be an electrochemical deposition method (Electr〇_
Chemical DepOSition ; ECD)，値得注意的是，在進行此 電化學沈積步驟之前，需要先沈積一層種子層（PVD seed layer)。 接著’請參照第2F圖，進行硏磨步驟，例如化學機 械硏磨法（CMP) ’硏磨金屬層34直到露出絕緣層22,將超 出絕緣層22表面的多餘金屬層34去除，而形成金屬配線 9 本紙張尺度⑽ 1½国^297·^--— ---^---.------裝-----：--訂--------線 ' - - , C锖先W讀背面之注意事項再填巧本页) !Chemical DepOSition; ECD), it should be noted that before performing this electrochemical deposition step, a PVD seed layer needs to be deposited. Next, please refer to FIG. 2F, and perform a honing step, such as a chemical mechanical honing method (CMP). Wiring 9 This paper size ⑽ 1½ country ^ 297 · ^ --- --- ^ ---.------ installation -----: --- order -------- line '- -, C 锖 first read the notes on the back before filling out this page)!
405231 3184TWF.DOC DOC/006 A7 B7 五、發明説明（δ ) 層34a的結構，其可以與其下基底中的元件（未顯示）作電 性連接。於是完成本發明的雙重嵌金製程。 綜上所述，本發明所提出之雙重嵌金製程法，具有以 下的特點： (1) 本發明所提出的銅導線製程，可以應用於銅硏磨 的步驟，避免於硏磨金屬銅時，因銅對其下之阻障層的硏 磨選擇比不同，而造成嚴重的凹陷與氧化層侵蝕的現象， 影響銅的阻値及平坦度。 (2) 本發明所提出的銅導線製程，可以避免殘留阻障 層金屬產生的短路與橋接現象。 (3) 本發明所提出的銅導線製程，不需要增加重作的 次數，可以節省製程的步驟與花費。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 ---„---.--i装-----^--訂---------線 - - 》 . (請先閲讀背面之注意事項再蛾寫本頁) 經潢部中央*?_而只-1-消资合作社印^ 本紙張尺度適用肀SS家樣率（CNS ) A4規格（2丨0X297公釐）405231 3184TWF.DOC DOC / 006 A7 B7 5. Description of the invention (δ) The structure of the layer 34a can be electrically connected to the components (not shown) in the underlying substrate. Thus, the double gold embedding process of the present invention is completed. In summary, the dual gold inlay process proposed by the present invention has the following characteristics: (1) The copper wire process proposed by the present invention can be applied to the step of copper honing, to avoid honing metal copper, Due to the different honing selection ratio of copper to the barrier layer underneath, it causes serious depression and oxide layer erosion, which affects the copper resistance and flatness. (2) The copper wire manufacturing process proposed by the present invention can avoid the short circuit and bridging phenomenon caused by the residual barrier layer metal. (3) The copper wire manufacturing process proposed by the present invention does not need to increase the number of redo operations, and can save the steps and costs of the manufacturing process. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. --- „---.-- i equipment ----- ^-order --------- line--》. (Please read the precautions on the back before writing this page) The central part of the decoration department *? _ And only -1-consumer cooperatives ^ This paper size is applicable 肀 SS home sample rate (CNS) A4 specifications (2 丨 0X297 mm)