TW439190B - Fabrication of semiconductor device having shallow junctions - Google Patents

Fabrication of semiconductor device having shallow junctions Download PDF

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TW439190B
TW439190B TW088122770A TW88122770A TW439190B TW 439190 B TW439190 B TW 439190B TW 088122770 A TW088122770 A TW 088122770A TW 88122770 A TW88122770 A TW 88122770A TW 439190 B TW439190 B TW 439190B
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William Hsioh-Lien Ma
Hsing-Jen C Wann
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Ibm
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Description

4391 9〇 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1) 發明領域 本發明係有關於一用於製造半導體裝置之方法，且更特 別地係有關於-製造具有期待之分開及隔離該源極及没極 區與該閑極區之超淺.接合面之方法。本發明之方法提供具 有超淺接合面之方法β. 發明背景 在形成之半導體裝置中，期待製造較小裝置及較密積體 電路持續成爲一重要目標。生產具有小至遇到超大型積體 電路（ULSI)嚅求尺寸之微電子裝置需要降低一半導體基質 中裝置之橫向及垂直兩者之尺寸。例如，當該裝置尺寸變 得較小時，對在該半導體基質表面形成一期待之導性之裝 置尺寸存在一需求。在製造金屬氧化物半導體場效電晶體 (MOSFET)中，特別是針對邏輯裝置，除了形成淺接合面 外，一重要考量係有關自該閘極區分開及隔離該源極/汲 極區。 發明概述 所以，本發明之一目的係提供—用於製造具有期待之分 開及隔離^源極及汲極區與該閘極區之超淺接合面之方 法。 本發明提供一用於製造可達到該上述目的之半導體裝置 之處理順序。更特別地，本發明之方法包括提供一具有源 極及没極區與多晶矽閘極區之半導體基質。在該源極及汲 極區上沉積選取之矽。提供攙雜物至該源極及汲極區以形 成淺接合面。在該閘極區之邊壁上形成第一絕緣邊壁間隔 -4- <請先閲讀背面之注意事項再填寫本頁) 裝 訂— 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 43 91 90 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（2 ) 物。在該第一絕緣邊壁間隔物上形成第二絕緣間隔物。接 著梦化該源極及ί及極區之上表面β 本發明也有關於藉上述之方法所得之半導體装置。 又對那些熟知此項技藝之人士，本發明之其它目的及優 點將從下列之詳細説明中變得顯而易見，其中僅顯示及描 述本發明之較佳具體實施例，簡單地經由該細思量之最佳 模式説明來施行本發明。如所了解的，本發明可有其它不 同之具體實施例，且它的一些細述能在不同之明顯相關性 上作修改而-不偏離本發明。據此，該説明書係有關本質之 説明而非作爲限制用。 圖式之簡單説明 本發明之上述及其它目的、觀點及優點從參考圖式對本 發明之一較佳具體實施例之詳細説明中將有較佳之了解，. 其中： ^圖1 -7係根據本發明之一具體實施例中有關本發明結構於 不同處理階段之略圖。 施行本發明之最佳之不同模式 爲了幫助_對本發明之了解，將參考根據本發明對一具體 實施例圖解式表示步驟所顯示之圖形。 根據本發明，一絕緣層2被提供於一半導體基質1上。該 半導禮基質1係典型之早晶碎或一絕緣體上秒（g〇i)之基 質。該絕緣層2可在該基質上成長或可由沉積技術如化學 氣相沉積法（CVD)或物理氣相沉積法（PVD)來提供之。同 時’該絕緣層2可由襯底基質1之熱氧化來提供，用以提供 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）. (請先閱讀背面之注意事項再填寫本頁〕 裝 I----訂--------線 經濟部智慧財產局員工消費合作社印製 4391 90 A7 一 B7 五、發明說明（3 ) 一二氧化矽。典型地，本層2係約1 5至約1 〇〇埃（又）厚且作 用如一閘控絕緣體。 一傳導材料3如一攙雜之多晶矽層被提供於該絕緣層2 上。該傳導層3在該半導體基質上形成之半導體裝置中提 供閘極。典型地，該傳導層3係約1000至約3000人厚。 一第二·絕緣層4係選擇性地提供於該傳導層3上。典型 地，本層係多至約丨5〇〇又厚。本絕緣層4 一般係一氧化 物’其例如可由氧化一沉積之四乙正發酸鹽 (tetraethylorThosilicate)來形成，接著加熱至溫度約4〇〇°C至 約750°C，用以形成該氧化物或更普遍地藉由化學氣相沉 積法形成之。 ， 蚀刻一預設圖案以定義該閘控導體來移去該第二絕緣層 4及傳導層3之選取部份。尤其’該部份可運用傳統光刻技 術如提供一光阻材料（未顯示）並接著將之圖案化以提供想 要之閘極結構。該圖案化光阻則作用如一用於移去該第二 絕緣層4曝光部份之遮罩並接著處理該傳導層3。這些可藉 離子蝕刻反應來移除。期待該絕緣層4之材料異於該絕緣 層2，使得雖行之移除能選擇性地停止在該絕緣層2上。 接著’剩餘之光阻由如一合適之溶劑溶解而移除。 接著，一第三絕緣層5係由如已知之包含化學氣相沉積 法（CVD)或物理氣相沉積法（PVD)之沉積技術提供之。典型 地，層5係二氧化矽、氮化矽或氮氧化矽/本層典型地係 約1 0至3〇0人厚。參見圖2。 接著’該絕緣層5係如圖3所示地從絕緣體4之頂部及該 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） '.. - „ i H ^--1-'--丨—, > 裝·------- 訂'--------線 (請先閱讀背面之注意事項再填寫本頁) 43 91 9 0 A7 B7 五、發明說明（4 ) 絕緣層2之頂部移去而留絕緣6在該閘控導體3之邊壁上。 此外，移去除了那些位於該閘極結構3及絕緣6下面部份外 之絕緣層2。可藉選擇之離子姓刻反應施行該移除，藉此 該钱刻選擇性地停止在該襯底之矽基質上。該絕緣6厚度 控制接著形成之接合面重疊，其係它的縱擴散及橫擴散。 一選擇之矽層7係藉由如化學沉積法沉積及成長。該矽 層7是一磊晶矽層並產生於曝光之單晶矽表面上之單晶 矽。選擇之矽係僅於它曝光之矽表面上成長。該層7典型 地係約1001約500 A厚。參見圖4。 可以是攙雜或未攙雜。挽雜時，則該攙雜物透過該選擇 之梦層7導入該源極及没極區8，用以提供典型地少於 〇 200A及大於約50至.約150A之淺接合面。爲了確保形成一 超淺接合面’對該結構作一短而快速之熱回火（RTP)，其 典型之溫度約8 0 0至約12 0 0 °C，更典型之溫度約9 〇 〇至約 110 0 C持續約〇 · 〇 5至約1. 〇 〇分，而更典型約〇. 2至約〇. 5分。 當該矽層7係未攙雜或相當微量攙雜時，植入之攙雜物離 子透過該選擇之矽層7至該源極及汲極區8，用以形成該淺 接合面。此_例中’當該矽層7係微量攙雜時，除了植入之 攙雜物離子透過矽層7外，它之攙雜物可透過層7導入該源 極及》及極區中。 用於矽之典型p型攙雜物是硼、鋁、鎵及銦。用於矽之 典型η型攙雜物是砷、辨及銻。植入之攙雜物典型劑量約 1Ε13至約1Ε16原子/平方公分，更典型約5£13至約托15原 子/平方公分且在能量約1至約2 〇仟電子伏特（keV)。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂---------線 經濟部智慧財產局員工消費合作社印製 4391 90 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（5 ) 接著可利用如選取矽及多晶矽蚀刻劑之蝕刻來移去該邊 壁絕緣層6。然而，不需移去層6且若想要，此可保留。如 圖5所示，接著一氧化層9藉著在溫度約700至約900°C下加 熱來乳化該曝光之砂及多晶妙而成長。如圖5所示，此產 生絕緣邊壁間隔物於該閘極3之邊壁上及該源極/汲極區8 遇到該閘控導體3處之一錐形隔離以便減少電容値。進一 步，此確保在該源極/汲極區8及該閘控導體3之間一相當 窄之分離及絕緣。該絕緣邊壁間隔物9典型是約2 〇至約 100又厚。…— 接著，藉由如化學沉積法沉積及物理氣相沉積法在該邊 壁間隔物9上形成一第二絕緣間隔物1 〇。本絕緣間隔物1 〇 可以是二氧化矽或氮化矽或氮氧化矽。此層典型是約500 至约2000又厚。接著，未被該絕緣間隔物層1 〇覆蓋之氧化 層9藉、離子蝕刻反應來移去，其選擇性地停止於該選擇之 矽7上_〇 一第二選擇之矽1 1係藉由如化學沉積法沉積及成長。該 梦層11是一磊晶矽層並產生於曝光之單晶珍表面上之單晶 梦°選擇鼓:沙係偉於它曝光之矽表面上成長。該層11典型 地係約100至約500又厚。參見圖6。 ——形成金屬之矽化物如鎢、鈦、鈷或鎳接著在該曝光之 表面上形成。該金屬典型地是由氣相沉積或濺鍍技術來沉 積。參見圖8。該金屬與該襯底之單晶矽反應形成該對應 之金屬矽化物1 2。 若想要，接著可將該裝置作傳統式處理以便形成接點及 -3 ** 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 297公釐） (諳先閲讀背面之注意事項再填寫本頁) 裝--------訂--------故 4 3 91 9 0 . A7 ____._JB7____ 五、發明說明（6 ) 接線，用以提供該想要之成品裝置。 本發明之前述説明顯示及描述本發明。此外，該揭示僅 顯示及描述本發明之最佳具體實施例，惟如上述，將了解 本發明可用於不同之其它結合、修改及包圍且可在此所示 之本發明觀念之範圍内作改變或修改，使同於上面之敎示 及/或該相關技藝或知識。其上所示之具體實施例進一步 要説明實施本發明中已知之最佳模式及使熟知此項技藝之 人士運用本發明於此或具體實施例’及其它因特定應用所 需之不同修致中或使用本發明。因此，該説明書未要將本 發明限在此揭示之形式中。同時，要組合附上之申請專利 範圍以.包含另一具體實施例。 ------------j.----ο' 裝--------tr.---------線.. (請先閱壌背面之生意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 專利申請案 剖範圍修正本(90年3月） A8 B8 CS D8 六、申請專利範圍 43S1 9 0- » 1·—種用於製造一具有淺接合面之半導體裝置之方法，勹 括： ^ 提供一具有源極及汲極區與多晶矽閘極區之半導體基 質； 在該源極及汲極區上沉積選取之矽； 提供攙雜物至該源極及沒極區，用以形成淺接合面. 在該閘極區之邊聋上形成第一絕緣邊壁間隔物； 在該第一絕緣邊壁間隔物上形成第二絕緣間隔物；以 及 梦化該源極及沒極區之上表面。 2. 如申請專利範園第1項之方法，其中，攙雜該選取之發 層並藉將攙雜物從該選取之矽導入至該源極及汲極區來 形成該淺接合面。 3. 如申請專利範圍第2項之方法，其包括對導入之攙雜物 應用一短而快速之熱回火。 4. 如申請專利範園第3項之方法，其中，.該短而快速之熱 回火係施行於溫度約800°C至約1200°C下持續約0.05至約 1分鐘。 經濟部中央標牟局負工消费合作社印製 5. 如申請專利範圍第1項之方法，其中，未攙雜該選取之 矽層並藉將攙雜物離子植入至該源極及汲極區來形成該 淺接合面。 6. 如申請專利範圍第1項之方法，其中，該淺接合面是少 於 200A。 7. 如申讀專利範園第1項之方法，其中，該淺接合面是約 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X29?公嫠） 經濟部中央標準局貝工消費合作社印製 . 43 9190 AS § , -----------D8 六、申請專利範圍 5 0至約150又。 8. 如申凊專利範圍第i項之方法’其中，該第一絕緣邊壁 間隔物係藉熱氧化曝光之矽及多晶矽以在該源極及汲福 區接觸到該閘極區處產生錐形隔離而形成。 9. 如申請專利範圍第8項之方法’其中，該第—絕緣邊壁 間隔物是約2 0至約1 〇 〇人厚。 10. 如申請專利範園第j項之方法，其中’該第二絕緣邊壁 間隔物係選自於由二氧化矽、氮化矽、氮氧化矽及其混 合物所組成之组群中。 11. 如申請專利範.園第i 〇項之方法，其中，該第一絕緣邊 壁間隔物是約5〇〇至約2000人厚。 12. 如申請專利範圍第】項之方法’其中，該形成金屬之珍 化物係選自由鎢、鈦、姑、鎳及其混合物所，組成之組群 中。 13. 如申請專利範圍第【項之方法，其進一步包括在該基質 及該閘極區之間之閘極絕緣。 M.如申請專利範圍第1項之方法，其進一步包括在沉積該 選取之梦層前，在該閘極區邊壁上·提供邊璧絕緣層。 15. 如申請專利範圍第1 4項之方法，其進—步包括在形成 該淺接合面及在形成該第一絕緣邊壁間隔物前，移去該 邊壁絕緣層。 16. 如申請專利範園第1 5項之方法，其中，該邊壁絕緣層 是約1 0至約300 A厚。 . . 17. 如申請專利範圍第1項之方法，其進—步包括在該閘極 ' y -1---mj---- ^--In--訂 (請先閲讀背面之注$項再填寫本頁) -2“
    4391 90 A8 B8 C8 D8______ 六、申請專利範圍 區上提供絕緣帽° 18. 如申請專利範圍第1 7項之方法，其中’該絕緣帽係在 該源極及汲極區上沉積該選取之矽之前所提供的。 19. 如申請專利範園第1項之方法’其進—步包括在該源極 及汲極區上面之曝光單晶矽表面上提供一第二選取之矽 層。 20. 如申請專利範圍第.1 9項之方法’其中該第二選取之硬 層係於形成該第二絕緣間隔物之後提供。 (請先閲讀背面之注意事項再填寫本頁) -訂 經濟部中央標隼局負工消費合作社印裝 本紙張尺度逋用t國國家榇準（CNS > A4規格（210x297公羞）
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CN1264166A (zh) 2000-08-23
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US6022771A (en) 2000-02-08

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