TW438049U - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
TW438049U
TW438049U TW087200826U TW87200826U TW438049U TW 438049 U TW438049 U TW 438049U TW 087200826 U TW087200826 U TW 087200826U TW 87200826 U TW87200826 U TW 87200826U TW 438049 U TW438049 U TW 438049U
Authority
TW
Taiwan
Prior art keywords
semiconductor device
semiconductor
Prior art date
Application number
TW087200826U
Other languages
English (en)
Inventor
Tomoyuki Furuhata
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW438049U publication Critical patent/TW438049U/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW087200826U 1990-11-28 1991-11-27 Semiconductor device TW438049U (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP32809690 1990-11-28
JP32809590 1990-11-28
JP12095991 1991-05-27
JP12095891 1991-05-27

Publications (1)

Publication Number Publication Date
TW438049U true TW438049U (en) 2001-05-28

Family

ID=27470736

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087200826U TW438049U (en) 1990-11-28 1991-11-27 Semiconductor device

Country Status (7)

Country Link
US (1) US5315150A (zh)
EP (1) EP0488154B1 (zh)
JP (1) JP3144000B2 (zh)
KR (1) KR100232910B1 (zh)
DE (1) DE69132995T2 (zh)
HK (1) HK1013890A1 (zh)
TW (1) TW438049U (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69220067T2 (de) * 1992-11-18 1997-09-11 Sgs Thomson Microelectronics Herstellung von direkte Kontakten in hoher Dichte MOS/CMOS Verfahren
US5541137A (en) * 1994-03-24 1996-07-30 Micron Semiconductor Inc. Method of forming improved contacts from polysilicon to silicon or other polysilicon layers
US5466616A (en) * 1994-04-06 1995-11-14 United Microelectronics Corp. Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up
US5525552A (en) * 1995-06-08 1996-06-11 Taiwan Semiconductor Manufacturing Company Method for fabricating a MOSFET device with a buried contact
US5895766A (en) 1995-09-20 1999-04-20 Micron Technology, Inc. Method of forming a field effect transistor
US5652152A (en) * 1996-04-22 1997-07-29 Chartered Semiconductor Manufacturing Pte, Ltd. Process having high tolerance to buried contact mask misalignment by using a PSG spacer
US5721146A (en) * 1996-04-29 1998-02-24 Taiwan Semiconductor Manufacturing Company Ltd Method of forming buried contact architecture within a trench
US6211556B1 (en) * 1998-04-23 2001-04-03 Texas Instruments - Acer Incorporated Eliminating buried contact trench in MOSFET devices having self-aligned silicide
US6153934A (en) * 1998-07-30 2000-11-28 International Business Machines Corporation Buried butted contact and method for fabricating
JP2002198436A (ja) * 2000-12-25 2002-07-12 Sanyo Electric Co Ltd 半導体集積回路装置およびその製造方法
US7135373B2 (en) * 2003-09-23 2006-11-14 Texas Instruments Incorporated Reduction of channel hot carrier effects in transistor devices
JP2014093739A (ja) * 2012-11-06 2014-05-19 Nagase Techno-Engineering Co Ltd 集音装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7611774A (en) * 1976-10-25 1978-02-28 Philips Nv FET prodn. from silicon semiconductor body - by forming inlaid oxide region having aperture in which the field effect structure is formed
JPS56134757A (en) * 1980-03-26 1981-10-21 Nec Corp Complementary type mos semiconductor device and its manufacture
JPS60219771A (ja) * 1984-04-16 1985-11-02 Mitsubishi Electric Corp Mos形半導体装置の製造方法
JPS6113668A (ja) * 1984-06-29 1986-01-21 Hitachi Ltd 半導体装置
CA1258320A (en) * 1985-04-01 1989-08-08 Madhukar B. Vora Small contactless ram cell
JPH01147829A (ja) * 1987-12-04 1989-06-09 Toshiba Corp 半導体装置の製造方法
JP2508818B2 (ja) * 1988-10-03 1996-06-19 三菱電機株式会社 半導体装置の製造方法
JPH03194974A (ja) * 1989-12-22 1991-08-26 Fuji Electric Co Ltd Mos型半導体装置

Also Published As

Publication number Publication date
US5315150A (en) 1994-05-24
DE69132995D1 (de) 2002-05-29
KR100232910B1 (ko) 1999-12-01
DE69132995T2 (de) 2002-10-31
JPH0541486A (ja) 1993-02-19
EP0488154A3 (en) 1993-04-07
EP0488154B1 (en) 2002-04-24
HK1013890A1 (en) 1999-09-10
EP0488154A2 (en) 1992-06-03
JP3144000B2 (ja) 2001-03-07

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Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MK4K Expiration of patent term of a granted utility model