TW436866B - Mixed mode device - Google Patents
Mixed mode device Download PDFInfo
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- TW436866B TW436866B TW089100145A TW89100145A TW436866B TW 436866 B TW436866 B TW 436866B TW 089100145 A TW089100145 A TW 089100145A TW 89100145 A TW89100145 A TW 89100145A TW 436866 B TW436866 B TW 436866B
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- 239000002184 metal Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 28
- 229910044991 metal oxide Inorganic materials 0.000 claims description 17
- 150000004706 metal oxides Chemical class 0.000 claims description 17
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 230000002079 cooperative effect Effects 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
A7 >，厶368 6 6 5384twf.doc/008 B7 五、發明説明（l ) 本發明是有關於一種混合元件（Mixed-Mode)的設計， 且特別是有關於一種位於混合元件之最上方，用以連接混 合元件與測試裝置之焊墊設計。 習知在高頻混合元件中最常用的測試圖案(Test Pattern) 是具有指狀（Finger-Type)多晶矽的金氧半電晶體（]\^1&1-Oxide. Semiconductor Transistor，MOS)，如第 1 圖戶斤示。 第1圖繪示爲一種習知的混合元件的結構上視圖。在 提供的半導體基底100中有井區102，其導電型態與半導 體基底1〇〇相反，在半導體基底100大致對應於井區102 的上方有一層指狀的多晶砂層104，用以作爲金氧半電晶 體的閘極，而在多晶矽層104的兩側基底100中分別植入 有高濃度的摻質，形成源極區106以及汲極區108。一層 指狀的第一金屬層U0形成在半導體基底1〇〇上方，與金 氧半電晶體的汲極區108作電性耦接，而另外有一層長方 形的第二金屬層112，形成在半導體基底100上方，透過 介層洞114與金氧半電晶體的源極區106作電性親接。 習知以一種網路分析器(Network Analyzer)進行電性測 試時’通常多畢矽層1〇4會與網路分析器的傳遞端相連接， 藉以傳送電流訊號，金氧半電晶體的汲極區108與網路分 析器的接收端相連接，藉以接收電流訊號，而金氧半電晶 體的源極區106與基底1〇〇均接地。 由於第二金屬層112連接源極區106，因此接地的線 路會與第二金屬層112相接，其表現的電路狀態如第2圖 所示。自金氧半電晶體的閘極2〇4施加一電壓，其汲極區 3 ---------1^.----——1T------t (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消贲合作社印製 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局SK工消費合作社印製 A7 B7 五、發明説明（：） 202會有電流產生，自源極區206流出。如第1圖所示， 混合元件包括多個金氧半電晶體結構，每一個電晶體的源 極區106皆透過介層洞114連接到第二金屬層112，進一 步接地，其中第二金屬層Π2爲一長方形，也就是在每·一 個源極區106上方的面積大小相同，因爲每一個金氧半電 晶體的電流相同，在第二金屬層112上會累積匯流每一個 電晶體的電流，因此在源極區106的部分裝設一個電壓計 208時，會量測到一個電壓持續上社也龛造成一 個負面的回饋效果。 因此混合元件，大小調 整第二金屬層的面積，以降低其電阻，藉以降低來自於源 y端的倉而的雷懕回_g 3 本發明提供一種混合元件，其結構包括提供具有井區 的半導體基底，井區的導電型態與基底相反，在半導體基 底上有一層多晶矽層，部分的多晶矽層橫跨在井區上方， 以作爲電晶體的閘極，在閘極兩側的井區中有高濃度的摻 質的濃摻雜區，爲電晶體的源極/汲極區。第一層金屬層 位在閘極上方，具有指狀結構與電晶體的汲極區作電性耦 接，第二金屬層位於第一金屬層上方，透過介層洞與電晶 體的源極區作電性耦接。 其中，第二金屬層的設計並非習知的長方形，而是由 長方形與梯形姐^^_成，在連接介層洞的區域爲長万形， 而橫跨源極區-閘極-汲極區上方的區壞掛形^。由於梯 形的上)1¾長較下底小，因此與上底__的長方_形__小於與 ---------------訂------ΙΊ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 4 3 6 8 〇 6 A7 5384twf.doc/008 B7 五、發明説明（}) 下底相接的長方形，藉由梯形的部分使第二金屬層的面積 逐漸增加，面積增加會使電.阻遂逝下降，因此因爲電流增 加造成.的負回饋效應可因此被避免。 而且連接介層洞區域的第二金屬層仍維持長方形的設 計，以確保金屬層與介層洞的連接完整，不會因爲梯形上 窄下寬的形狀，在對準產生些許偏差時，第二金屬層無法 完全覆蓋介層洞的情況發生。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖繪示爲一種習知的混合元件的結構上視圖； 第2圖所示爲第1圖的混合元件之電路簡示；以及 第3圖繪示依照本發明一較佳實施例的一種混合元件 的結構上視圖。 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 圖示標記說明： 100, 300 半導體基底 102, 302 井區 104, 304 多晶矽層 106, 206, 306 源極區 108, 202, 308 汲極區 110, 310 第一金屬層 112, 312 第二金屬層 114, 314 介層洞 本紙張尺度適用中國囷家標準（CNS ) A4规格（210X297公釐） 5 1 ' 4 3 6 8 6 6 A7 5384 twf.doc/008 B7 五、發明説明（V ) 204 閘極 208 電壓計 (請先閲讀背面之注意事項再填寫本頁) 312a 第二金屬層的方形部分 312b 第二金屬層的梯形部分 實施例 第3圖繪示依照本發明一較佳實施例的一種混合元件 的結構上視圖。 請參照第3圖，本發明提供一種混合元件，其結構包 括提供具有井區302的半導體基底300，井區302的導電 型態與基底相反，在半導體基底300上有一層多晶矽層 304，部分的多晶矽層304橫跨在井區302上方，以作爲 電晶體的閘極，在閘極兩側的井區302中有高濃度的摻質 的濃摻雜區，爲電晶體的源極/汲極區306/308。第一層金 屬層310位在閘極上方，具有指狀結構與電晶體的汲極區 308作電性耦接，第二金屬層312位於第一金屬層310上 方，透過介層洞314與電晶體的源極區306作電性耦接。 經濟部智慧財產局員工消費合作杜印製 其中，第二金屬層312的設計並非習知的長方形，而 是由長方形邵分312a與梯形部分312b交替組合而成，在 連接介層洞314的區域312a爲長方形，而橫跨源極區-閘 極-汲極區上方的區域312b則爲梯形。 因爲電阻與導電層的長度成正比，而與導電層面積大 小成反比，由於梯形的上底^長較下底小，因此與上底相 接的長方形小於與下底相接的長方形，藉由梯形的部分使 第二金屬層312的面積逐漸增加，面積增加會使電阻逐漸 6 本紙張尺度適用中國國家標準（CNS ) A4说格（2丨0X29?公釐） ' 4368 6 6 A7 5384twf,doc/〇〇8 B7 五、發明説明（<) 下降，因此因爲電流增加造成的負回饋效應可被避免。 而且連接介層洞區域的第二金屬層仍維持長方形的設 計，以確保金屬層與介層洞的連接完整，不會因爲梯形上 窄下寬的形狀，在對準產生些許偏差時，第二金屬層無法 _完全覆蓋介層洞的情況發生。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消賫合作社印製 7 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐）
Claims (1)
- 經濟部智慧財產局員工消费合作杜印製 -* 436 8 6 6 B8 C8 _5384twf.doc/008_™_ 六、申請專利範圍 1. 一種混合元件的焊墊，用以覆蓋在一混合元件上方， 其中該混合元件包括複數個金氧半電晶體，包括： 複數個方形部分；以及 • 複數個梯形部分； 其中，該些方形部分係分別位於該些金氧半電晶體之 源極上方，並分別透過複數個介層洞與該些金氧半電晶體 之源極作電性耦接，而該些梯形部分係分別位於該些金氧 半導體之汲極上方。 2. 如申請專利範圍第1項所述之混合元件的焊墊，其 中該些方形部分更進一步覆蓋該些金氧半電晶體之部分源 極-閘極-汲極。 3. 如申請專利範圍第1項所述之混合元件的焊墊，其 中該些梯形部分更進一步覆蓋該些金氧半電晶體之部分汲 極-閘極-源極。 4. 如申請專利範圍第1項所述之混合元件的焊墊，其 中該些方形部分分別與該些梯形部分鄰接，且互相交替分 布。 5. 如申請.專利範圍第1項所述之混合元件的焊墊，其 中該些方形部分與該些梯形部分接皆爲金屬。 6. —種混合元件，包括： 複數個金氧半電晶體，分別共用複數個源極或複數個 汲極； 一第一金屬層，位於該金氧半電晶體上方，分別與該 些金氧半電晶體之汲極區電性耦接；以及 δ 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） _________Iχ— — — — — — — τ — — — — — — — I I^· 言· 矣· 1 (請先閒讀背面之注意事項再填寫本頁) 888β ABCD ^ 436866 5384twf.doc/008 六、申請專利範圍 一第二金屬層，橫跨於該些金氧半電晶體之上，透過 複數個介層洞與該些金氧半電晶體之源極作電性耦接； 其中該第二金屬層包括複數個方形部分與複數個梯形 •部分，該些方形部分橫跨該些金氧半電晶體之源極·閘極-汲極，而該些梯形部分橫跨該些金氧半電晶體之汲極-閘 極-源極。 7.如申請專利範圍第6項所述之混合元件，其中該第 二金屬層之寬度自該混合元件由內往外逐漸增加。 ------------/^--------訂---------線 (請先閱讀背面之注音U事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 9 本紙張尺度遶用中國國家標準（CNS)A4規格（210 X 297公釐〉
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089100145A TW436866B (en) | 2000-01-06 | 2000-01-06 | Mixed mode device |
| US09/493,387 US6236092B1 (en) | 2000-01-06 | 2000-01-28 | Mixed mode device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089100145A TW436866B (en) | 2000-01-06 | 2000-01-06 | Mixed mode device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW436866B true TW436866B (en) | 2001-05-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089100145A TW436866B (en) | 2000-01-06 | 2000-01-06 | Mixed mode device |
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|---|---|
| US (1) | US6236092B1 (zh) |
| TW (1) | TW436866B (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111384024A (zh) * | 2018-12-27 | 2020-07-07 | 南亚科技股份有限公司 | 半导体结构及其制备方法 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002203957A (ja) * | 2000-12-28 | 2002-07-19 | Rohm Co Ltd | トランジスタ |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4158807A (en) * | 1977-04-25 | 1979-06-19 | Massachusetts Institute Of Technology | Gapped gate charge-flow transistor with a thin film sensor having two modes of conduction within the gapped gate used to sense a property of the ambient environment |
| US5283452A (en) * | 1992-02-14 | 1994-02-01 | Hughes Aircraft Company | Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier |
| US5925901A (en) * | 1997-03-21 | 1999-07-20 | Nec Corporation | Field effect transistor with plated heat sink on a fet chip |
| JP3515886B2 (ja) * | 1997-09-29 | 2004-04-05 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
-
2000
- 2000-01-06 TW TW089100145A patent/TW436866B/zh not_active IP Right Cessation
- 2000-01-28 US US09/493,387 patent/US6236092B1/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111384024A (zh) * | 2018-12-27 | 2020-07-07 | 南亚科技股份有限公司 | 半导体结构及其制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US6236092B1 (en) | 2001-05-22 |
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