TW431067B - Single source differential circuit - Google Patents

Single source differential circuit

Info

Publication number
TW431067B
TW431067B TW084100503A TW84100503A TW431067B TW 431067 B TW431067 B TW 431067B TW 084100503 A TW084100503 A TW 084100503A TW 84100503 A TW84100503 A TW 84100503A TW 431067 B TW431067 B TW 431067B
Authority
TW
Taiwan
Prior art keywords
circuit
source
source follower
delay
data input
Prior art date
Application number
TW084100503A
Other languages
English (en)
Inventor
Tai Anh Cao
Satyajit Dutta
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW431067B publication Critical patent/TW431067B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
TW084100503A 1994-06-22 1995-01-20 Single source differential circuit TW431067B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26412194A 1994-06-22 1994-06-22

Publications (1)

Publication Number Publication Date
TW431067B true TW431067B (en) 2001-04-21

Family

ID=23004680

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084100503A TW431067B (en) 1994-06-22 1995-01-20 Single source differential circuit

Country Status (4)

Country Link
US (1) US5530401A (zh)
JP (1) JPH0818358A (zh)
KR (1) KR0153067B1 (zh)
TW (1) TW431067B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821809A (en) * 1996-05-23 1998-10-13 International Business Machines Corporation CMOS high-speed differential to single-ended converter circuit
JP3045071B2 (ja) * 1996-05-30 2000-05-22 日本電気株式会社 差動信号生成回路
US5801549A (en) * 1996-12-13 1998-09-01 International Business Machines Corporation Simultaneous transmission bidirectional repeater and initialization mechanism
US6411151B1 (en) * 1999-12-13 2002-06-25 Inter Corporation Low jitter external clocking
US6366168B1 (en) * 2000-03-20 2002-04-02 Marvell International Ltd. Efficient ground noise and common-mode suppression network
US6775526B2 (en) 2000-12-01 2004-08-10 Microchip Technology Incorporated Modulated input signal filter

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2252130C2 (de) * 1972-10-24 1978-06-08 Deutsche Itt Industries Gmbh, 7800 Freiburg Monolithisch integrierte Schmitt-Trigger-Schaltung aus Isolierschicht-Feldeffekttransistoren
JPS5318308B2 (zh) * 1973-03-05 1978-06-14
GB1480984A (en) * 1975-09-25 1977-07-27 Standard Telephones Cables Ltd Schmitt trigger circuit
JPS5783930A (en) * 1980-11-12 1982-05-26 Fujitsu Ltd Buffer circuit
JPS5877317A (ja) * 1981-11-02 1983-05-10 Matsushita Electric Ind Co Ltd シユミツト・トリガ回路
US4507795A (en) * 1983-02-14 1985-03-26 Motorola, Inc. Apparatus and method for locating leading and trailing edges of RF pulses
US4687954A (en) * 1984-03-06 1987-08-18 Kabushiki Kaisha Toshiba CMOS hysteresis circuit with enable switch or natural transistor
US4677388A (en) * 1985-10-17 1987-06-30 Ampex Corporation Synchronization slicer
JPS62294328A (ja) * 1986-06-13 1987-12-21 Nec Corp カレントスイツチ
US4733107A (en) * 1986-07-10 1988-03-22 Western Digital Corporation Low current high precision CMOS schmitt trigger circuit
US4677315A (en) * 1986-07-28 1987-06-30 Signetics Corporation Switching circuit with hysteresis
JPH02142214A (ja) * 1988-11-24 1990-05-31 Nippon Motoroola Kk オフセット電圧を補償したラッチングコンパレータ
JP2635778B2 (ja) * 1989-09-21 1997-07-30 株式会社東芝 パルス回路
US5034623A (en) * 1989-12-28 1991-07-23 Texas Instruments Incorporated Low power, TTL level CMOS input buffer with hysteresis
JPH0555881A (ja) * 1991-08-27 1993-03-05 Toshiba Corp 遅延回路
US5274273A (en) * 1992-01-31 1993-12-28 Sperry Marine Inc. Method and apparatus for establishing a threshold with the use of a delay line

Also Published As

Publication number Publication date
KR960003101A (ko) 1996-01-26
KR0153067B1 (ko) 1998-12-15
US5530401A (en) 1996-06-25
JPH0818358A (ja) 1996-01-19

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees