TW429375B - Memory device including a double-rate input/output circuit - Google Patents

Memory device including a double-rate input/output circuit

Info

Publication number
TW429375B
TW429375B TW088106956A TW88106956A TW429375B TW 429375 B TW429375 B TW 429375B TW 088106956 A TW088106956 A TW 088106956A TW 88106956 A TW88106956 A TW 88106956A TW 429375 B TW429375 B TW 429375B
Authority
TW
Taiwan
Prior art keywords
data
write
memory device
output circuit
double
Prior art date
Application number
TW088106956A
Other languages
English (en)
Inventor
Tatsuya Kanda
Hiroyoshi Tomita
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW429375B publication Critical patent/TW429375B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW088106956A 1998-10-08 1999-04-29 Memory device including a double-rate input/output circuit TW429375B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28648898A JP3604291B2 (ja) 1998-10-08 1998-10-08 ダブルレートの入出力回路を有するメモリデバイス

Publications (1)

Publication Number Publication Date
TW429375B true TW429375B (en) 2001-04-11

Family

ID=17705061

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088106956A TW429375B (en) 1998-10-08 1999-04-29 Memory device including a double-rate input/output circuit

Country Status (4)

Country Link
US (1) US6208582B1 (zh)
JP (1) JP3604291B2 (zh)
KR (1) KR100323257B1 (zh)
TW (1) TW429375B (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4216415B2 (ja) 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
KR100372247B1 (ko) * 2000-05-22 2003-02-17 삼성전자주식회사 프리페치 동작모드를 가지는 반도체 메모리 장치 및 메인데이터 라인수를 줄이기 위한 데이터 전송방법
JP4569915B2 (ja) * 2000-08-11 2010-10-27 エルピーダメモリ株式会社 半導体記憶装置
JP2003022674A (ja) * 2001-07-10 2003-01-24 Fujitsu Ltd 可変設定されるデータ入出力端子とその制御信号端子を有する半導体メモリデバイス
JP3542574B2 (ja) * 2001-08-28 2004-07-14 Ｎｅｃマイクロシステム株式会社 システムクロック同期化回路
KR100428684B1 (ko) * 2001-09-24 2004-04-30 주식회사 하이닉스반도체 제어신호의 마스킹을 고려한 반도체 기억장치
DE10159180B4 (de) * 2001-11-30 2011-07-14 Qimonda AG, 81739 Speichervorrichtung und Verfahren zum Speichern und zum Auslesen von Datenströmen
FR2839830A1 (fr) * 2002-05-17 2003-11-21 Koninkl Philips Electronics Nv Memoire pour decodeur turbo
KR100486263B1 (ko) * 2002-09-19 2005-05-03 삼성전자주식회사 Ｓｄｒ/ｄｄｒ 겸용 반도체 메모리 장치의 데이터 출력 회로
JP2004185134A (ja) * 2002-11-29 2004-07-02 Matsushita Electric Ind Co Ltd 記憶装置
KR100507367B1 (ko) * 2003-01-24 2005-08-05 주식회사 하이닉스반도체 불휘발성 강유전체 메모리를 이용한 직렬 버스 제어 장치
US7177379B1 (en) 2003-04-29 2007-02-13 Advanced Micro Devices, Inc. DDR on-the-fly synchronization
JP4615896B2 (ja) 2004-05-25 2011-01-19 富士通セミコンダクター株式会社 半導体記憶装置および該半導体記憶装置の制御方法
US7170813B2 (en) * 2004-12-16 2007-01-30 Infineon Technologies Ag Memory circuit receivers activated by enable circuit
KR100605607B1 (ko) * 2005-06-30 2006-08-01 주식회사 하이닉스반도체 반도체 메모리 장치
KR100744042B1 (ko) * 2005-09-28 2007-07-30 주식회사 하이닉스반도체 반도체메모리소자의 내부 어드레스 생성장치
JP4708176B2 (ja) * 2005-12-08 2011-06-22 エルピーダメモリ株式会社 半導体装置
US7397727B2 (en) * 2005-12-22 2008-07-08 Infineon Technologies Ag Write burst stop function in low power DDR sDRAM
US8274412B1 (en) 2011-01-10 2012-09-25 Lattice Semiconductor Corporation Serializer with odd gearing ratio
US10622065B2 (en) * 2018-09-12 2020-04-14 Micron Technology, Inc. Dedicated commands for memory operations

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3319105B2 (ja) * 1993-12-15 2002-08-26 富士通株式会社 同期型メモリ

Also Published As

Publication number Publication date
JP2000113671A (ja) 2000-04-21
JP3604291B2 (ja) 2004-12-22
KR100323257B1 (ko) 2002-02-04
US6208582B1 (en) 2001-03-27
KR20000028575A (ko) 2000-05-25

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