TW423118B - CMOS process having poly-SiGe gate - Google Patents

Abstract

This invention is about CMOS process having poly-SiGe gate and can be used in the dual gate CMOS process. The Ge compositions of the NMOS and the PMOS transistors can be adjusted according to the designed requirement such that the purpose of optimizing the whole CMOS is obtained without increasing extra mask.

Description

4 23118 V. Description of the invention ¢ 1) The present invention relates to a CMOS process, and particularly to a CMOS process with a Poly-Si Ge gate. Nowadays, ‘to meet the requirements of high computing speed, low power consumption, and high accumulation’, CMOS semiconductor process technology has continued to develop into the deep-submicron field. With the continuous advancement of semiconductor process technology, the width and thickness of the gate of the MOS transistor and the thickness of the gate oxide layer have been reduced. Because the gate oxide thickness is reduced and the doped carrier concentration of the polycrystalline stone is not high enough, the polycrystalline silicon gate is prone to generate a depletion region without carriers near the gate oxide layer interface. 'As a result, the so-called "poiy-gate depletion effect (PDE) " will affect the performance of the M0S transistor. In addition,' P + complex dream gates are used in deep submicron processes. It also encounters the problem of Boron penetration. Recent research has pointed out that PolyHxGex is a very promising choice for gates (where X represents the proportion of Ge in Poly-SiGe). Because it has Poly- Si ^ Ge, the gate element, in addition to having a lower gate sheet resistance and a higher driving current, and can reduce the polycrystalline silicon gate depletion effect (PDE). In addition, for the problem of boron penetration Can also be effectively reduced.

Wen-Chin Lee et al. In the paper "Optimized Poly-SU '^ -Gate T ech η ο 1 〇gyf 〇r D ua 1 Gate C Μ 0 SA pp 1 icati 〇η" (1998 VLSI Technical Conference) The data disclosed in the article pointed out that: for NMOS transistors, when the proportion X of Ge is greater than 20%, the gate gap width will increase and the active carrier concentration will decrease; otherwise, for PMOS transistors,

Page 4 V. Description of the invention (2) When the component ratio X of Ge is greater than 20%, the gate empty width will decrease and the active carrier Han degree will increase. Because the driving ability of NMOS transistors is better than PMOS transistors, NMOS is still the main component in the fabrication of integrated circuits. In addition, Poly-SUex dual-gate CMOS process is now used for NMOS and PMOS transistors. It is still impossible to set different ratios of the Ge components in the gates (respectively P + gates and N + gates). Therefore, in the case of taking NMOS characteristics as the main consideration; Wen-Chin Lee believes that when the poiy-SilxGex gate is applied to the dual gate CM OS technology, when the composition ratio x of Ge is about At about 20%, optimized results can be obtained (but the characteristics are only within acceptable ranges, and may not be optimized; because for the PM0S transistor, 'p〇iy —sl xGex gate The more Ge's composition ratio, the better its performance. For the dual-gate CMOS process of the Poly-Si ^ Gex gate, if the Ge components in the NMOS and PM0S transistor gates can be set to different ratios, then the NMOS and PM0S transistors are optimized separately. For the overall CMOS device, better performance can be obtained. In view of this, "the purpose of the present invention is to propose a (dual interpolar) CMOS process with a poly_SiGe gate" which enables one of the NMOS and PMOS transistor gates

Ge composition ’has different composition ratios according to the design requirements, so as to achieve the purpose of overall CMOS optimization. In order to achieve the above object, the first CMOS process with a Poly-SiGe gate provided by the present invention includes the following steps: providing a half-conductor substrate 'having an N-type well region, a p-type well region, and an insulating structure (for example, a shallow

5. Description of the invention on page 5 (3) Trench isolation area), the above-mentioned insulating structure electrically isolates the above P 蜇 and N-type well areas; forming a gate dielectric layer on the semiconductor substrate; sequentially forming Poly -Si Ge layer, and a first insulating layer (such as a silicon nitride layer) on the gate dielectric layer; the proportion of Ge and Si in the Poly-Si Ge layer is X% and (100 ™ x) %; Among them, the Poly-SiGe layer above the N-type well region is the first Poly-SiGe layer, and the Poly-SiGe layer above the P-type well region is the second Poly-SiGe layer; the N-type well region is removed The first insulating layer above retains the first insulating layer above the P-type 丼 region; heating and oxidizing C, for example, using the thermal oxygen method), the first Poly_SiGe layer causes its surface to form an oxide layer. In the p〇ly_SiGe layer, and the composition ratio of y Ge and S i becomes y% and (1 q 〇 _ y)% except for the first insulating layer above the P-type well region, and the second Poly-SiGe is exposed. Layer; removing the oxide layer to expose the first Poly-SiGe layer; forming a conductive layer (such as a metal layer) on the first On the second Poly-SiGe layer; define the etching of the conductive layer and the first and second Poly-SiGe layers' to expose the gate dielectric layer to form a gate structure on the N-type and p-type wells, respectively Above the region; and the subsequent process of lining and source / drain region. In order to achieve the above, the present invention proposes a Poly-SiGe interrogation process, which includes a body substrate, has an N-type well area, and „blanket for supply + guide trench isolation area. Edge structure (for example, shallow isolation; formation of an idler dielectric layer on top of a P-type, N-type well area to be electrically-converted to a Poly-SiGe layer, and a first insulating layer) on a bulk substrate; sequentially forming a marginal layer (For example, a vaporized silicon layer)

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4 23 1 1 B V. Description of the invention (4) On the gate dielectric layer; the proportions of Ge and Si in the above-mentioned Polly-Si Ge layer are X% and (100-x)%; The Po y-S i Ge layer above the P-well area is the first Po y-S i Ge layer. The Poly-SiGe layer above the p-well area is the second Po-SiGe layer; Remove the first insulating layer above the p-type well area, and retain the first-insulating layer above the n-type well area; bring an unpressed polycrystalline stone layer on the first insulating layer, and the second Pol on the y-SiGe layer; remove the undoped polycrystalline stone layer above the N-type well region; and retain the undoped and doped polycrystalline silicon layer above the P-type well region; perform a heating process (for example, high temperature) Tempering procedure) to diffuse the Ge in the second poly_SiGe layer to the undoped polycrystalline silicon layer; wherein, in the second Poly-SiGe layer, the composition ratio of Ge and Si becomes z% and (100%)%, and z <x; remove the first insulating layer above the p-type well region to expose the first Poly-SiGe layer; form a conductive layer (eg, a metal layer) on the , The first Poly_Si Ge layer 'and the above-mentioned undoped polycrystalline silicon layer; define the etching of the above-mentioned conductive layer, the above-mentioned first 1504_ and (^ layer: and the above-mentioned undoped polycrystalline silicon layer, and expose the gate The electrode dielectric layer is used to form gate structures above the N-type and p-type well regions, respectively; and, the completed process of the side lining and source / drain regions. '' Brief description of the drawings: In order to make the present invention The above-mentioned objects, features, and advantages can be more obvious and easy to understand 1: Wente cites two preferred embodiments, and cooperates with the attached drawings < to make a detailed description as follows: FIGS. 1A to 11 show the invention according to the present invention. Flow chart of the first embodiment

Page 7 5. Description of the invention (5) Plan view; and Figs. 2A to 2I show cross-sectional views of a process according to the second embodiment of the present invention. Explanation of symbols: 1 ~ semiconductor substrate; 2 ~ N type well area; 3 ~ P type well area; 4 ~ insulation structure; 5 ~ gate dielectric layer; 6 ~ Poly-SiGe layer; 6a ~ first Poly-SiGe layer 6b ~ second Poly-SiGe layer; 7 ~ first insulating layer; 8 ~ oxide layer; 9 ~ conductive layer; 10, 11 ~ gate structure; 12, 13 ~ side lining; 1 4, 1 5 ~ source / No pole region; 16 ~ PM0S transistor; 17 ~ NM0S transistor; 2 ~ Undoped polycrystalline silicon. Embodiment one:

4 23 11 8 V. Description of the invention (6) Figures 1A to 1I show sectional views of the process according to the first embodiment of the present invention. According to a first embodiment of the present invention, a semiconductor substrate 1 is first provided, which has an N-type (first type) well region 2, a p-type (second type) well region 3, and an insulation structure 4; the above-mentioned insulation structure 4 is, for example, shallow A trench isolation (sha 1 1 0wtrench isolation; STI) structure is used to electrically isolate the above-mentioned N-type and p-type well regions (2, 3). A gate dielectric layer 5 (for example, a thin oxide layer) is further formed on the semiconductor substrate 1. The result is shown in FIG. 1A. Using LPCVD ', a Poly-SiGe layer 6 and a first insulating layer 7 are sequentially deposited on the gate dielectric layer 5; the results are shown in FIG. 1B. Above

The composition ratios of Ge and Si in the Poly-SiGe layer 6 are Xl% and (i〇〇_x 丨)%; wherein the thickness of the above-mentioned Poly-SiGe layer 6 is between 30 and 50 ηα, and the above-mentioned N-type well region 2 The upper Poly-SiGe layer is a first Poly-SiGe layer 6a, the above Poly-SiGe layer above the P-type well region 3 is a second Poly-SiGe layer 6b; the above-mentioned first insulating layer 7, in this embodiment, It is a silicon nitride layer with a thickness ranging from 30 to 50 nm. Then, the first insulating layer 7 above the N-type well region 2 is removed by using active ion etching (r IE) to expose the above-mentioned p-iy_SiGe layer. Therefore, the first insulating layer 7 above the P-type well region 3 is retained, as shown in FIG. Here, it is also possible to use the first insulating layer 7 above the p-type well region 3 as a mask to perform ion implantation (using B + or BF 彳 ions) on the first Poly_SiGe layer 6a to provide p + -type p. ly —Si gives PMOS transistor. An oxide layer 8 'is formed on the first Poly-SiGe layer 6a using the thermal oxygen method as shown in FIG. 1D. Of which, because of being oxidized during the thermal oxidation process,

423118 ''

The Ge in the Poly-SiGe layer will be pushed out and diffuse out to the first Poly-SiGe layer 6a which is not oxidized; therefore, in the first Poly-SiGe layer 6a which is not oxidized, the Ge and Si The component ratio becomes y% and (100-y)%, and y > X. ‘So, make the Zhou IPO4 solution remove the first-insulator layer 7 (nitride stone layer) above the p-type well area 3 and expose the second? 〇1 丫 _ 以 (^ 层 61;); As shown in Figure 1E. Here, the second Poly-SiGe layer 6b can also be ion-implanted (using As + or p + ions) using the oxide layer 8 as a mask, so as to provide a type 1 port for the 05 transistor. The BOE is then used to remove the oxide layer 8 to expose the first Poly-SiGe layer 6a; as shown in FIG. 1F. A conductive layer 9 'is deposited on the first and second layers (6a' 6b); as shown in Fig. 1G. The aforementioned 'conductive layer 9 is, for example, a metal layer having a thickness of 50 to 200 nm. The gate etching process is performed to perform a remainder on the conductive layer 9 and the first and first SiGe layers (6a'6b), and the gate dielectric layer 5 'is exposed to form gate structures (丨 0, u) above the N, p-type 丼 region (2, 3); as shown in Figure 1H. The subsequent processes of the side lining (12, 13), the source /; and the polar region (η, 15) are completed to form a PMOS transistor 16 and a NMOS transistor 17, as shown in FIG. Second embodiment: Figures 2A to 2I show a flow chart according to a second embodiment of the present invention.

Page 10 42311δ V. Description of the invention (8) A plan view; where ′ is the same as or similar to the first embodiment, it is indicated by the same number or symbol. According to a first embodiment of the present invention, a semiconductor substrate 1 is first provided, which has an N-type (first type) well region 2, a P-type (second type) well region 3, and an insulation structure 4; the above-mentioned insulation structure 4 is, for example, shallow A trench isolation (STI) structure is used to electrically isolate the N-type and P-type well regions (2, 3). A gate dielectric layer 5 (for example, a thin oxide layer) is further formed on the semiconductor substrate 1 described above, and the result is shown in FIG. 2A = using the LPCVD method to sequentially deposit the Poly-SiGe layer 6 and the first The insulating layer 7 is on the gate dielectric layer 5; the result is shown in FIG. 2B. Above

The composition ratios of Ge and Si in the Poly-SiGe layer 6 are χ2% and (100_center)%; where the thickness of the above-mentioned Poly-SiGe layer 6 is between 30 and 50 nra, and the P above the above-mentioned N-type well region 2 The Oly-SiGe layer is the first poly-SiGe layer 6a, and the Poly-SiGe layer above the P-type well region 3 is the second poly-SiGe layer 6b; the above-mentioned first insulating layer 7, in this embodiment It is a silicon nitride layer with a thickness between 30 and 50 nm. Next, the first insulating layer 7 above the P-type well region 3 is removed, and the second Poly-SiGe layer 6b is exposed, and the N-type well region is retained. The first insulating layer 7 above 2 is shown in FIG. 2C. An undoped poly-Si layer 20 is formed on the first insulating layer 7 and the second Poly-Si Ge layer 6b, as shown in the outer figure. The active ion etching method (r I £) is used to remove the undoped polycrystalline silicon layer 20 above the N-type well region 2 and leave the undoped above the P-type well region 3

Page 11 423118 V. Description of the invention (9) Polycrystalline silicon layer 20. Then 'at a temperature between 80 and 1050. Under the condition of C, an annealing process is performed. The Ge content of the second poiy-SiGe layer 6b is due to the fact that the Ge in the second poi_SiGe layer 6b above the P-type ytterbium region 3 will diffuse to the undoped polycrystalline silicon 20 during high temperature annealing. % Becomes z% 'and z <x2; the result is shown in Fig. 2E. The Y3P04 solution is used to remove the first insulating layer 7 (silicon nitride layer) above the N-type Y region 2 to expose the first Poly-Si Ge layer 6a; as shown in FIG. 2F. A conductive layer 9 'is deposited on the first and second poiy-Si Ge layers (6a, 6b); as shown in FIG. 2G. As mentioned above, the conductive layer 9 is, for example, a metal layer with a thickness of 50 to 200 nm. The gate #etching process is performed, and the conductive layer 9 and the first and second Poly-SiGe layers (6a, 6b) are left etched to expose the gate dielectric layer 5 ′ to form gate structures ( 10, π) above the N, p-type well area (2, 3); as shown in Figure 2H. The subsequent processes of the side linings (12, 13), and the source / j: and the polar regions (14, 15) are completed to form a PMOS transistor 16 and a NMOS transistor 17, as shown in FIG. For the first embodiment, in the pre-deposited poly_SiGe layer, the Ge component accounts for X!%. When the process of the first embodiment is completed, in the Poly-SiGe gate of the PMOS transistor, the Ge component ratio becomes y%, and the ratio of the pseudotransistor? In the 〇17-5166 gate, the 〇6 component ratio is still meaning%, and y> 4. All

Page 5 (5) Description of the invention (10) Therefore, 1C manufacturers can pre-set the NM0S transistor so that the proportion of Ge component in the Poly-SiGe gate is about 20% (that is, X1 = 320). In addition, according to the method of the first embodiment of the present invention, the Ge component ratio y% in the Poly-SiGe gate of the PMOS transistor obtained will be greater than 20% (that is, y > X]). Therefore, according to the method of the first implementation of the present invention, for the PM0s and NMOS transistors, the ratio of the Ge composition ratio of their Poly-SiGe gates can be set separately to achieve the purpose of optimization. The performance is no longer limited by the NMOS transistor (that is, the poly composition of the poly-SiGe gate of the pMOS transistor does not have to be the same as that of the NMOS transistor), so the overall CMOS performance can be increased. For the second embodiment, the pre-deposited Poly-Si Ge layer has a Ge component of X2%. When the process of the second embodiment is completed, the proportion of Ge in the Poly-SiGe gate of the NMOS transistor becomes z%, and that of the pMOS transistor? The proportion of the '〇6 component in the 〇17-51〇6 pole is still &%, and 2 < ~. Therefore, a '1C manufacturer can preset a pMOS transistor so that the proportion of the Ge component in the poly_SiGe gate is greater than 20% (for example, & Ξ 25), and according to the method of the second embodiment of the present invention, In the fabricated NMOS transistor, the proportion of Ge in its Poly-Si Ge gate becomes z% and is less than 25% (that is, z < & 'for example, z% becomes about 20%) . Therefore, in the same way, according to the method of the second embodiment of the present invention, the ratio of Ge components of pOiy-Si Ge gates can be set respectively for pM0s and the passivation transistor to optimize. The purpose of the performance of PM 0s transistor is no longer subject to the limitation of NMOS transistor (ie, the PM composition of PM 0s transistor p0ly_SiGe gate does not have to be the same as that of NMOS transistor), so it can be Increase overall cm〇s

Page 13 m 423118 V. Description of the invention. (11) Performance performance. From the above, it can be known that using the method of the present invention can have the following advantages:-In the double idle CMOS process, the PMOS transistor and the 008 transistor can be set to 1301 ¥ _ $ 1 (^ in the gate electrode respectively). The 66 component ratio makes the Ge component of the PMOS transistor greater than the Ge component of the NMOS transistor '| to achieve the purpose of optimization. — The method of the present invention is applied, whose process steps are compatible with the traditional double gate -P〇ly-SiGe gate CM〇s process' no need to add extra light for Si :: Already ::::::: The example is exposed as above, but it is not the spirit and scope, when; Without departing from the scope of the present invention, it should be attached as appended ... patentee = this invention

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Claims (1)

4 2311 8 VI. Scope of patent application I. A CMOS process with a Poly-SiGe gate, including: providing a semiconductor substrate with a first well region, a second well region, and an insulation structure; The first and second type well regions are electrically isolated; a gate dielectric layer is formed on the semiconductor substrate; a Poly-SiGe layer and a first insulating layer are sequentially formed on the gate dielectric layer; the P The composition ratios of Ge and Si in the 〇ly-Si Ge layer are X% and (100-X)%; wherein, the Poly-SiGe layer above the first type well region is the first Poly-SiGe layer. The Poly-SiGe layer above the type well area is the second Poly-SiGe layer; the first insulation layer above the first type well area is removed, and the first insulation layer above the second type well area is retained; The above-mentioned first POiy-SiGe layer is formed on its surface to form an oxide layer; wherein in the above-mentioned first Poly_SiGe layer which has not been oxidized, the composition ratio of Ge * Si becomes y% and (100-y)% And y >χ; remove the first insulating layer above the first type well area, and expose the second Poly- A SiGe layer; removing the oxide layer ’to expose the first poly_SiGe layer; forming a conductive layer on the first and second? 〇17_5 丨 (^ layer; the last name is engraved on the conductive layer, and the first and second layers, and the gate dielectric layer is exposed to form a gate structure in the first and second well areas, respectively. Above; and complete the subsequent process of lining the source / inverted region. 2. The process as described in the scope of patent application: Item 1, where the above Page 15 4 23 1 1 8 Six-application patent range Poly-SiGe layer system. Deposited using LPCVD method, thickness is 30nra ° 3. The process described in item 1 of the patent application range, wherein the above The first insulating layer is a nitride obtained by LPCVD; the ε layer has a thickness of 30 to 50 nm. 4. The process according to item 3 of the scope of patent application, wherein the removal of the first insulating layer 'above the first type well area is by using an active ion etching method. 5. The process according to item 3 of the scope of patent application, wherein the removal of the first insulating layer 'above the second type well area uses an h3P04 solution. 6 ‘The process as described in item 1 of the scope of patent application, wherein the first Poly-SiGe layer is oxidized by heating using a thermal oxygen method. 7. The process described in item 1 of the scope of patent application said oxide layer is etched using BOE. 8. The process described in item 1 of the scope of the patent application The electrical layer is a metal layer with a thickness of 50 ~ 200 nm. 9. As described in item 1 of the scope of the patent application, the light-type well area is an N-type well area, and the second type well area is a p-type well area \ 0. A CM0S process with a Poly-SiGe gate, Including: and a semiconductor substrate for insulation, having a first type well area, a second type well area, and an electric edge structure, the above-mentioned insulation structure electrically isolates the first and second type well areas; forming a gate dielectric Layer on the semiconductor substrate; a Poly-Si Ge layer and a first insulating layer are sequentially formed on the gate dielectric 50; Page 16 4 23118 6. On the electric layer for patent application; the proportion of Ge and Si in the above Poly-SiGe layer is x% and (100-x)%; among them, the Poiy- The SiGe layer is a first Poly-SiGe layer, and the Poly-SiGe layer above the second type well region is a second Poly-SiGe layer; removing the first insulating layer above the second type well region, and leaving the first A first insulating layer above the well region; forming an undoped polycrystalline spar layer on the first insulating layer and the second Poly-SiGe layer; removing the The doped polycrystalline silicon layer 'retains the undoped polycrystalline silicon layer above the second type well region; and a heating process is performed to make the Ge in the second poly_SiGe layer to the undoped polycrystalline silicon layer. Diffusion; wherein the composition ratio of 'Ge and Si' in the second Poly-SiGe layer becomes z% and (100-z)%, and z <X; remove the first insulating layer above the first type well region And expose the first Poly-SiGe layer; forming a conductive layer on the first poly_SiGe layer and the above-mentioned un-doped Above the polycrystalline silicon layer; define the above-mentioned conductive layer, the first Poly-SiGe layer, and the undoped polycrystalline silicon layer, and expose the gate dielectric layer to form a gate structure respectively on the above Above the first and second well areas; and complete the subsequent lining and source / drain region processes. 11. The process according to item 10 of the scope of patent application, wherein the Poly-SiGe layer is deposited by Lpcv]) method, and the thickness is between 30 and 50. Page 17 423118 VI. Patent Application Range nm. 1 2. The process according to item 10 of the scope of the patent application, wherein the first insulating layer is a silicon nitride layer deposited by LPCVD and has a thickness of 30 to 50 nm. 1 3. According to the process described in the scope of application patent No. 12 (1), wherein the removal of the first insulating layer above the second type well area is performed by an active ion etching method. 1 4. The process ′ described in item 12 of the scope of the patent application, wherein the removal of the first insulation layer above the first type well area ′ uses a Η3 Ρ04 solution. 15. The process according to item 10 of the scope of the patent application, wherein the heating process is a high-temperature tempering process, and the temperature is between 800 and 105 ° C. 16. The process according to item 10 of the scope of patent application, wherein the undoped polycrystalline silicon layer above the first type well region is removed by using an active fence etching method. 17. The system described in item 10 of the scope of application for a patent, wherein the conductive layer is a metal layer with a thickness of 50 to 200 nm. 18. The process according to item 10 of the scope of patent application, wherein the first type well area is an N type well area, and the second type well area is a p type well area. ^ Page 18