JP4723182B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as a MIS (Metal insulator semiconductor) field effect transistor and a manufacturing method thereof.

  In recent years, with the high integration of semiconductor integrated circuits, the gate length of MIS field effect transistors has been miniaturized. In a field effect transistor having such a fine gate length, short channel effects such as a large dependency of the threshold voltage on the gate length and a tendency of punch-through between the source and the drain appear.

  As one method for preventing such a short channel effect, an MIS field effect transistor having a second gate electrode on the side wall of the gate electrode has been proposed (see, for example, Non-Patent Document 1). A cross-sectional view of this conventional MIS type field effect transistor is shown in FIG.

  According to the MIS field effect transistor, as shown in FIG. 7, the first gate insulating film 114 formed on the silicon substrate 101 and the first gate insulating film 114 formed on the first gate insulating film 114 are formed. Of the surface of the silicon substrate 101, the first gate electrode 115 and the second gate electrode 117 formed so as to cover the first gate electrode 115 with the second gate insulating film 116 interposed therebetween. The source region 109 and the drain region 110 are formed at positions away from the channel region under the electrode 115.

  According to the above configuration, an inversion layer is formed on the surface of the silicon substrate 101 immediately below the second gate electrode 117 by applying a voltage to the second gate electrode 117 independently of the first gate electrode 115. Shallow source / drain extensions can be formed. Thereby, the short channel effect can be extremely suppressed.

However, in the MIS field effect transistor, by forming the second gate electrode 117, a parasitic capacitance generated between the first gate electrode 115 and the second gate electrode 117 becomes a load, and for example, an integrated circuit is integrated. When a circuit or the like is formed, there is a problem that the operation speed is reduced. Further, compared to a normal MIS type field effect transistor, it is necessary to form an extra contact and wiring for the second gate electrode 117, which causes an increase in element size and a decrease in the degree of freedom in wiring design. There is.
Hisao Kawamura, Toshisugu Sakamoto, Toshio Baba, Yukinori Ochiai, Jun'ich Fujita, and Jun'ich Sone, "IEEE TRANSACTION ON ELETRON DEVICES", USA (IEEE), Volume 47 (VOL.47), Issue 4 (NO.4), April 2000 (APRIL2000), P.856-860

  The present invention has been made to solve the above problems, and an object of the present invention is to manufacture a semiconductor device such as a MIS field effect transistor that can suppress a short channel effect without causing an increase in parasitic capacitance or element size, and its manufacture. It is to provide a method.

In order to achieve the above object, a semiconductor device according to a first invention includes a first conductivity type semiconductor substrate, a gate electrode formed on one main surface of the semiconductor substrate via a first insulating film, A source region and a drain region of a second conductivity type provided in a region not covered by the gate electrode on one main surface side of the semiconductor substrate; a channel region under the gate electrode; and a region sandwiched between the source regions And a second insulating film containing a fixed charge having a polarity different from that of carriers passing through the channel region on a region sandwiched between the channel region and the drain region, and including the fixed charge of the second insulating film The interface between the region and the semiconductor substrate is at a deeper position on the semiconductor substrate side than the interface between the first insulating film and the semiconductor substrate, and the first insulating film is the second insulating film. With a different composition I, and a said second diffusion hard film quality than impurities above a fixed charge second insulating film in the insulating film, the first contact with the region containing the fixed charge of the second insulating film An inversion layer is formed in the vicinity of the surface of the one conductivity type semiconductor substrate.

  In the present specification, the first conductivity type and the second conductivity type represent semiconductor conductivity types. When the second conductivity type is P type, the first conductivity type means N type or intrinsic (intrinsic semiconductor), and when the second conductivity type is N type, the first conductivity type means P type or intrinsic. To do.

  According to the semiconductor device having the above structure, the channel region is formed on the region sandwiched between the channel region and the source region under the gate electrode on the one main surface side of the semiconductor substrate and on the region sandwiched between the channel region and the drain region. A second insulating film containing a fixed charge having a polarity different from that of the carrier passing through the substrate. For this reason, band inversion occurs in the vicinity of the surface of the first conductivity type semiconductor below the region including the fixed charge of the second insulating film, whereby an inversion layer is formed, and extremely shallow source / drain extensions are formed. Further, the interface between the region including the fixed charge of the second insulating film and the semiconductor substrate is located closer to the semiconductor substrate than the interface between the first insulating film and the semiconductor substrate, thereby fixing the fixed charge. The distance between the gate electrode (particularly, the fixed charge near the interface between the second insulating film and the semiconductor substrate) and the gate electrode can be increased. For this reason, the electric lines of force extending from the region including the fixed charge of the second insulating film are hardly terminated at the gate electrode, can be terminated at the semiconductor substrate side, and a high carrier density inversion layer is formed. Is possible. Therefore, the inversion layer can function as a very shallow and low resistance source / drain extension.

  Further, since there is no need to add an extra electrode or the like to a normal MIS type field effect transistor, there is no increase in parasitic capacitance or an element area.

  Accordingly, it is possible to provide a semiconductor device such as a MIS field effect transistor in which the short channel effect is suppressed without causing an increase in parasitic capacitance or element size.

In one embodiment , when the cesium is used as the impurity that becomes the fixed charge and the carrier is an electron , the surface density of the fixed charge in the region including the fixed charge of the second insulating film is 5 It is characterized by being not less than 3 × 10 ¹² cm ^{−2 and not} more than 3 × 10 ¹⁴ cm ⁻² .

According to the semiconductor device of the above embodiment, when the semiconductor device is an N-type channel element using electrons as carriers, the surface density of the fixed charge in the region including the positive fixed charge of the second insulating film is 5 By setting it to 3 × 10 ¹² cm ⁻² or more and 3 × 10 ¹⁴ cm ⁻² or less, the sheet resistance of the inversion layer induced by the region including the positive fixed charge can be sufficiently reduced, and the driving current is extremely high. Can be obtained.

  In one embodiment, when the carrier is an electron, a part or all of the region including the fixed charge in the second insulating film includes cesium, barium, and rubidium as impurities that become the fixed charge. It is characterized by using at least one of the following.

  According to the semiconductor device of the above embodiment, when this semiconductor device is an N-type channel element, positive fixed charges are realized using at least one of cesium, barium, and rubidium.

  Since the above cesium, barium, and rubidium belong to alkali metals or alkaline earth metals, the first ionization energy is small and they tend to be ions having a positive charge. The cesium, barium, and rubidium have a large atomic number, unlike light elements such as sodium, which are easy to move even at room temperature, so that charges do not move in the normal device operating temperature region. Therefore, the above cesium, barium, and rubidium are extremely effective substances as impurities that become positive fixed charges. Further, at a high temperature, there is a property of diffusing in an insulating film such as a silicon oxide film, and a property of pile-up near an interface such as an interface between a silicon oxide and a semiconductor substrate. Therefore, by using thermal diffusion, the distribution of the fixed charges near the interface between the region including the fixed charges of the second insulating film and the semiconductor substrate is realized in a self-aligned manner. Therefore, it is very easy to distribute positive fixed charges at positions far from the gate electrode and very close to the semiconductor substrate.

  Moreover, since the cesium, barium, and rubidium can be introduced into the second insulating film using a general ion implantation apparatus as a semiconductor manufacturing apparatus, a special apparatus is not required and the implantation amount It is possible to easily manufacture a semiconductor device such as an N-type channel MIS type field effect transistor while precisely controlling.

In one embodiment of the present invention, when iodine is used as the impurity that becomes the fixed charge and the carrier is a hole, the area density of the region including the fixed charge of the second insulating film is 8 × 10 ^12. It is characterized by being cm ⁻² or more.

According to the semiconductor device of the above embodiment, when the semiconductor device is a P-type channel element using holes as carriers, the area density of the region including the negative fixed charge of the second insulating film is 8 × 10 ^12. By setting it to cm ⁻² or more, the sheet resistance of the inversion layer induced by the negative fixed charge can be sufficiently reduced, and a very high driving current can be obtained.

  In one embodiment, when the carrier is a hole, iodine is used as an impurity that becomes a fixed charge in part or all of the region including the fixed charge in the second insulating film. It is a feature.

  According to the semiconductor device of the above embodiment, when the semiconductor device is a P-type channel element using holes as carriers, negative fixed charges are realized using iodine.

  Since iodine is a halogen element belonging to Group VIIB of the periodic table, it has a high electron affinity and tends to be an ion having a negative charge. In addition, since the atomic number is large, unlike light elements such as fluorine and chlorine, which easily move at room temperature, charges do not move in the normal device operating temperature region. Therefore, the iodine is a substance that is extremely effective as a negative fixed charge, diffuses in an insulating film such as a silicon oxide film at a high temperature, and near the interface such as an interface between a silicon oxide and a semiconductor substrate. Has the property of pile-up. Therefore, by using thermal diffusion, the distribution of the fixed charges near the interface between the region including the fixed charges of the second insulating film and the semiconductor substrate is realized in a self-aligned manner. Therefore, it is very easy to distribute negative fixed charges at positions far from the gate electrode and very close to the semiconductor substrate.

  Since the iodine can be introduced into the second insulating film using a general ion implantation apparatus as a semiconductor manufacturing apparatus, a special apparatus is not required and the implantation amount is precisely controlled. A semiconductor device such as a P-type channel MIS field effect transistor can be easily manufactured.

  According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method for manufacturing the semiconductor device, wherein the semiconductor device is selectively formed on the first insulating film provided on one main surface of the semiconductor substrate. A step of forming a gate electrode; a step of forming a second insulating film in a region of the main surface of the semiconductor substrate that is not covered with the gate electrode by a chemical reaction with the semiconductor substrate; And the step of injecting an impurity which becomes a fixed charge into the insulating film.

  According to the method for manufacturing a semiconductor device, after a gate electrode is selectively formed on the first insulating film, a semiconductor substrate is formed in a region of the main surface of the semiconductor substrate that is not covered with the gate electrode. In order to form the second insulating film by a chemical reaction (for example, oxidation of the surface of the semiconductor substrate), the interface between the second insulating film and the semiconductor substrate is deeper than the interface between the first insulating film and the semiconductor substrate. It can be easily formed at the position (semiconductor substrate side).

  As a result, an inversion layer is formed by band bending near the semiconductor surface under the region including the fixed charge of the second insulating film, and extremely shallow source / drain extensions are formed. Furthermore, the lines of electric force extending from the region including the fixed charge in the second insulating film are hardly terminated at the gate electrode, can be terminated at the semiconductor substrate side, and a high carrier density inversion layer can be formed. It is.

  Therefore, it is possible to manufacture a semiconductor device such as a MIS field effect transistor in which the short channel effect is suppressed without causing an increase in parasitic capacitance or element size.

  In one embodiment, the method of manufacturing a semiconductor device includes an annealing step after the step of injecting impurities that become fixed charges into the second insulating film.

  According to the method of manufacturing a semiconductor device of the above embodiment, since the annealing is performed after the step of injecting impurities that become fixed charges into the second insulating film, the fixed charges are regenerated in the second insulating film. Distribution occurs, and fixed charges can be easily distributed in the vicinity of the interface between the second insulating film and the semiconductor substrate in a self-aligning manner.

  According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method for manufacturing the semiconductor device, wherein the semiconductor device is selectively formed on the first insulating film provided on one main surface of the semiconductor substrate. A step of forming a gate electrode; a step of forming a second insulating film in a region of the main surface of the semiconductor substrate that is not covered with the gate electrode by a chemical reaction with the semiconductor substrate; After forming the two insulating films, the method includes a step of exposing to an atmosphere containing at least one of nitrogen, nitric oxide, dinitrogen monoxide, ammonia, and nitrogen radicals.

  According to the method for manufacturing a semiconductor device, after the gate electrode is selectively formed on the first insulating film, the semiconductor substrate is formed in a region of the main surface of the semiconductor substrate that is not covered with the gate electrode. A second insulating film is formed by a chemical reaction with the substrate (for example, oxidation of the surface of the semiconductor substrate), and then exposed to an atmosphere containing at least one of nitrogen, nitrogen monoxide, dinitrogen monoxide, ammonia, and nitrogen radicals. As a result, nitrogen atoms are introduced into the second insulating film, particularly in the vicinity of the interface between the second insulating film and the semiconductor substrate, resulting from bond defects between atoms, such as silicon-nitrogen bonds, and strain. A fixed charge can be easily formed. In addition, since the second insulating film is formed by a chemical reaction with the semiconductor substrate, the interface between the second insulating film and the semiconductor substrate is positioned deeper than the interface between the first insulating film and the semiconductor substrate (semiconductor It can be easily formed on the substrate side).

  As a result, an inversion layer is formed by band bending near the semiconductor surface under the region including the fixed charge of the second insulating film, and extremely shallow source / drain extensions are formed. Furthermore, the lines of electric force extending from the region including the fixed charge in the second insulating film are hardly terminated at the gate electrode, can be terminated at the semiconductor substrate side, and a high carrier density inversion layer can be formed. It is.

  Therefore, it is possible to manufacture a semiconductor device such as a MIS field effect transistor in which the short channel effect is suppressed without causing an increase in parasitic capacitance or element size.

  Moreover, since it can be manufactured using a normal semiconductor manufacturing material and a semiconductor manufacturing apparatus, it can be manufactured very easily without problems with respect to contamination and the like.

  As is clear from the above, according to the semiconductor device and the manufacturing method thereof of the present invention, a semiconductor device such as a MIS field effect transistor capable of suppressing the short channel effect without causing an increase in parasitic capacitance or element size is provided. be able to.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments shown in the drawings.

  The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. Furthermore, an SOI (Semiconductor On Insulator) substrate or a strained silicon substrate in which carrier mobility is improved by applying strain to the silicon crystal may be used. In each embodiment, the description will focus on an N-type channel element using cesium as an impurity serving as a fixed charge. However, by reversing the conductivity type of the impurity and replacing cesium with iodine, the P-type channel element is changed. Can be formed. In the case of an N-type channel element, the same effect can be obtained even when barium or rubidium is used instead of cesium or a mixture containing at least two of these three is used. Of course, both types of elements may be formed on the same substrate, a complementary MIS (Metal insulator semiconductor) field effect transistor may be formed, or an integrated circuit may be formed.

(First embodiment)
In the semiconductor device according to the first embodiment of the present invention, an N-type channel MIS field effect transistor having a source / drain extension as an inversion layer induced by a fixed charge of cesium is realized by a simple process.

  1A to 1D are cross-sectional views of an N-type channel MIS field effect transistor as an example of a semiconductor device shown in the order of steps for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention. is there.

  First, as shown in FIG. 1A, an STI (Shallow Trench Isolation) region 2 is formed on one main surface of a P-type silicon substrate 1 as an example of a semiconductor substrate by a known method, and an element formation region is divided. . Next, a polycrystalline silicon film is deposited and patterned on the gate insulating film 3 made of silicon oxide as an example of the first insulating film provided on the surface of the element formation region, thereby forming the gate electrode 4. To do. Any material may be used for the gate insulating film 3 as long as it has an insulating property, but it is desirable that the material (such as cesium) that becomes a fixed charge hardly diffuses, such as silicon oxynitride or silicon nitride.

  Next, a silicon oxide film 5 as an example of a second insulating film is formed by a chemical reaction that oxidizes the entire surface of the silicon substrate. The interface between the silicon oxide film 5 and the silicon substrate 1 is formed at a position deeper than the interface between the gate insulating film 3 and the silicon substrate 1. The film thickness of the silicon oxide film 5 is preferably larger than the film thickness of the gate insulating film 3. Thus, when an impurity (cesium or the like) that becomes a fixed charge in the silicon oxide film 5 is thermally diffused in a later process, the gate insulating film viewed from the silicon oxide film 5 side containing the impurity that becomes the fixed charge. Since the cross-sectional area of 3 becomes small, it is possible to suppress the impurity that becomes the fixed charge from entering the gate insulating film 3. Therefore, it is possible to easily control the distribution of impurities (such as cesium) that become fixed charges.

  The silicon oxide film 5 is formed by thermally oxidizing the silicon substrate 1. For example, after the silicon substrate 1 is thermally oxidized, silicon oxide is deposited by a CVD (Chemical Vapor Deposition) method or the like. A laminated film may be deposited. Thereby, the film thickness of the silicon oxide film 5 and the depth of the interface between the silicon oxide film 5 and the silicon substrate 1 can be controlled independently.

  Next, as shown in FIG. 1B, after a resist is applied to the surface of the silicon substrate, the STI region 2 is covered, and at least the region where the source / drain extension is to be formed in the element formation region is opened. The resist mask 6 is formed by patterning the resist in this manner. Thereafter, cesium ions are implanted into the silicon oxide film 5 using the gate electrode 4 and the resist mask 6 as a mask. Since the first ionization energy is very small, the cesium can exist stably as an ion having a positive charge. Therefore, a region 7 containing positive fixed charges made of cesium is formed in the silicon oxide film 5. Note that barium or rubidium may be used instead of cesium, or at least two of cesium, barium, and rubidium may be used.

  Band bending occurs on the surface of the silicon substrate 1 under the region 7 containing the positive fixed charge due to the electric field generated from the region 7 containing the positive fixed charge. When the potential of the surface of the silicon substrate 1 reaches about twice the difference between the Fermi potential and the intrinsic Fermi potential of the silicon substrate 1, an inversion layer is formed on the surface of the silicon substrate 1 under the region 7 containing positive fixed charges. Is done. The inversion layer functions as a source / drain extension.

  Further, a silicon nitride film may be formed on the entire surface of the silicon substrate before the ion implantation. By forming a silicon nitride film before injecting an impurity (cesium or the like) that becomes a fixed charge into the silicon oxide film 5, the impurity is applied to the silicon substrate 1 by a heat treatment or the like in a process after the impurity is injected. Heat diffusion to the opposite side. The silicon nitride film may be made of any material that does not diffuse impurities such as cesium. In this case, since the cesium ions are ion-implanted into the silicon oxide film 5 through the silicon nitride film, the film thickness of the silicon nitride film is ½ or less of the film thickness of the silicon oxide film 5. Is preferred. For example, when the silicon oxide film 5 has a thickness of 350 to 500 mm, the silicon nitride film has a thickness of 100 mm and the implantation energy of cesium ions is about 30 to 50 keV, so that the cesium ions are approximately near the center in the film thickness direction of the silicon oxide film 5. Can be distributed.

  Next, as shown in FIG. 1 (c), after removing the resist mask 6 (shown in FIG. 1 (b)), a silicon oxide film is desired by a CVD (Chemical Vapor Deposition) method. The gate sidewalls 8 are formed on both sides of the gate electrode 4 so as to cover a part of the region 7 including the fixed charge by depositing the thickness of the gate electrode 4 and etching back by RIE (Reactive Ion Etching). . However, any material may be used for the silicon oxide film as long as it has an insulating property, but a material such as silicon oxynitride or silicon nitride that prevents diffusion of impurities (such as cesium) serving as a fixed charge is preferable. Thereafter, arsenic ions are ion-implanted using the gate electrode 4 and the gate sidewall 8 as a mask to form the source region 9 and the drain region 10 shown in FIG. 1D, and then activation annealing is performed. As a result, cesium diffuses in the silicon oxide film 5, piles up near the interface between the silicon oxide film 5 and the silicon substrate 1, and can distribute the fixed charges closer to the surface of the silicon substrate 1. Therefore, cesium can be efficiently activated as a fixed charge, and an inversion layer having a sufficient carrier density can be formed.

  Further, as shown in FIG. 1C, since the interface between the silicon oxide film 5 and the silicon substrate 1 is deeper than the interface between the gate insulating film 3 and the silicon substrate 1, the fixed charge is transferred to the gate electrode 4. It can be distributed at a position away from the silicon substrate 1 and close to the silicon substrate 1. As a result, the capacitance between the gate electrode and the fixed charge can be reduced, so that the lines of electric force extending from the fixed charge hardly end at the gate electrode 4 and effectively end on the silicon substrate 1 side. It becomes possible. Therefore, a source / drain extension composed of a low resistance inversion layer can be formed.

  Moreover, since the electrostatic capacitance between the inversion layer induced by the fixed charge and the gate electrode 4 is reduced, the parasitic capacitance is reduced, and the device operation speed can be improved.

  The activation annealing is preferably high-temperature short-time annealing such as RTA (Rapid Thermal Annealing), spike annealing, flash lamp annealing, or laser annealing. For example, annealing is performed at 800 ° C. to 1100 ° C. for about 1 second to 180 seconds. In addition to the activation annealing, annealing for promoting redistribution of cesium may be performed before the source region 9 and the drain region 10 are formed and after ion implantation of cesium into the silicon oxide film 5. For example, cesium can be sufficiently diffused by annealing at 700 ° C. to 1100 ° C. for about 1 second to 2 hours.

  Next, as shown in FIG. 1D, the interlayer insulating film 11, the upper wiring 12, and the like are formed by a known method, thereby completing the semiconductor device.

FIG. 2 shows the electrical characteristics of the semiconductor device (N-type channel element) of the first embodiment prepared with a gate length of 35 nm, a silicon oxide equivalent film thickness of 1 nm, and a cesium dose of 3 × 10 ¹³ cm ^−2. Indicates. In FIG. 2, the horizontal axis represents the gate voltage [V], and the vertical axis represents the drain terminal current [A / μm]. The drain voltage was 1 V, and the on-current at that time was 1.2 mA / μm. As can be seen from FIG. 2, very good transistor characteristics could be obtained.

  Further, as can be seen from FIG. 1 (d), the semiconductor device of the first embodiment of the present invention has a silicon oxide film 5 between the channel region covered with the gate electrode 4 and the source region 9 and the drain region 10. A region 7 containing a positive fixed charge made of cesium is included therein.

  Cesium is large in mass with atomic number 55, and has the lowest first ionization energy (3.89 eV) in the periodic table. Therefore, in the normal device operating temperature region, the insulation of a silicon oxide film or the like is used. It does not move in the film and can exist stably as positively charged ions. Therefore, it can exist very stably as a positive fixed charge in the insulating film. Similar effects can be obtained with barium and rubidium.

  Band bending occurs on the surface of the silicon substrate 1 below the region 7 containing the positive fixed charge due to the electric field generated from the region 7 containing the positive fixed charge, and the surface of the silicon substrate 1 below the region 7 containing the positive fixed charge. An inversion layer is formed. Since the inversion layer is formed between the channel region and the source region 9 and between the channel region and the drain region 10, it functions as a very shallow source / drain extension.

κ ： 基板の比誘電率
ε ： 真空の誘電率[Ｆ／ｃｍ]
Ｎ_A ： 空乏層中のアクセプター濃度[ｃｍ^-3]
Ｎ_D ： 空乏層中のドナー濃度[ｃｍ^-3]
ｑ ： 電荷素量[Ｃ]
φ_B ： ２（ｋ_BＴ／ｑ)ln（|Ｎ_A-Ｎ_D|／Ｎ_i)
Ｎ_i ： 真性キャリア濃度[ｃｍ^-3]
ｋ_B ： ボルツマン定数[ｅＶ／Ｋ]
Ｔ ： 温度[Ｋ]
Ｖ_R ：シリコン基板−ソース領域９間にかかる逆バイアス電圧(＞０)[Ｖ]
（チャネル領域−ソース領域９間の反転層の場合）
または、シリコン基板−ドレイン領域１０間にかかる逆バイアス電圧（＞０）[Ｖ]
（チャネル領域−ドレイン領域１０間の反転層の場合）
よりも大きいことが必要である。例えば、チャネル領域−ソース領域９間に反転層を形成するためには、Ｖ_R=０[Ｖ]、|Ｎ_A-Ｎ_D|＝１×１０¹⁸[ｃｍ^-3]の場合(Ｎ_A＞Ｎ_D)、固定電荷密度は３.５×１０¹²[ｃｍ^-2]以上必要である。
また、固定電荷によって誘起される反転層のシート抵抗は、低ければ低いほど素子特性は向上する。固定電荷密度が大きいほど反転層として誘起されるキャリア密度は上昇するが、逆に基板表面に対して垂直方向の電界が大きくなるため、キャリア移動度の劣化が起こる。このため、シート抵抗を低くするために最適な固定電荷密度が現われる。 However, in order to form the inversion layer, for example, when the impurity concentration in the depletion layer formed in the silicon substrate 1 by the fixed charge is uniform, the fixed charge density is

κ: dielectric constant of the substrate
ε: dielectric constant of vacuum [F / cm]
N _A : Acceptor concentration in the depletion layer [cm ^-3 ]
N _D : Donor concentration in the depletion layer [cm ^-3 ]
q: Elementary charge [C]
_{φ B: 2 (k B T} / q) ln (| N A -N D | / N i)
_Ni : Intrinsic carrier concentration [cm ^-3 ]
k _B : Boltzmann constant [eV / K]
T: Temperature [K]
V _R : Reverse bias voltage (> 0) [V] applied between the silicon substrate and the source region 9
(In the case of an inversion layer between the channel region and the source region 9)
Alternatively, the reverse bias voltage (> 0) [V] applied between the silicon substrate and the drain region 10
(In the case of an inversion layer between the channel region and the drain region 10)
Must be greater than For example, in order to form an inversion layer between the channel region and the source region 9, V _R = 0 [V], | N _A -N _D | = 1 × 10 ¹⁸ [cm ⁻³ ] (N _A > N _D ) and a fixed charge density of 3.5 × 10 ¹² [cm ⁻² ] or more is required.
Further, the lower the sheet resistance of the inversion layer induced by the fixed charge, the better the device characteristics. The carrier density induced as the inversion layer increases as the fixed charge density increases, but conversely, the electric field in the direction perpendicular to the substrate surface increases, so that the carrier mobility deteriorates. For this reason, an optimum fixed charge density appears to lower the sheet resistance.

FIG. 3 shows the measurement result of the fixed charge density dependence of the sheet resistance of the inversion layer induced by the positive fixed charge made of cesium. In FIG. 3, the horizontal axis represents the positive fixed charge (cesium) density [cm ⁻² ], and the vertical axis represents the sheet resistance [Ω / □] of the inversion layer. The sample used for the measurement was prepared as follows. First, a P-type silicon substrate (substrate concentration: 1 × 10 ¹⁸ cm ⁻³ ) is thermally oxidized to form a silicon oxide film (350 mm), and a silicon nitride film is formed thereon by LP-CVD (low pressure CVD). After forming (100 cm), cesium was ion-implanted at 40 keV and annealed in a nitrogen atmosphere. The amount of cesium activated as a fixed charge substantially coincided with the amount of cesium in the silicon oxide film distributed within about 50 cm from the interface between the silicon oxide film and the silicon substrate. As can be seen from FIG. 3, under a certain substrate concentration condition, the sheet resistance of the inversion layer induced by the fixed charge becomes a minimum value at a certain fixed charge density. For example, when the substrate concentration is 1 × 10 ¹⁸ [cm ⁻² ], the fixed charge density is set to 5.3 × 10 ¹² cm ⁻² or more and 3 × 10 ¹⁴ cm ⁻² or less to 10 [kΩ / □ The following low sheet resistance values can be obtained. More preferably, a sufficiently small sheet resistance value can be obtained by setting it to 1 × 10 ¹³ cm ⁻² or more and 3 × 10 ¹³ cm ⁻² or less, and accordingly, the driving current of the N-type channel MIS type field effect transistor Can be very large.
Similarly, fixed charges with a sheet resistance of the inversion layer of 10 kΩ / □ or less as a result of measurement using a P-type silicon substrate with a substrate concentration of 1.2 × 10 ¹⁶ cm ⁻³ and 1.1 × 10 ¹⁹ cm ^−3. The density is 1.3 × 10 ¹² cm ⁻² or more and 3.0 × 10 ¹⁴ cm ⁻² or less (substrate concentration: 1.2 × 10 ¹⁶ cm ⁻³ ), 2.3 × 10 ¹³ cm ⁻² or more, respectively. In addition, it was 3.0 × 10 ¹⁴ cm ⁻² or less (substrate concentration: 1.1 × 10 ¹⁹ cm ⁻³ ).

ただし κ ： 基板の比誘電率
ε ： 真空の誘電率[Ｆ／ｃｍ]
Ｎ_A ： アクセプター濃度[ｃｍ^-3]
Ｎ_D ： ドナー濃度[ｃｍ^-3]
ｑ ： 電荷素量[Ｃ]
φ_B ： ２(ｋ_BＴ／q)ln(Ｎ_A／Ｎ_i)
Ｎ_i ： 真性キャリア濃度[ｃｍ^-3]
ｋ_B ： ボルツマン定数[ｅＶ／Ｋ]
Ｔ ： 温度[Ｋ]
Ｖ_R ： シリコン基板−ソース領域間にかかる逆バイアス電圧(＞０)[Ｖ]
(またはシリコン基板−ドレイン領域間にかかる逆バイアス電圧)
よりも大きいことが必要である。例えば、チャネル領域−ソース領域９間に反転層を形成するためには、Ｖ_R＝０[Ｖ]、｜Ｎ_A−Ｎ_D｜＝１×１０¹⁸[ｃｍ^-3]の場合(Ｎ_A＜Ｎ_D)、固定電荷密度は３.５×１０¹²[ｃｍ^-2]以上必要である。 In the case of a P-type channel element, the polarity of the fixed charge becomes negative by replacing the cesium with iodine. In this case, in order to form the inversion layer, when the impurity concentration in the depletion layer formed by the fixed charge is uniform,
Fixed charge density is

Where κ is the dielectric constant of the substrate
ε: dielectric constant of vacuum [F / cm]
N _A : Acceptor concentration [cm ^-3 ]
N _D : Donor concentration [cm ^-3 ]
q: Elementary charge [C]
_{φ B: 2 (k B T} / q) ln (N A / N i)
_Ni : Intrinsic carrier concentration [cm ^-3 ]
k _B : Boltzmann constant [eV / K]
T: Temperature [K]
V _R : Reverse bias voltage (> 0) [V] applied between the silicon substrate and the source region
(Or reverse bias voltage between silicon substrate and drain region)
Must be greater than For example, in order to form an inversion layer between the channel region and the source region 9, in the case of V _R = 0 [V], | N _A −N _D | = 1 × 10 ¹⁸ [cm ⁻³ ] (N _A < N _D ) and a fixed charge density of 3.5 × 10 ¹² [cm ⁻² ] or more is required.

FIG. 4 shows the measurement result of the fixed charge density dependence of the sheet resistance of the inversion layer induced by the negative fixed charge made of iodine. In FIG. 4, the horizontal axis represents the negative fixed charge (iodine) density [cm ⁻² ], and the vertical axis represents the sheet resistance [Ω / □] of the inversion layer. The sample used for the measurement was prepared as follows. First, an N-type silicon substrate (substrate concentration: 1 × 10 ¹⁸ cm ⁻³ ) is thermally oxidized to form a silicon oxide film (350 mm), and a silicon nitride film is formed thereon by LP-CVD (low pressure CVD). After forming (100 cm), iodine was ion-implanted at 40 keV and annealing was performed in a nitrogen atmosphere. The amount of iodine activated as a fixed charge almost coincided with the amount of iodine in the silicon oxide film distributed within about 50 mm from the interface between the silicon oxide film and the silicon substrate. As can be seen from FIG. 4, by setting the fixed charge density to 8 × 10 ¹² cm ⁻² or more, a low sheet resistance value of 20 [kΩ / □] or less can be obtained. More preferably, a substantially minimum sheet resistance can be obtained by setting the fixed charge density to 1 × 10 ¹⁴ cm ⁻² or more. Therefore, the drive current of the P-type channel MIS type field effect transistor can be increased. Similarly, fixed charges with a sheet resistance of the inversion layer of 20 kΩ / □ or less as a result of measurement using an N-type silicon substrate with a substrate concentration of 1.2 × 10 ¹⁶ cm ⁻³ and 1.1 × 10 ¹⁹ cm ^−3. The densities were 3.0 × 10 ¹² cm ⁻² or more and 2.2 × 10 ¹³ cm ⁻² or more, respectively.

  When a strained silicon substrate is used instead of the silicon substrate 1, the sheet resistance is further reduced due to the effect of increasing carrier mobility, and a larger driving current can be obtained.

  Further, as can be seen from FIG. 1 (d), the semiconductor device of the first embodiment of the present invention has the interface between the silicon oxide film 5 and the silicon substrate 1 more than the interface between the gate insulating film 3 and the silicon substrate 1. Although it is formed at a deep position, the superiority of this structure will be described with reference to FIGS. 5 (a) and 5 (b).

Consider a situation where an inversion layer is formed by a fixed charge. FIG. 5A shows an enlarged view of the vicinity of the end of the gate electrode 4 on the source region side. The capacitance between the gate electrode 4 and the fixed charge 18 is C ₁ [F / cm ² ], and the effective capacitance between the fixed charge 18 and the inversion layer 19 is C ₂ [F / cm ^2]. ], An equivalent circuit diagram reaching the gate electrode 4, the fixed charge 18, and the silicon substrate 1 is represented as shown in FIG. However, the potential of the gate electrode 4 is V [V], and the potential of the silicon substrate 1 is 0 [V]. The film thickness (silicon oxide equivalent film thickness) of the gate insulating film 3 is t _ox [cm], the effective distance (silicon oxide equivalent film thickness) between the fixed charge 18 and the inversion layer 19 is t _inv [cm], and gate insulation Assuming that the depth of the interface between the silicon oxide film 5 and the silicon substrate 1 viewed from the interface between the film 3 and the silicon substrate 1 is d [cm], in the vicinity of the end of the gate electrode 4 on the source region side, It is expressed in
C ₁ = κ _SiO2 ε / (t _ox + d)
C ₂ = κ _SiO2 ε / t _inv
However, κ _SiO2 : Dielectric constant of silicon oxide
ε: dielectric constant of vacuum [F / cm ² ]

κ_Si：シリコン基板１の比誘電率 Here, the fixed charge density is + Q _FC [C / cm ² ], the charge density induced in the gate electrode 4 is −Q ₁ [C / cm ² ], and the charge density induced on the silicon substrate 1 side is −Q _2. [C / cm ² ], the charge density of the inversion layer 19 is Q _inv [C / cm ² ], the voltage applied to the gate electrode 4 is V [V], the potential of the fixed charge 18 is V _FC [V], the gate When the flat band voltage of the electrode 4 is V _FB (<0) [V], the following equation is established.
Q _FC = Q ₁ + Q ₂
Q ₁ = C ₁ (V _FC −V + V _FB )
Q ₂ = Q _inv + Q _B
Q _inv = C ₂ (V _FC -2φ _B )
However, Q _B [C / cm ² ] is a space charge density in the depletion layer 20 and is expressed as follows.

κ _Si : dielectric constant of silicon substrate 1

From the above equation, Q _inv is expressed as follows.
Q _inv = [C ₂ / (C ₁ + C ₂ )] [Q _FC + C ₁ (V−V _FB −2φ _B −Q _B / C ₁ )]
Here, C ₁ (V−V _FB −2φ _B −Q _B / C ₁ ) corresponds to the charge density generated by the electric field leaking from the gate electrode 4, but the inversion layer 19 induced by the fixed charge 18 is used as the source. When used as a drain extension, the charge density of the inversion layer 19 is
C ₁ (V−V _FB −2φ _B −Q _B / C ₁ )
It is preferable to take a sufficiently large value. In this case, the fixed charge density QFC is sufficiently large.
If Q _FC is large enough,
Q _inv = [C ₂ / (C ₁ + C ₂ )] Q _FC
Can be approximated. Therefore, by reducing C _1, that is, by increasing d, the inversion layer 19 can be formed efficiently, and a larger inversion layer charge density Q _inv can be obtained.

As can be seen from the above, by forming the interface between the silicon oxide film 5 and the silicon substrate 1 at a position deeper than the interface between the gate insulating film 3 and the silicon substrate 1, the gap between the gate electrode 4 and the fixed charge 18 is obtained. The capacitance C ₁ can be reduced, the formation of the efficient inversion layer 19 in the vicinity of the end of the gate electrode 4 can be realized, and the device performance can be improved.
For example, when designing with C ₁ / C ₂ = 1/5,
d = 5t _inv −t _ox
And it is sufficient. For example, when t _ox = 1 [nm] and t _inv = 0.5 [nm], d = 1.5 [nm] may be set.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention is an N-type channel MIS field effect transistor having a source / drain extension as an inversion layer induced by a fixed charge derived from bond defects between atoms, strain, and the like. It is realized by the process.

  6A to 6D are cross-sectional views of an N-type channel MIS field effect transistor as an example of a semiconductor device shown in the order of steps for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention. is there.

  First, as shown in FIG. 6A, an STI (Shallow Trench Isolation) region 2 is formed on one main surface of a P-type silicon substrate 1 as an example of a semiconductor substrate by a known method, and an element formation region is divided. . Next, a gate electrode 4 is formed by depositing and patterning a polycrystalline silicon film on the gate insulating film 3 made of silicon oxide provided on the surface of the element formation region. The material of the gate insulating film 3 may be anything as long as it has insulating properties, but may be a material such as silicon oxynitride or silicon nitride in which impurities (cesium or the like) that become fixed charges are difficult to diffuse.

  Next, a silicon oxide film 5 is formed by a chemical reaction that oxidizes the entire surface of the silicon substrate. The interface between the silicon oxide film 5 and the silicon substrate 1 is formed at a position deeper than the interface between the gate insulating film 3 and the silicon substrate 1.

  Next, as shown in FIG. 6B, annealing is performed at 1080 ° C. for 300 seconds in an ammonia atmosphere. The annealing conditions may be, for example, 900 ° C. or higher and 1100 ° C. or lower, and 5 seconds or longer and 1000 seconds or shorter. As a result, a silicon oxynitride film 13 is formed as an example of a second insulating film in which nitrogen atoms are introduced into the silicon oxide film 5 and low-density fixed charges are generated. The nitrogen concentration in the silicon oxynitride film 13 near the interface with the silicon substrate 1 is preferably 10 atom% or more. Next, annealing is performed in a nitrogen atmosphere at 1080 ° C. for 300 seconds. As a result, the fixed charge increases, and a fixed charge having a density sufficient to form the inversion layer can be generated. The details of the cause of the increase in the fixed charge density are unknown, but are thought to be derived from bond defects, strain, etc. between silicon-nitrogen, silicon-oxygen, nitrogen-oxygen, and the like.

  As a result, positive fixed charges are generated, and an inversion layer is formed on the surface of the silicon substrate 1 between the channel region and the source region and between the channel region and the drain region.

  The ammonia may be nitrogen, nitric oxide, dinitrogen monoxide, or a nitrogen radical.

  Further, at least one of cesium, barium, and rubidium may be introduced into the silicon oxide film 5 by an ion implantation method or the like.

  Next, as shown in FIG. 6C, a silicon oxide film is deposited to a desired thickness by a CVD (Chemical Vapor Deposition) method, and RIE (Reactive Ion Etching) is performed. Etchback is performed to form gate sidewalls 8 on both sides of the gate electrode 4. However, the gate sidewall 8 may be made of any material as long as it has an insulating property, but a material such as silicon oxynitride or silicon nitride that prevents diffusion of impurities (cesium or the like) that becomes a fixed charge is preferable. Thereafter, arsenic ions are ion-implanted using the gate electrode 4 and the gate sidewall 8 as a mask to form the source region 9 and the drain region 10, and then activation annealing is performed.

  The activation annealing is preferably high-temperature short-time annealing such as RTA (Rapid Thermal Annealing). Of course, the arsenic ions may be implanted species serving as donors such as phosphorus and antimony. Salicide may be formed after the activation annealing.

  Next, as shown in FIG. 6D, the interlayer insulating film 11, the upper wiring 12, and the like are formed by a known method to complete the semiconductor device.

  The semiconductor device according to the second embodiment of the present invention is positively fixed in the silicon oxynitride film 13 between the channel region covered by the gate electrode 4 and the source region 9 and between the channel region and the drain region 10. It has the area | region 17 containing an electric charge. Band bending occurs on the surface of the silicon substrate 1 below the region 17 including the positive fixed charge due to the electric field generated from the region 17 including the positive fixed charge, and the surface of the silicon substrate 1 below the region 17 including the positive fixed charge. An inversion layer is formed. Since the inversion layer is formed between the channel region and the source region 9 and the drain region 10, it functions as a very shallow source / drain extension.

FIG. 1 is a diagram for explaining the procedure of a method of manufacturing an N-type channel MIS field effect transistor as an example of the semiconductor device according to the first embodiment of the invention. FIG. 2 is a diagram showing the electrical characteristics of the semiconductor device (N-type channel element). FIG. 3 is a diagram showing the fixed charge density dependence of the inversion layer sheet resistance induced by the positive fixed charge generated using cesium. FIG. 4 is a diagram showing the fixed charge density dependence of the inversion layer sheet resistance induced by the negative fixed charge generated using iodine. FIG. 5 (a) is an enlarged view of the vicinity of the gate electrode end on the source side of the semiconductor device according to the first embodiment of the present invention, and FIG. 5 (b) is a diagram showing an equivalent circuit of FIG. 5 (a). It is. FIG. 6 is a diagram for explaining the procedure of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view of a conventional MIS field effect transistor having a second gate electrode on the side wall of the gate electrode.

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... STI area | region 3 ... Gate insulating film 4 ... Gate electrode 5 ... Silicon oxide film 6 ... Resist mask 7,17 ... Area | region containing positive fixed electric charge 8 ... Gate side wall 9 ... Source area 10 ... Drain area | region 11 ... Interlayer insulating film 12 ... Upper wiring 13 ... Silicon oxynitride film 18 ... Fixed charge 19 ... Inversion layer 20 ... Depletion layer 101 ... Silicon substrate 109 ... Source region 110 ... Drain region 114 ... First gate insulating film 115 ... First Gate electrode 116 ... second gate insulating film 117 ... second gate electrode

Claims (8)

A first conductivity type semiconductor substrate;
A gate electrode formed on one main surface of the semiconductor substrate via a first insulating film;
A source region and a drain region of a second conductivity type provided in a region not covered with the gate electrode on one main surface side of the semiconductor substrate;
A second charge containing a fixed charge having a polarity different from that of a carrier passing through the channel region, on a region sandwiched between the channel region and the source region under the gate electrode and on a region sandwiched between the channel region and the drain region. Insulating film
The interface between the region including the fixed charge of the second insulating film and the semiconductor substrate is located deeper on the semiconductor substrate side than the interface between the first insulating film and the semiconductor substrate,
The first insulating film has a composition different from that of the second insulating film, and a film quality in which impurities serving as fixed charges in the second insulating film are less likely to diffuse than the second insulating film. And
A semiconductor device, wherein an inversion layer is formed in the vicinity of the surface of the semiconductor substrate of the first conductivity type in contact with the region containing the fixed charge of the second insulating film. The semiconductor device according to claim 1,
Using cesium as an impurity that becomes the fixed charge,
When the carrier is an electron, the surface density of the fixed charge in the region including the fixed charge of the second insulating film is 5.3 × 10 ¹² cm ⁻² or more and 3 × 10 ¹⁴ cm ⁻² or less. A semiconductor device characterized by the above. The semiconductor device according to claim 1 ,
When the carrier is an electron, at least one of cesium, barium, and rubidium is used as an impurity that becomes a fixed charge in part or all of the region including the fixed charge of the second insulating film. A semiconductor device. The semiconductor device according to claim 1,
Using iodine as an impurity that becomes the fixed charge,
When the carrier is a hole, a surface density of a region including a fixed charge of the second insulating film is 8 × 10 ¹² cm ⁻² or more. The semiconductor device according to claim 1 or 4,
A semiconductor device, wherein when the carrier is a hole, iodine is used as an impurity which becomes a fixed charge in a part or all of a region including the fixed charge of the second insulating film. A semiconductor device manufacturing method for manufacturing the semiconductor device according to claim 1,
Selectively forming a gate electrode on the first insulating film provided on one main surface of the semiconductor substrate;
Forming a second insulating film by a chemical reaction with the semiconductor substrate in a region of the main surface of the semiconductor substrate that is not covered with the gate electrode;
And a step of injecting an impurity which becomes a fixed charge into the second insulating film. In the manufacturing method of the semiconductor device according to claim 6,
A method of manufacturing a semiconductor device, comprising an annealing step after the step of injecting impurities that become fixed charges into the second insulating film. A semiconductor device manufacturing method for manufacturing the semiconductor device according to claim 1,
Selectively forming a gate electrode on the first insulating film provided on one main surface of the semiconductor substrate;
Forming a second insulating film by a chemical reaction with the semiconductor substrate in a region of the main surface of the semiconductor substrate that is not covered with the gate electrode;
A method of manufacturing a semiconductor device, comprising the step of exposing to an atmosphere containing at least one of nitrogen, nitrogen monoxide, dinitrogen monoxide, ammonia, and nitrogen radicals after forming the second insulating film. .

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