CN100334740C - Power MOSFET and its mfg. method - Google Patents
Power MOSFET and its mfg. method Download PDFInfo
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- CN100334740C CN100334740C CNB031577989A CN03157798A CN100334740C CN 100334740 C CN100334740 C CN 100334740C CN B031577989 A CNB031577989 A CN B031577989A CN 03157798 A CN03157798 A CN 03157798A CN 100334740 C CN100334740 C CN 100334740C
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Abstract
The present invention relates to a power metal oxide semiconductor field effect transistor (MOSFET) and a manufacture method thereof. A polysilicon Ge gate electrode is used for substituting for a polysilicon gate electrode in a double-diffused transistor of the existing trench. A base material of a first conducting type is first provided, a built crystal layer of the first conducting type is formed on the base material, and a main body area of a second conducting type is formed on the built crystal layer. Then, the main body area and the built crystal layer are etched to form a trench. An insulation layer is formed at the surface of the trench to be used as a liner of the trench. Successively, a source electrode area of the first conducting type is formed in a position adjacent to the trench in the main body area. Finally, a polysilicon Ge material is deposited in the trench to be used as a gate electrode of a double-diffused transistor of the trench.
Description
Technical field
The invention relates to a kind of manufacture method of mos field effect transistor, particularly relevant for a kind of manufacture method with power metal oxide semiconductor field-effect transistor of irrigation canals and ditches structure.
Background technology
Double-diffused transistor (double diffused MOS, DMOS) be a kind of mos field effect transistor (metal oxide semiconductor field effect transistor, MOSFET), it utilizes diffusion to form transistor area.Double-diffused transistor is used as the power transistor that is used for high-tension power integrated circuit usually, under the requirement of low forward pressure drop, provides higher per unit area electric current.
One particular type of double-diffused transistor is a so-called irrigation canals and ditches double-diffused transistor (trench DMOStransistor) 100, as shown in Figure 1.The gate 104 of irrigation canals and ditches double-diffused transistor 100 is to be formed in the irrigation canals and ditches 116, and the drain source current Ids 122 of this irrigation canals and ditches double-diffused transistor 100 transmits along its channel vertical ground.These irrigation canals and ditches 116 are to extend between source electrode 106 and drain 108, and the surface of irrigation canals and ditches 116, and is filled in wherein with polysilicon 114 as liner by coating one thin oxide layer 112.The gate 104 of filling polysilicon 114 can make this irrigation canals and ditches double-diffused transistor 100 allow less limitation electric current (constricted current), therefore can provide lower conduction resistance (specific on-resistance) value.The relevant patent of irrigation canals and ditches double-diffused transistor is disclosed in United States Patent (USP) the 5th, 072, and 266,5,541,425 and 5,866, in No. 931.
Existing irrigation canals and ditches double-diffused transistor 100 has one and runs through (punch-through) problem.Running through problem takes place when transistorized passage is vague and general usually and presents early than avalanche breakdown (avalanche breakdown) with a nondestructive leakage current form.In causing the various causes that run through problem, the most serious cause is exactly to occur in the forming process of irrigation canals and ditches gate 104, and occurs in sacrificial oxidation processing and oxide skin(coating) subsequently (as the oxide skin(coating) among Fig. 1 112) deposition process in this forming process especially easily.
In addition, when power transistor is operated under high voltage, as the operating voltage that works the power transistor that drives function in the LCD usually more than 30 volts, so high magnitude of voltage makes the dopant penetration oxide skin(coating) in the gate enter body region, causes carrier to penetrate (carrier penetration) and the problem of polycrystalline vague and general (poly depletion).Carrier penetrates the carrier concentration that can significantly reduce in the passage, and the vague and general meeting of polycrystalline increases the brake-pole dielectric layer thickness of equivalence, causes the actuating force of minimizing of gate capacitance and gate to fail thereupon.
In the sacrificial oxidation of under hot conditions, the carrying out processing, the alloy in the passage of adjacent trenches 116, the boron in the P type doped body zone 102 for example, the oxide skin(coating) 112 that can from silicon, emanate and come out and enter gate.In addition, carrying out deposit spathic silicon 114 when filling the deposition process of irrigation canals and ditches 116, also can run through problem.Alloy in the polysilicon 114 is generally phosphorus, and the high temperature when understanding because of deposition passes gate 104 and enters P type doped body zone 102, so the problem that also can cause carrier to penetrate.
United States Patent (USP) the 5th, 072 discloses a kind of procedure of processing of producing the irrigation canals and ditches double-diffused transistor in No. 266.In this processing, P type doped body zone and source region are to form before irrigation canals and ditches form.Yet as previously mentioned, in the process that irrigation canals and ditches form, the boron in the P type doped body zone still can be emanated from silicon and be come out and enter the gate oxide layer, like this, above-mentioned run through problem and still can exist.In addition, when after use the processing of above-mentioned oxidate when continuing to finish the formation of irrigation canals and ditches, the silicon among the source region can produce defective, and this source region is produced bad influence.
United States Patent (USP) the 5th, 468, in No. 982 then at the irrigation canals and ditches gate etched and fill after form P type doped body zone again so that reduce the influence that runs through problem.Yet this method still is not very satisfactory.Because it uses the diffusing step (being generally 1100 to 1150 ℃) of a high temperature to form P type doped body zone, enter P type doped body zone and this high temperature can make alloy among the polysilicon that is used for filling irrigation canals and ditches pass gate as described above, so still cause the above-mentioned problem that runs through.
United States Patent (USP) the 6th, 518 discloses a kind of procedure of processing of irrigation canals and ditches double-diffused transistor of producing in No. 621 to reduce the above-mentioned problem that runs through.This procedure of processing is to be used for before the shade of irrigation canals and ditches removing, and finishes the forming process of irrigation canals and ditches earlier, so can utilize shade as a barrier layer, prevents from that alloy in the P type doped body zone from emanating to come out and enter among the gate oxide layer from silicon.But after forming irrigation canals and ditches, this procedure of processing still can produce when filling irrigation canals and ditches at deposit spathic silicon and run through problem, can't avoid alloy in the polysilicon because deposition or the high temperature when operating afterwards, and pass gate and enter P type doped body zone.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of power metal oxide semiconductor field-effect transistor, have the low double-diffused transistor that runs through problem generation probability in order to production.
According to above-mentioned purpose of the present invention, the present invention proposes a kind of manufacture method of power metal oxide semiconductor field-effect transistor.The present invention utilizes a polycrystalline silicon germanium gate to replace the polycrystalline silicon gate pole that has now in the irrigation canals and ditches double-diffused transistor, utilize polycrystalline silicon germanium to be better than the characteristic of polysilicon, for example high carrier concentration and low energy gap, the carrier that improves existing irrigation canals and ditches double-diffused transistor penetrates the problem vague and general with polycrystalline.
Manufacture method of the present invention provides the base material of one first conduction type earlier, forms the epitaxial layer of one first conduction type again on base material, and forms the body region of one second conduction type on this epitaxial layer.This body region of etching and epitaxial layer form the liner of an insulating barrier as irrigation canals and ditches again to form irrigation canals and ditches on the surface of these irrigation canals and ditches then.Then, among body region, form the source region of first conduction type with the irrigation canals and ditches position adjacent.At last, in irrigation canals and ditches, deposit the gate of a polycrystalline silicon germanium material as this irrigation canals and ditches double-diffused transistor.
According to one embodiment of the present invention, the first above-mentioned conduction type mixes for the N type, and second conduction type mixes for the P type, and insulating barrier is the monoxide layer.Germanium composition in the polycrystalline silicon germanium gate zone is preferably between 10% to 40%, most preferably is, the germanium composition is about at 30% o'clock, can obtain best effect.
Because the present invention utilizes the material of gate characteristic in essence, be characteristics such as the high carrier concentration of polycrystalline silicon germanium, low energy gap and low contact resistance, improve existing problem, therefore the present invention can implement according to common processing and transistor arrangement, do not need special procedure of processing and special transistor arrangement, the carrier that can improve existing irrigation canals and ditches double-diffused transistor effectively penetrates the problem vague and general with polycrystalline.
The higher carrier concentration of polycrystalline silicon germanium can improve the ability that vague and general problem takes place in opposing, and its carrier activation rate is also apparently higher than polysilicon, therefore compare with polycrystalline silicon gate pole in the existing power transistor, the vague and general problem of the more difficult generation of polycrystalline silicon germanium gate in the power transistor of the present invention, and can improve transistor and when operation, bear high-tension ability.
In addition, the depositing temperature that the present invention is used for filling the polycrystalline silicon germanium of gate is lower than the depositing temperature of existing polysilicon, the lower depositing temperature of polycrystalline silicon germanium, make alloy in the gate, as phosphorus or arsenic, can Yin Gaowen and diffuse to body region, so can improve the existing problem that runs through.In addition, therefore the edge energy of polycrystalline silicon germanium also has the advantage of low contact resistance because of lower than the polysilicon.And the deposition process compatibility of the deposition process of polycrystalline silicon germanium and existing polysilicon need not expend a large amount of boards and processing R﹠D costs.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, hereinafter will be especially exemplified by a preferred embodiment, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 shows the schematic diagram of existing irrigation canals and ditches double-diffused transistor;
Fig. 2 shows the flow chart of manufacture method of the present invention; And
Fig. 3 A to Fig. 3 E shows the schematic diagram corresponding to the irrigation canals and ditches double-diffused transistor of the step among Fig. 2.
Embodiment
In order to improve the problem that runs through of existing double-diffused transistor, the present invention propose a kind of power metal oxide semiconductor field-effect transistor with and manufacture method.
Feature of the present invention comprises at least utilizes a polycrystalline silicon germanium gate to replace the polycrystalline silicon gate pole that has now in the irrigation canals and ditches double-diffused transistor, utilize polycrystalline silicon germanium to be better than the characteristic of polysilicon, for example high carrier concentration and low energy gap, the carrier that improves existing irrigation canals and ditches double-diffused transistor penetrates the problem vague and general with polycrystalline.
The manufacture method of the embodiment of the invention is the base material that one first conduction type is provided earlier, forms the epitaxial layer of one first conduction type again on base material, and forms the body region of one second conduction type on this epitaxial layer.This body region of etching and epitaxial layer to be forming irrigation canals and ditches then, and form the liner of an insulating barrier as irrigation canals and ditches on the surface of these irrigation canals and ditches.Then, among body region, form the source region of first conduction type with the irrigation canals and ditches position adjacent.At last, among irrigation canals and ditches, deposit the gate of a polycrystalline silicon germanium material as this irrigation canals and ditches double-diffused transistor.
Fig. 2 shows the flow chart of manufacture method of the present invention, and Fig. 3 A to Fig. 3 E shows the schematic diagram corresponding to the irrigation canals and ditches double-diffused transistor of the step among Fig. 2.Below utilize Fig. 2 and cooperate Fig. 3 A to Fig. 3 E, explain the manufacture method with irrigation canals and ditches double-diffused transistor of polycrystalline silicon germanium gate of the present invention.
At first, provide a N+ type doping base material 302 (steps 202), building crystal to grow forms N-type doping epitaxial layer 304 (steps 204) that a thickness is 13.5 μ m on N+ type doping base material 302 then.On this N-type doping epitaxial layer 304, form P type doped body zone 306 (steps 206) of one 6 μ m afterwards again, as shown in Figure 3A.
Then, utilize dry ecthing processing etching this P type doped body zone 306 and N-type doping epitaxial layer 304, to form irrigation canals and ditches 312 (step 208), shown in Fig. 3 B.This dry ecthing processing is to utilize a hard mask (hard mask) layer (not shown among Fig. 3 B) to be covered in P type doped body zone 306 earlier, this hard mask layer of pictureization makes it expose an opening so that mold irrigation canals and ditches 312 in the position in P type doped body zone 306 again.The opening that exposed of this hard mask layer of dry ecthing begins etching from the surface in P type doped body zone 306, and extends to N-type doping epitaxial layer 304 then, just forms these irrigation canals and ditches 312 at last.
Shown in Fig. 3 C, remove after the hard mask layer of the above-mentioned usefulness that is used for carrying out dry ecthing processing, a thickness be the oxide skin(coating) 322 of 200 be formed on the surface in P type doped body zone 306 and irrigation canals and ditches 312 around (step 210).This oxide skin(coating) 322 is the insulating barriers as liner.
Then, utilize photoresistance 332 to limit the position in N+ type doped source zone 322 again, the position in this N+ type doped source zone 322 is to be arranged in P type doped body zone 306 and adjacent with irrigation canals and ditches 312.Utilize implanting ions handle to implant alloy again, for example phosphorus or arsenic are so that form this N+ type doped source zone 322, afterwards and remove above-mentioned photoresistance 332 (step 212).Certainly, after implanting ions, also can impose an annealing (annealing) and handle to repair it because of the impaired lattice structure of implanting ions.
At last, carry out the chemical vapour deposition (CVD) processing of a polycrystalline silicon germanium, polycrystalline silicon germanium 326 is filled in the irrigation canals and ditches 312 gate (step 214) as this irrigation canals and ditches double-diffused transistor.According to the preferred embodiments of the present invention, the temperature of chemical vapour deposition (CVD) processing is decided on the shared content of germanium composition wherein between 500 ℃ to 700 ℃.The scope that is used for filling germanium composition contained in the polycrystalline silicon germanium 326 of gate is between 10% to 40%, and the germanium component content can obtain better effect more preferably when 30% left and right sides.In addition, in order to reduce its resistance, the polycrystalline silicon germanium in this gate that mixes usually, with the embodiment of Fig. 3 D, usually can be when deposit spathic silicon germanium Doping Phosphorus, or implanting ions arsenic subsequently can reduce its resistance value effectively.
As known to persons of ordinary skill in the art, this irrigation canals and ditches double-diffused transistor can add source electrode 334 on its N+ type doped source zone 304 when finishing, and form a drain electrode layer 336 at the basal surface of its N+ type base material 302.And in this embodiment, the present invention is to be that the N type mixes and second conduction type is that the P type is doped to example with first conduction type.Yet those of ordinary skills should be known in that the present invention also can be applicable to first conduction type and mixes for the P type, and among the embodiment of second conduction type for the doping of N type.And, the P type mixes and the N type mixes alloy that employed alloy is not limited in the present embodiment to be mentioned, the various existing alloys of having used all can apply among the present invention.
Pure matter carrier concentration (intrinsic carrierconcentration) ni that can derive semiconductor material according to Semiconductive Theory is:
A wherein
*Be a constant relevant with material, T represents absolute temperature, and k then is Boltzmann's constant (Boltzmann constant), and Eg then represents energy gap (energy gap) value of this semiconductor material.
By equation (1) as can be known, the edge energy Eg of semiconductor material is bigger, and its pure matter carrier concentration ni is also big more.Because the edge energy of germanium is less than the edge energy of silicon, so the pure matter carrier concentration of germanium is higher than the carrier concentration of silicon.Table one is edge energy and the semiconductor material silicon of the relation of pure matter carrier concentration and the comparison sheet of germanium that is used for illustrating both:
Table one: the characteristic comparison sheet of silicon and germanium
| Semiconductor material | Eg(eV) | ni(1/cm3) |
| Silicon | 1.12 | 1.45×1010 |
| Germanium | 0.66 | 2.4×1013 |
As shown in Table 1, the pure matter carrier concentration of germanium than the pure matter carrier concentration height of silicon three orders of magnitude.The present invention utilizes the polycrystalline silicon germanium gate to replace the polycrystalline silicon gate pole that has now in the irrigation canals and ditches double-diffused transistor, and the carrier concentration of polycrystalline silicon germanium is between silicon and germanium.Higher carrier concentration can improve the ability that vague and general problem takes place in opposing, and the carrier activation rate of polycrystalline silicon germanium is also apparently higher than polysilicon, and therefore polycrystalline silicon germanium gate of the present invention is compared the problem that more difficult generation is vague and general with existing polycrystalline silicon gate pole.And, utilize polycrystalline silicon germanium as gate of the present invention, also can improve the ability that it bears high voltage operation at irrigation canals and ditches double-diffused transistor of the present invention as the effect transistor.
Moreover the depositing temperature of polycrystalline silicon germanium is decided on the shared content of germanium wherein between 500 ℃ to 700 ℃.The depositing temperature of the existing employed polysilicon that is used for filling gate is then between 700 ℃ to 800 ℃, far above the depositing temperature of polycrystalline silicon germanium of the present invention.From the above, when the processing temperature of being carried out when this irrigation canals and ditches double-diffused transistor was high more, then its probability that carrier penetration problem takes place because of high temperature was also high more.The lower depositing temperature of polycrystalline silicon germanium makes alloy in the gate of the present invention as phosphorus, can not diffuse to body region because of high temperature, so can improve the existing problem that runs through.
In addition, polycrystalline silicon germanium also has the advantage of low contact resistance.Contact resistance value is relevant with edge energy, the material that edge energy is high more, and its contact resistance value is big more.As shown in Table 1, the edge energy of germanium only is about 1/2nd of silicon.The edge energy of polycrystalline silicon germanium can be between the edge energy of silicon and germanium, and therefore polycrystalline silicon germanium gate of the present invention can more existing polycrystalline silicon gate pole, has lower contact resistance.
Because the present invention system utilizes the material characteristic in essence of gate, be characteristics such as the high carrier concentration of polycrystalline silicon germanium, low energy gap and low contact resistance, improve existing problem, therefore the present invention can implement according to common processing and transistor arrangement, do not need special procedure of processing and special transistor arrangement, the carrier that can improve existing irrigation canals and ditches double-diffused transistor effectively penetrates the problem vague and general with polycrystalline.
Moreover the present invention is lower than the depositing temperature of existing polysilicon, the lower depositing temperature of polycrystalline silicon germanium in order to the depositing temperature of the polycrystalline silicon germanium of filling gate, make alloy in the gate, as phosphorus, can not diffuse to body region because of high temperature, so can improve the existing problem that runs through.In addition, therefore the edge energy of polycrystalline silicon germanium also has the advantage of low contact resistance because of being low than polysilicon.And the deposition process compatibility of the deposition process of polycrystalline silicon germanium and existing polysilicon need not expend a large amount of boards and processing R﹠D costs.
Claims (7)
1, a kind of manufacture method of power metal oxide semiconductor field-effect transistor, this manufacture method comprises the following step at least:
The base material of one first conduction type is provided;
On this base material, form the epitaxial layer of one first conduction type;
On this epitaxial layer, form the body region of one second conduction type;
This body region of etching and this epitaxial layer are to form at least one irrigation canals and ditches that extend to this epitaxial layer from this body region;
Form the liner of an insulating barrier as these irrigation canals and ditches;
Form at least one first conduction type and be positioned among this body region and the source region adjacent with these irrigation canals and ditches; And
Depositing a polycrystalline silicon germanium material is positioned among these irrigation canals and ditches and covers gate zone on this insulating barrier to form one.
2, manufacture method as claimed in claim 1 is characterized in that: the germanium composition in this polycrystalline silicon germanium material is between 10% to 40%.
3, manufacture method as claimed in claim 1 is characterized in that: this manufacture method also is included in the step of the alloy that mixes among this polycrystalline silicon germanium material.
4, manufacture method as claimed in claim 1 is characterized in that: the step of this body region of this etching and this epitaxial layer utilizes dry ecthing processing this body region of etching and this epitaxial layer to form this irrigation canals and ditches.
5, manufacture method as claimed in claim 1 is characterized in that, the step that forms this source region comprises at least:
On this body region, form a photoresist layer;
This photoresist layer of patterning; And
At least one alloy of implanting ions is so that form the source region of this first conduction type among this body region;
Wherein this source region is adjacent with this irrigation canals and ditches.
6, manufacture method as claimed in claim 5 is characterized in that: this manufacture method also is included in the step of implanting ions and carries out an annealing in process afterwards.
7, manufacture method as claimed in claim 1, it is characterized in that: the step that deposits this polycrystalline silicon germanium material is to deposit this polycrystalline silicon germanium material among these irrigation canals and ditches and cover on this insulating barrier by a chemical vapor deposition process, thereby forms this gate zone.
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| CNB031577989A CN100334740C (en) | 2003-08-26 | 2003-08-26 | Power MOSFET and its mfg. method |
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| CNB031577989A CN100334740C (en) | 2003-08-26 | 2003-08-26 | Power MOSFET and its mfg. method |
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| CN100334740C true CN100334740C (en) | 2007-08-29 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
| US6133084A (en) * | 1999-05-25 | 2000-10-17 | United Microelectronics Corp. | Method of fabricating static random access memory |
| TW423118B (en) * | 1999-11-22 | 2001-02-21 | Shr Min | CMOS process having poly-SiGe gate |
| US6518621B1 (en) * | 1999-09-14 | 2003-02-11 | General Semiconductor, Inc. | Trench DMOS transistor having reduced punch-through |
| CN1412858A (en) * | 2001-10-18 | 2003-04-23 | 旺宏电子股份有限公司 | High-performance grid nitride ROM structure |
-
2003
- 2003-08-26 CN CNB031577989A patent/CN100334740C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
| US6133084A (en) * | 1999-05-25 | 2000-10-17 | United Microelectronics Corp. | Method of fabricating static random access memory |
| US6518621B1 (en) * | 1999-09-14 | 2003-02-11 | General Semiconductor, Inc. | Trench DMOS transistor having reduced punch-through |
| TW423118B (en) * | 1999-11-22 | 2001-02-21 | Shr Min | CMOS process having poly-SiGe gate |
| CN1412858A (en) * | 2001-10-18 | 2003-04-23 | 旺宏电子股份有限公司 | High-performance grid nitride ROM structure |
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