TW413877B - Package body and semiconductor chip package using same - Google Patents
Package body and semiconductor chip package using same Download PDFInfo
- Publication number
- TW413877B TW413877B TW86116757A TW86116757A TW413877B TW 413877 B TW413877 B TW 413877B TW 86116757 A TW86116757 A TW 86116757A TW 86116757 A TW86116757 A TW 86116757A TW 413877 B TW413877 B TW 413877B
- Authority
- TW
- Taiwan
- Prior art keywords
- package
- hole
- patent application
- scope
- semiconductor chip
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 229920006336 epoxy molding compound Polymers 0.000 claims abstract description 5
- 239000000945 filler Substances 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 230000000875 corresponding effect Effects 0.000 claims description 4
- 230000002079 cooperative effect Effects 0.000 claims description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 abstract description 13
- 235000012431 wafers Nutrition 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 5
- DEVSOMFAQLZNKR-RJRFIUFISA-N (z)-3-[3-[3,5-bis(trifluoromethyl)phenyl]-1,2,4-triazol-1-yl]-n'-pyrazin-2-ylprop-2-enehydrazide Chemical compound FC(F)(F)C1=CC(C(F)(F)F)=CC(C2=NN(\C=C/C(=O)NNC=3N=CC=NC=3)C=N2)=C1 DEVSOMFAQLZNKR-RJRFIUFISA-N 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241001190694 Muda Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229940125773 compound 10 Drugs 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000004512 die casting Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- ZLVXBBHTMQJRSX-VMGNSXQWSA-N jdtic Chemical compound C1([C@]2(C)CCN(C[C@@H]2C)C[C@H](C(C)C)NC(=O)[C@@H]2NCC3=CC(O)=CC=C3C2)=CC=CC(O)=C1 ZLVXBBHTMQJRSX-VMGNSXQWSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000015170 shellfish Nutrition 0.000 description 1
Classifications
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
4138*77 A7 ______B7 五、發明説明(i ) 發明背景 發明領域 本發明係有關於半導體晶片封裝,而特別是有關於 將其使用於改良封裝體與半導體晶片封裝者’藉由排除基 材與金屬線之使用適合用以縮小其尺寸與厚度。 相關習知技藝之說明 考慮一般之半導體晶片封裝,常述及使用眾多焊球 以作為外部端子的球陣列(以下稱BGA)半導體晶片封裝, 因為其可在小區域中產生多銷件結構,是以此種BGA封 裝被廣风地應用’在傳統BGA封裝之外端子夠短,是以 可防止當電訊傳輸時的外界應力而變形彎屈。 而且’當將其裝設於主機板時’在融爐中封裝體瞬 時迴流可藉以縮短裝設時間。 經濟部中央標準局負工消費合作社印製 如第1圖所示,傳統之BGA封裝體包括:一基板1、 籍黏合劑2裝設於基板j中央表面之半導體封裝晶片3、形 成於晶片3上表面之眾多晶片墊3a、分別連接晶片墊3&於 基板1之金屬圖樣(未示出)之眾多金屬線4、在基板1上所 形成之用以覆蓋晶片3與金屬線4之模鑄化合物5,以及附 接於基板底表面之眾多焊球。 如此構成之傳統BGA封裝的製造方法包括的步驟 如· 一用以將半導體晶片3附接於基板1上表面的晶圓鍵接 步驟、—藉由對應之金屬線4而將基板1上金屬圖樣(未示 出)連接於才目對應晶片3上表面所形成的晶月墊3a之線鍵接 步驟Λ ~使用環氧樹脂以環封晶片3與金屬線4的模造化合 -4- 姆尺度逋财 413877 經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明(2 ) 物5之模造步驟、以及—用以聯接基板i下表面上眾多焊球 來完成BGA封裝之焊球連接步驟。 然而,如此構成之BGA封裝體有其封裝體積之限 制,因為金屬線4應有其固定迴圈高度。 再者,使用各別金屬線4來進行線鍵接步驟以將晶片 3上所形成之晶片墊3a聯接至基板j上金屬圖樣(未示出)是 困難且耗時的’是以限制生產力。 發明概述 因此,本發明之目的係欲提供不需使用基材與金屬 線的半導體晶片封裝來縮小其尺寸與厚度。. 本發明之另一目的係欲提供一可藉由排除需許多時 間之線鍵接步騍來改良半導體晶片封裝的生產力。 為達到上述之目的,所供設之半導體晶片封裝用之 封裝體具有眾多由第二孔洞下表面穿出而至封裝體下表面 的第一穿孔’以及由封裝體上表面邊緣部穿出至封裝體下 表面的第二穿孔。 再者’為達上述之目的,所供設之半導體晶片封裝 包括一封裝體,其具有在封裝體上表面所形成之第一孔洞 以及在第一孔洞上下表面所形成之第二孔洞,並具有取多 聯接第二孔洞底表面與封裝體下表面之金屬圖樣、一表面 上具有附接於其上的鍵接墊以及附接於鍵接墊上之眾多突 塊’其中,突塊聯接於相對應之金屬圖樣、一在第二孔洞 上所形成之填充劑,以及形成於第一孔洞上之環氧樹脂模 造化合物。 本紙張尺度適用中國國家標準(CNS > Λ4規格U〗0X297公釐) » n ^^^1 HI n (請先閲讀^面之、注意事項再填寫本頁) 摩 413877 A7 一——____ B7 五、發明説明(3 ) ' ~ 圖示簡要說明 參考所附圖式,本發明將更容易瞭解,其等僅用以 說明而非限制本發明之用,其中: 第1圖係傳統BGA封裴之截面圖; 第2圖係依本發明之半導體封裝體的截面圖; 第3圖係本發明半導體晶片封裝的截面圖; 第4A至4E圖為用以說明本發明半導體晶片封裴續 列步驟的製造圖;以及 第5圖係一流程圖,用以說明依本發明之半導體晶片 封裝製造步驟。 發明詳細說明 參考所附之圖式,以下將說明本發明之半導體晶片封 裝。 如說明本發明封裝體之截面視圖的第2圖,在封裝 體上表面形成一正方形第一孔洞i i,在第一孔洞丨丨之底部 形成一正方形第二孔洞12,在封裝體10之下方部形成眾多 訊號線13,以聯訊第二孔洞丨2與封裝體10之底表面。 經濟部中央標準局員工消費合作社印裝 所形成之第二孔洞12小於第一孔洞〖丨,設置於封裝 體10中之每一信號線13的端部曝露於第二孔洞12之底部與 封裝體10的底表面,在第一孔洞11上所餘之底表面上形成 一金屬板14,穿過第二孔洞12之底表面所形成之眾多第— 穿孔’以與封裝體10下表面聯訊,而且’幕多第二穿孔16 係垂直地自封裝體10周緣由上向下穿出。 第3圖說明本發明之完成半導體晶片封裝,一如其 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297^7 413877 經濟部中央標準局貝工消費合作社印製 A7 _B7五、發明説明(4 ) 中所示者,晶片封裝保括一裝設有眾多信號線13的封裝 體,以及裝設於封裝體10中之.半導體晶片20。 第4A至4E圖為用以說明本發明半導體晶片封裝續 列步驟的製造圖;以及第5圖係一用以說明依本發明之半 導體晶片封裝製造步驟的流程圖。 首先,參照第4 Α圓,在許半導體晶片20上所形成 之眾多鍵接塾3Q相對應處形成眾_多突塊4〇,此種突塊步驟 係在晶圓(未示出)上進行,在此,可獲得眾多半導體裝置 或晶片β ' 如第4Β圖所示者,突塊化半導體晶片2〇係藉由向 異性材料而裝設於信號線13上端,其曝露於封裝體10之第 二孔洞的底部。 如第4 C圖所示,藉由下填技術將低黏度之液態封 裝劑60形成於半導體晶片20底表面與第二孔洞的底面,為 此以將突塊40固定於第二孔洞12,在此,液.態封裝劑之 上表面與第一孔洞11底面等齊。 參照第4 D圖,將封裝體10之第一孔洞^充以環氧 模造化合物70,如此,經裝設半導體晶片2〇之上表面向外 曝露,在此,形成於第一孔洞U底面之金屬板14可用以增 加環氧模造化合物70與封裝體1〇間的黏合力,再者,所形 成之經裝設之半導體晶片20的上表面、封裝體10周緣上表 面與模造化合物70之上表面係共平面或等齊的。 如第4E圖所示’在封裝體10下表面所曝露之信號 線13的下緣對應處接有眾多焊球8〇,再者’眾多焊球係 本,.A張尺度適用中國國家標準(CNS〉A4規格(210X297公楚) (諳先閱讀背面's^再填寫本買} -叫'^.· .L--¢. — 訂 _ to- 413877 經濟部中央標準局員工消費合作社印裝 五、發明説明( 供設於相對應之第一與第二穿孔15,16之下方入口處,藉 以可完成本發明之半導體封裝製造。 如上所述者,本發明之半導體晶片封裝藉由排除基 板與金屬線之使用而最小化其尺寸與厚度。 再者,可藉由本發明之半導體晶启封裝排除耗 焊線鍵接步驟,而改善生產力。 元件標號對照表 1 基板 3,20 晶片 4 金屬線 5 模造化合物 10 封裝體 11,12孔洞 13 信號線 14 金屬板 15,16孔洞 40 突塊 80,90 焊球 -8- 本紙張欠度適用中國國家標準(CNS ) A4規格(210X297公釐) (諳先閲讀背面之注拳項再填考本頁j -訂- t
Claims (1)
- 413877 驾 — ___ D8 '申請專利範圍 1. 一種半導體晶片封裝用之封裝體,其包括: 在該封裝體上表面中所形成之第一孔洞; 在第一孔洞底表面中所形成之第二孔洞;以及 用以連接第二孔洞至封裝體之下表面的眾多金屬圖樣。 2·如申請專利範圍第1項之封裝體,更包括: 眾多由第二孔洞底面穿透至封裝體下表面的第一 穿孔;以及 眾多由封裝體上表面邊緣部穿透至封裝體下表面 的第二穿孔。 3·如申請專利範圍第1項之封裝體,更包括: 在第一孔洞底表面邊緣部上所形成之金屬板。 4·如申請專利範圍第1項之封裝體,其中,該金屬圖樣 係顯露於第二孔洞之底表面與封裝體下表面處。 5.如申請專利範圍第4項之封裝體,更包括: 眾多附接於第二孔洞底表面處曝露之金屬圖樣上 的向異性-導體元件;以及 眾多附接於封裝體下表面處金屬圖樣的焊球。 6 如申請專利範圍第2項之封裝體,更包括: 眾多附接於穿過封裝體下表面之第一與第二穿孔 的焊球。 7 ·如申請專利範圍第1項之封裝體,其中,該第一孔洞 與第二孔洞為方型。 8.—種半導體晶片封裝,其包括: 一封裝體,其具有在封裝體頂表面中所形成之第 -9- 本紙張尺度適用中國國家樣準(CNS ) A4规格.(210x29*7公董) (請先閲讀背面之注意事項异填寫本瓦) 訂 經濟部智慧財產局員工消費合作钍印製 413877 ss C8 ' --------D3 : '申請專利範圍 一孔洞與在第一孔洞底表面中所形成之第二孔洞, 並具有眾多聯接第二孔洞之底表面與封裝體下表面 的金屬圖樣; 一半導體晶片,其具有其上所附接之眾多鍵接 墊,以及附接於該鍵接墊之眾多突塊,其中該突塊 係聯接至金屬圍樣之相對應處; 在第二孔洞中所形成的填充劑;以及 在一孔洞中所形成的環氧模造化合物。 9·如申請專利範圍第8項之半導體晶片封裝,其中, 金屬圓樣係曝露於第二孔洞底表面與封裝體底表 面處。 10. 如申請專利範圍第8項之半導體晶片封裝,更包括: 眾多附接於第二孔洞底表面處曝露之金屬圖樣上 的向異性導體元件;以及 眾多附接於封裝.體下表面處金屬圖樣的焊球。 11. 如申請專利範圍第8項之半導體晶月封裝,更包括: 在第一孔洞底表面之邊緣處所形成之金屬板。 12‘如申請專利範圍第8項之半導體晶片封裝,其中,封 裝體包括眾多由第二孔洞底面穿透至封裝體下表面的 第一穿孔:以及眾多由封裝體上表面邊緣部穿透至封 裝體下表面的第二穿孔。 13. 如申凊專利範圍第8項之半導體晶片封裝,更包括幕 多附接第一與第二穿孔至封裝體下表面的焊球。 14. 如申請專利範圍第8項之半導體晶片封裝,其中,所 -10- 本纸張尺度適用中國國家標準< CNS > A4規格(210X297公釐) •---------Λ/,— (請先閲讀背面之注意事項再填寫本頁) -s 經濟部智慧財產局員工消費合作社印製 AS B8 C8 D8 413877 申請專利範圍 裝設晶片的上表面係曝露在外。 15. 如申請專利範圍第14項之半導體晶片封裝,其中, 裝設晶片上表面、封裝體上表面的邊緣部以及: 造化合物之上表面係大致共平面的。 、 16. 如申請專利範圍第8項之半導體晶片封裝,其中,填 充劑之上表面係與第—孔洞之底表面大致共平面的。 17. 如申請專利範圍第8項之半導體晶片封裝’其中,第 一與第二孔洞係成方形的。 f請先閲讀背面之注意事項再填寫本買) 訂 線 經濟部智慧財產局員工消費合作社印製 -11· 本纸承尺度適用中國國家揉準(CNS ) A4規格(2丨0><297公着 + )
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CN110211888A (zh) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | 一种嵌入式扇出封装结构及其制造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5043794A (en) * | 1990-09-24 | 1991-08-27 | At&T Bell Laboratories | Integrated circuit package and compact assemblies thereof |
US5241133A (en) * | 1990-12-21 | 1993-08-31 | Motorola, Inc. | Leadless pad array chip carrier |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
KR100206893B1 (ko) * | 1996-03-11 | 1999-07-01 | 구본준 | 반도체 패키지 및 그 제조방법 |
-
1997
- 1997-03-14 KR KR1019970008653A patent/KR100234719B1/ko not_active IP Right Cessation
- 1997-11-10 TW TW86116757A patent/TW413877B/zh not_active IP Right Cessation
-
1998
- 1998-02-11 US US09/021,829 patent/US6031284A/en not_active Expired - Lifetime
- 1998-03-06 JP JP5511698A patent/JPH10261738A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH10261738A (ja) | 1998-09-29 |
KR100234719B1 (ko) | 1999-12-15 |
US6031284A (en) | 2000-02-29 |
KR19980073411A (ko) | 1998-11-05 |
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