4 祕、、4 A7 五、發明說明（f ) 本發明是有關於—種半導體封裝結構之製作方法，且 特別是有關於一種具有印製導線(Trace Line)及金屬拴之球 格陣列封裝結構的製作方法。 (請先閱讀背面之注意事項再填寫本頁) 在半導體產業中，積體電路（Integraied Circuits，ic)的 生產，主要分爲三個階段：一爲半導體基底之形成，即磊 晶技術部份’如矽晶片的製造；其次是半導體元件製造， 諸如金氧半導體製程、多重金屬內連線等；最後則爲半導 體的封裝(Package)。封裝之目的在於提供晶片（Die)與印刷 電路板（Printed Cuxuh B0ard，PCB)或其他適當元件之間進 行電性連接的媒介以及保護晶片^ 經濟部智慧財產局員工消費合作社印製 在積體電路的模組（M〇dule)中，由於大量導線從晶片 中釋出’故需要數以百計的連接來構成完整的線路。傳統 的方式是以導線架(Lead Frame)電性連接晶片與封裝的外接 導線。因爲積體電路的積集度日益增加，雖然封裝體積保 持原狀或縮小，但其所需之導線卻大量增加，傳統導線架 已不敷使用。而且電子產品之發展日趨輕、薄、短、小， 因此發展出許多不同的封裝技術，諸如晶片尺寸封裝(Chip Scale Package，Chip Size Package, CSP)、多晶片型封裝 (Multi-Chip Module, MCM)等。 由於半導體製程技術已發展至線寬0.18微米(Micron) 的元件’對提高積集度有許多突破，因此如何開發出對應 之小體積封裝，以達到產品縮小化的目的，便成爲現今重 要課題。 傳統封裝係以導線架作爲承載器，而導線架之導腳 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 五、發明說明（2 ) (Lead)則是從封裝之側面伸出，由於導腳爲.周緣式配置 (Peripheral Layout)，使得封裝面積變大，且對於高腳數元 件而言’將因導腳間距受限而被迫加大封裝面積。所以， 許多面積陣列式（Area Array)封裝結構相繼發展出來，將封 裝接點配置於封裝底部，諸如：球格陣列封裝（Ball Grid Array, BGA)、小型無導腳封裝（Small Outline No-lead, SON)、球型晶片承載器（Ball Chip Carrier, BCC)等。 請參照第1A圖至第IE圖，其所繪示的是習知球型晶 片承載器封裝之製作流程的剖面示意圖。首先請參照第1A 圖，在銅底材100之表面102a、102b分別塗佈光阻層104a、 104b，並對光阻層104a進行曝光顯影，以曝露出銅底材100 上表面102a中的球型接腳區域106。 接著，請麥照第1B圖，以光阻層104a ' 104b爲罩幕， 對銅底材100進行濕式蝕刻，在銅底材100中的球型接腳 區域106形成半球型凹穴108。接著進行電鍍，於半球型 凹穴108表面電鍍一層金膜110。 請參照第1C圖，剝除光阻層104a、104b，並在表面102a 粘黏一晶片112。進行打線接合（Wire Bonding)，以金線114 將晶片112上之焊墊（未顯不於圖中）與金膜110連接。然 後，請參照第1D圖，對銅底材100之上表面102a進行封 膠，以樹脂116包覆晶片112、金線114及金膜110。 再請參照第1E圖，接著進行濕式蝕刻，將銅底材（如 第1D圖之1〇〇)完全去除，而露出半球型之金膜110、晶. 片112底面及樹脂U6表面。至此，即完成球形晶片承載 4 · (請先閱讀背面之注意事項再填寫本頁) --------訂---！！-故 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ 297公釐） A7 B7 ^432644 46^9tvv f.doc/006 五、發明說明（4 ) 器封裝’而此種封裝乃是利用半球形金膜1 ] 〇作爲接腳， 與外部之電路耦接。 然而’上述球形晶片承載器之主要缺點在於產品之可 靠度’以及製造良率。由於該種封裝係利用金膜作爲接腳， 而金膜爲貴金屬’就成本考量鍍層不能太厚，卻容易在加 工過程或搬運過程磨損或剝落，影響後續與其他電路基板 之連接，例如表面焊接技術（Surface Mount Technology, SMT) 之可靠度，以及產品之製造良率》 而且’由於元件之腳位數日益增加，封裝基板上對應 之焊墊密度亦隨之昇高，焊墊間距愈形縮小。而封裝基板 上用以與其他電路基板連接之接點，其數量則需對應於焊 墊同時增加，且接點的尺寸與間距受限於其他基板而無法 縮小，故必須呈面積陣列式配置，方能滿足封裝之需求。 因此本發明提供一種具有印製導線及金屬栓之球格陣 列封裝結構的製作方法，具有良好之可靠度及製造良率。 以金屬栓作爲封裝之接腳，且金屬栓可呈面積陣列式配 置，並使封裝具有較薄之厚度。而裸露晶片座之底面，可 以提高晶片散熱效果。金屬栓之端面還配置有鍍層，兼具 良好之接合性、封裝性以及焊接性，利於後續表面焊接技 術製程，可應用於高腳數元件之封裝。 根據本發明之上述及其他目的，提出一種具有印製導 線及金屬栓之球格陣列封裝結構的製作方法，可應用於高 腳數元件之封裝。首先提供金屬底材，並於金屬底材表面 之金屬栓區域及晶片座區域形成鍍層。對金屬底材上表面 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公爱） I I Γ I I *r I I I I I L - I I I I I I I 11111111 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員Η消費合作社印製 r 143264 4 4 6 5 91 w f, d o c /0 Ο 6 A7 五、發明說明（#) 進行部份蝕刻，移除部份金屬底材，以縮減其厚度，形成 印製導線、晶片座及內部金屬栓。將晶片黏著於晶片座’ 並與內部金屬栓形成電性連接。再以絕緣材料進行封膠’ 覆蓋晶片、晶片座及內部金屬栓。其次對金屬底材下表面 進行蝕刻，曝露出部份絕緣材料與晶片座之底部’並形成 外部金屬栓，且由印製導線電性連接內部和外部金屬栓。 然後於晶片封裝表面形成焊罩，覆蓋印製導線’且曝露出 外部金屬栓端面之鍍層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式’作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1E圖所繪示爲習知球型晶片承載器封裝 之製作流程的剖面示意圖； 第2A圖至第2H圖所繪示爲依照本發明之較佳實施 例，一種具有印製導線及金屬栓之球格陣列封裝，其製作 流程的剖面示意圖； 第3A圖與第3B圖_所繪示爲依照本發明之較佳實施 例，一種具有印製導線及金屬栓之球格陣列封裝，其製作 流程中，形成鍍層後之金屬底材的上視圖及下視圖； 第4圖所繪示爲依照本發明之較佳實施例’一種具有 印製導線及金屬栓之球格陣列封裝，其製作流程中’於金 屬底材上形成印製導線後之示意圖；以及 . 第5圖所繪示爲依照本發明之較佳實施例，一種具有 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） ---------— 11. - I ------^ - — — — In — · ^ <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 r P4326 4 4 46S9t\vf.doc.O06 幻 _B7_ 五、發明說明（g ) 印製導線及金屬栓之球格陣列封裝，其製作流程中，金屬 底材經黏著晶片及打線接合後之上視圖。 _ 圖式之標記說明： 100 :銅底材 102a、102b :表面 l〇4a、104b :光阻層 106 :球型接腳區域 108 :半球型凹穴 110 :金镆 112、216，晶片 ‘ 114 :金線 116 :樹脂 200 :金屬底材 202a、202b :金屬底材表面 206a :晶片座區域 206b、_206c :金屬栓區域 208a、2()8b、208c :鍍層 210:晶片座 · 212a、212b :金屬栓 214、2丨4a、2丨4b :印製導線 218 :導線 220 :絕緣材料 222 :焊罩 224 :焊接材料 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ΐ請先閱讀背面之注意事項再填寫本頁) 裝·-------訂·!------ 經濟部智慧財產局員工消費合作社印製 ^432644 465^t\v r.duc/006 A7 ____B7__ 五、發明說明（4) 226 :接著材料 Η :,高度差 實施例 請參照第2Α圖至第2Η圖，其所繪示的是依照本發明 之較佳實施例，一種具有印製導線及金屬栓之球格陣列封 裝，其製作流程的剖面示意圖。 如第2Α圖所示，本發明具有印製導線及金屬栓之球 格陣列封裝製程，首先提供金屬底材200，其材質包括銅ν 鐵、銅合金（C151、C194、C7025、KCF125、EFTEC 等）或 鐵鎳合金（Ni-Fe 42 Alloy)等。於金屬底材200之第一表面 202a及第二表面202b上塗佈光阻，經曝光、顯影等微影 (Photolithography)製程定義晶片座區域206a、第一金屬栓 區域206b和第二金屬检區域206c後，曝露出金屬底材200 之部份表面，形成圖案化之第一光阻層204a與第二光阻 層 204b 。 請參照第2B圖，進行電鍍製程(Platmg)，於第一表面 202a的晶片座區域206a及第一金屬栓區域206b上，分別 形成晶片座鍍層208a和第一鍍層208b，以及在第二表面 202b的第二金屬栓區域206c形成第二鍍層208c。其中晶 片座鍍層208a、第一鍍層208b與第二鍍層208c之材質包 括金(Au)、銀（Ag)、鎳（Ni)、鈀（Pd)、鎳鈀合金或者是由上 述材質組成之複合鍍層。而較佳的組合則是先電鍍一層鎳 層’再於其上電鍍形成鎳鈀層，最後在表面電鍍一層鈀層。 而鎳層之作用t要是在防止腐蝕，鈀層則兼具良好之接合 8 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公爱） --^----'1------- 裝！|訂·--------線 、 (請先閲讀.t面之注意事項再填寫本頁) A7 B7 P43264 4 4659UVl\doc/〇 06 五、發明說明（/y) 性（Bondability)、封裝性（Molding Compound Characteristic) 以及焊接性（SoiderabiHty)。 請配合參照第3A圖與第3B圖，其所繪示的是依照本 發明之較佳實施例，一種具有印製導線及金屬栓之球格陣 列封裝’其製作流程中，形成鍍層後之金屬底材的上視圖 及下視圖。如圖所示，於金屬底材中可以同時製作數個封 裝所需之基板。第3A圖所示爲金屬底材之上視圖，亦即 類似於第2B圖中第一表面202a的俯視圖，其中晶片座鍍 層208a係配置於晶片封裝區域的中央位置，覆蓋於晶片 座區域上’而第一鍍層208b則是位於晶片座區域之周緣， 其餘表面爲光阻層204a所覆蓋。第3B圖所示則爲金屬底 材之下視圖，亦即類似於第2B圖中第二表面202b之俯視 圖’第二鍍層208c呈面積陣列式分佈，其餘之表面則爲 光阻層204b所覆蓋。 第3A圖中之晶片座鑛層208a及第一鍍層208b呈矩 形’而第3B圖中的第二鍍層208c呈圓形，在本實施例中 係以此構型進行說明，然而晶片座鍍層208a、第一鍍層208b 或第二鍍層208c可爲其他各種不同之形狀，故圖中所示 的鍍層形狀並非用以限制本發明之範圍。此外，第一鍍層 208b與第二鍍層208c係依據電性連接及接點數目之需求， 而呈不同型態之分佈，例如於晶片座鍍層之周緣形成單層 圈狀分佈（如第3A圖），或多層圈狀分佈（如第3B圖）。然 而圖中所不之鏟層分佈型態，係用以舉例說明本窗施例， 並非用以限制本發明之範圍。 ’ --.---I------jf--------訂--------.-線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） _4 3264 4 4659t wl'.doc ΌΟΟ 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 Β7 五、發明說明（》） 其次請爹照_ 2C圖’將第2B圖中之第一光阻層204a 及第二光阻層204b剝除，再於金屬底材200之第一表面202a 上塗佈光阻（未顯示於圖中），經曝光、顯影等微影製程， 定義所需晶片座210、第一金屬栓212a及印製導線2i4a 之位置。然後對金屬底材200進行蝕刻，例如使用濕式蝕 刻法，移除部份金屬底材200，以形成晶片座210、第一 金屬栓212a及印製導線214a，並使印製導線214a與晶片 座2丨〇之間保持距離，在晶片座210周圍形成隔離區，防 止晶片與印製導線214a產生不必要之電性連接。其中晶 片座210表面覆有晶片座鍍層208a，第一金屬栓212a之 表面則爲第一鍍層208b所覆蓋，而印製導線214a是用以 電性連接不同金屬栓及接點。 請參照第2D圖，對於金屬底材200未被晶片座鍍層 2〇8a及第一鍍層208b覆蓋之區域，進行厚度縮減，以降 低第2C圖中之印製導線214a的高度，形成所需之印製導 線214b、晶片座210及位於其周圍的第一金屬栓212a，並 使第一金屬栓212a與印製導線214b之間具有高度差Η。 其中高度差Η至少約爲1密爾(mil)，即0.025毫米(mm)， 而較佳的高度差Η則是大於2密爾(0.05毫米）。 如第2D圖所示，其中縮減金屬底材厚度之方法，例 如是以晶片座鍍層208a和第一鍍層208b作爲触刻罩幕1 對金屬底材200進行半蝕（Half Etching)，蝕刻金屬底材 200，移除部份金屬底材200，形成所需之印製導線214b ' 晶片座210及第一金屬栓212a。亦可以採用壓製(Coin)方 丨 1 丨丨 —— 丨 — I— —— — — — — I— ^ — — — — — — — f (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國®家標準（CNS)A4規格（2】〇χ297公釐） 經濟部智慧財產局員工消費合作社印製 曩4 3 2 6 4 4 46州、'「山)以〇〇6 A7 _ B7 五、發明說明（q) 式’對於金屬底材200第一表面202a上未覆有晶片座鍍層 2〇8a及第一鍍層208b之區域，使用模具進行壓製，以降 低金屬底材之厚度，形成所需之印製導線214b、晶片座2丨〇 及第一金屬栓212a。 請配合參照第4圖，其所繪示的是依照卒發明之較佳 實施例’一種具有印製導線及金屬栓之球格陣列封裝，其 製作流程中’於金屬底材上形成印製導線後之結構示意 圖。如第4圖所示’並參考第3A及3B圖，類似於第2C 及2D圖中金屬底材2〇〇之俯視圖，其中晶片座鍍層2〇8a 係配置於晶片封裝區域的中央位置，而印製導線214則是 電性連接第一鍍層208b及第二鍍層208c之媒介。 再請參照第2E圖’進行晶片黏著(Chip Attach)及晶片 與金屬栓之間的電性連接。將晶片216固定於晶片座21〇 之鍍層208a的表面上，例如使用絕緣膠、導電膠或貼帶 等接著材料226，使晶片216黏貼於晶片座鍍層208a表面 上°而電性連接晶片焊墊（未顯示於圖中）與第一金屬栓 212a’則是採用例如打線接合方式，以導線218連接晶片 焊墊與第--金屬栓212a上之第一鍍層208b，其中導線218 之材質例如是金、鋁或銅等。 請配合參照第5圖，其所繪示的是依照本發明之較佳 實施例’一種具有印製導線及金屬栓之球格陣列封裝，其 製作流程中’金屬底材經黏著晶片與打線接合後之上視 圖。如圖所示’其中晶片座鍍層208a之面積小於其所承 載之晶片216,晶片焊墊與第-鍍層2〇8b之間的電性連接1 本纸張尺度適用中國國家標準 (CNS)A4規格（2]〇 X 297公爱） ------------- * I 1-----訂-----—---線 <請先閱讀背面之注意事項再填寫本頁) Γ Μ43 2 6 4 4 465ι)ΐννί'.ι3οο. 006 幻 ___Β7__ 五、發明說明（/〇) 係由例如使用打線接合形成之導線2i8來完成，而導線218 之材質則包括金、銘或銅等。 請同時參照第4圖與第5圖，第一鍍層208b是分佈 於晶片之周緣《然而金屬底材上第一鍍層208b的分佈型 態，係配合晶片焊墊之分佈，因此可呈不同型態之分佈， 例如第一鍍層分佈於晶片之相對兩側，故圖中所示第一鍍 層的分佈型態係爲舉例說明，並非用以限制本發明之範 圍。 請參照第2F圖，進行封膠製程（Molding)，以絕緣材 料220包覆導線218、晶片216、晶片座鍍層208a、晶片 座210、第一鍍層208b、第一金屬栓212a及印製導線214b 等，其中所使用之絕緣材料包括樹脂（Resm)、環氧樹脂 (Epoxy)等。然而此封膠製程僅在金屬底材200之第一表面 上進行，至於第二表面202b則是完全裸露於絕緣材料220 之外。 然後請參照第2G圖，以第二鍍層208c作爲蝕刻罩幕， 對金屬底材200之第二表面（第2F圖中之202b)裸露的部份 進行蝕刻，移除部份金屬底材，曝露出部份絕緣材料220 及印製導線214b，以形成第二金屬栓212b，完成印製導線 及金屬栓之製作。而晶片座210於蝕刻後形成完整的輸廓， 具有約與絕緣材料224底面平行之下表面。其中第二金屬 栓212b可藉由印製導線214b作爲媒介，與第一金屬栓212a 電性連接。 再請參照第2H圖，於晶片封裝之表面塗佈焊罩材料， 本纸張尺度適用_國國家標準（CNS)A4規格（210 X 297公釐） 、r _4 326 4 4 4 659t wr,doc/006 五、發明說明（//) 於印製導線214b之表面形成焊罩222，並使第二鍍層208c 曝露出來。圖中焊罩222僅覆蓋印製導線214b裸露之表 面，然而焊罩222並不限於覆蓋印製導線222，僅需使第 二鍍層208c曝露出來即可。因此，圖中焊罩之構型係用 以舉例說明本實施例，並非用以限制本發明之範圍。 形成第2H圖中焊罩222之材質爲絕緣材料，包括感 光型綠漆及熱硬化型綠漆等，而塗佈綠漆形成焊罩之方法 則包括滾筒塗佈法（Roller Coating)、簾幕塗佈法（Cunam Coating)、網版印刷法（Screen Printing)以及乾膜（Dry Film) 形成方法等。例如使用感光型綠漆形成焊罩222，是先將 綠漆塗佈於晶片封裝之表面，並覆蓋印製導線214b裸露 之表面，經第一次烤乾、曝光、顯影及第二次烤乾等步驟 後，形成所需之焊罩222。又例如使用熱硬化型綠漆形成 焊罩222，則是按照所需之焊罩圖案將綠漆塗佈於印製導 線214b裸露之表面，經烤乾使其硬化，即可形成所需之 焊罩222。 請再參照第2H圖，完成焊罩222之製作後，還可於 封裝底面的第二鍍層208c上佈植焊接材料224，以提供晶 片封裝與其他電路基板進行電性連接之媒介，其中焊接材 料224包括焊接錫膏（Solder Paste)、焊接錫球（Solder Ball)、 銅球(Copper Ball)等。若於第二鍍層208c佈植焊接錫球或 銅球，則可構成球格陣列；若於第二鍍層208c表面塗佈 焊接錫膏，則可構成焊墊陣列(Land Grid Array，LGA)。最 後再以晶圓切割方法進行分割’完成封裝成品之製作。 ί請先閱讀背面之注意事項再填寫本頁) ---- •訂---------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 •432644 4 6 5 9 tw t.. d o c / Ο 06 Λ7 五、發明說明（h) 由第2H圖可知，應用本發明具有印製導線及金屬栓 之球格陣列封裝，在其封裝結構中至少具有承載晶片216 之晶片座210，其表面與有鍍層208a，而其底面則可裸露 於絕緣材料220外。第二金屬栓212b配置於晶片座210周 緣，且呈面積陣列式分佈。第一金屬栓212a —端埋入絕 緣材料220中，且與晶片焊墊電性連接；另一端則是與印 製導線2Ub連接，並藉由印製導線214b與第二金屬栓2I2b 電性連接。此外在第一金屬栓212a及第二金屬栓212b之 端面還分別具有第一鍍層208b和第二鍍層208c，以利封 裝之接合、封膠及後續表面焊接技術等製程。 由上述本發明較佳實施例可知，應用本發明至少具有 下列優點： 1.本發明具有印製導線及金屬栓之球格陣列封裝，係 利用金屬栓作爲封裝之接腳，以連接晶片與外部電路，可 採面積陣列式配置，提高封裝之積集度。而且金屬栓具有 較佳之機械強度，可提高封裝之可靠度，並提昇良率。 2·由於本發明具有印製導線及金屬栓之球格陣列封 裝，係採用單而封膠的方式，具有較薄之封裝厚度，可以 降低封裝體積。而金屬底材下表面經蝕刻後，晶片座底面 曝露於絕緣材料外，可以提高晶片散熱效果。 3.本發明具有印製導線及金屬栓之球格陣列封裝中， 在金)ί栓之一端配置有鍍層，可用以作爲蝕刻製程之罩 幕。適當選擇鍍層材質，則可使金屬栓兼晷良好之接合性、 封裝性以及焊接性，提高產品之良率，及後續進行表面焊 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公爱） ------------^--------訂---------線 <請先閱讀背面之注意事項再填窝本頁} A7 B7 P4 32 6 4 4 4659t\vi .doc/0{)6 五、發明說明（丨·>) 接時的可靠度。 4.本發明具有印製導線及金屬栓之球格陣列封裝’除 了可以在外部金屬栓端面佈楢焊接錫球或銅球’形成球格 陣列，與其他電路基板進行電性連接外，還可以在外部金 屬栓端面塗佈錫膏，形成焊墊陣列與其他電路基板連接。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 <請先閱讀背面之沒意事項再填寫本頁) 裝---- 訂--------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐）4. Secret, 4 A7 5. Invention Description (f) The present invention relates to a method for manufacturing a semiconductor package structure, and more particularly to a ball grid array package structure with a trace line and a metal tie. Production method. (Please read the notes on the back before filling this page.) In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: one is the formation of semiconductor substrates, that is, the epitaxial technology part 'Such as the manufacture of silicon wafers; followed by the manufacture of semiconductor components, such as metal-oxide semiconductor processes, multi-metal interconnects, etc .; and finally the packaging of semiconductors. The purpose of packaging is to provide a medium for the electrical connection between a die and a printed circuit board (Printed Cuxuh B0ard, PCB) or other appropriate components, and to protect the chip. In the module (Module), because a large number of wires are released from the chip, hundreds of connections are required to form a complete circuit. The traditional method is to use a lead frame to electrically connect the chip and the external leads of the package. Because the integration degree of integrated circuits is increasing, although the package volume remains the same or shrinks, the required wires have increased significantly, and traditional lead frames are no longer sufficient. And the development of electronic products is becoming lighter, thinner, shorter, and smaller. Therefore, many different packaging technologies have been developed, such as Chip Scale Package (Chip Size Package, CSP), Multi-Chip Module (MCM) )Wait. Since semiconductor process technology has developed to 0.18 micron (Micron) line width components, there have been many breakthroughs in improving the degree of integration. Therefore, how to develop a corresponding small-volume package to achieve the goal of product reduction has become an important issue today. The traditional package uses a lead frame as the carrier, and the lead frame of the lead frame 3 paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 V. Description of the invention (2) (Lead) is Protruding from the side of the package, the lead area is a Peripheral Layout, which makes the package area larger, and for high-pin-count components, it will be forced to increase the package area due to the limited lead space. Therefore, many Area Array packaging structures have been developed one after another, and the packaging contacts are arranged at the bottom of the package, such as: Ball Grid Array (BGA), Small Outline No-lead , SON), Ball Chip Carrier (BCC), etc. Please refer to FIG. 1A to FIG. IE, which are schematic cross-sectional views showing a manufacturing process of a conventional spherical wafer carrier package. First, referring to FIG. 1A, the photoresist layers 104a and 104b are coated on the surfaces 102a and 102b of the copper substrate 100, respectively, and the photoresist layer 104a is exposed and developed to expose the balls in the upper surface 102a of the copper substrate 100. Type pin area 106. Next, as shown in FIG. 1B, using the photoresist layers 104a 'to 104b as a mask, the copper substrate 100 is wet-etched to form a hemispherical cavity 108 in the ball-shaped pin region 106 in the copper substrate 100. Next, electroplating is performed, and a gold film 110 is plated on the surface of the hemispherical cavity 108. Referring to FIG. 1C, the photoresist layers 104a and 104b are peeled off, and a wafer 112 is stuck on the surface 102a. Wire bonding is performed, and a bonding pad (not shown in the figure) on the wafer 112 is connected to the gold film 110 with a gold wire 114. Then, referring to FIG. 1D, the upper surface 102a of the copper substrate 100 is sealed, and the wafer 112, the gold wire 114, and the gold film 110 are covered with a resin 116. Please refer to FIG. 1E again, and then perform wet etching to completely remove the copper substrate (such as 100 in FIG. 1D), and expose the bottom surface of the hemispherical gold film 110, the wafer 112, and the resin U6 surface. At this point, the spherical wafer loading is completed 4 · (Please read the precautions on the back before filling in this page) -------- Order ---! !! -Therefore, the paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard (CNS) A4 specification (2) 0 × 297 mm. A7 B7 ^ 432644 46 ^ 9tvv f.doc / 006 5. Description of the invention ( 4) Device package ', and this package uses hemispherical gold film 1] 〇 as a pin, and is coupled to external circuits. However, the main disadvantages of the above-mentioned spherical wafer carrier are the reliability of the product and the manufacturing yield. Because this package uses gold film as the pin, and the gold film is a precious metal, the cost should not be too thick, but it is easy to wear or peel off during processing or handling, which affects subsequent connections with other circuit substrates, such as surface soldering. Reliability of Surface Mount Technology (SMT), and Product Yield "and" As the pin count of components is increasing, the corresponding pad density on the package substrate is also increasing, and the pad pitch is shrinking. . The number of contacts used to connect to other circuit substrates on the package substrate needs to increase at the same time as the number of solder pads, and the size and spacing of the contacts are limited by other substrates and cannot be reduced. Only to meet the needs of packaging. Therefore, the present invention provides a method for manufacturing a ball grid array package structure with printed wires and metal pins, which has good reliability and manufacturing yield. The metal pins are used as the pins of the package, and the metal pins can be arranged in an area array, and the package has a thinner thickness. The exposed bottom surface of the chip holder can improve the heat dissipation effect of the chip. The end surface of the metal bolt is also provided with a plating layer, which has good jointability, packaging and solderability, which is conducive to the subsequent surface soldering process and can be applied to the packaging of high pin count components. According to the above and other objects of the present invention, a manufacturing method of a ball grid array package structure with printed wires and metal pins is proposed, which can be applied to the packaging of high-pin-count components. First, a metal substrate is provided, and a plating layer is formed on the metal pin area and the wafer seat area on the surface of the metal substrate. For the upper surface of metal substrates, this paper applies the Chinese National Standard (CNS) A4 specification (210x297 public love) II Γ II * r IIIIIL-IIIIIII 11111111 (Please read the precautions on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives and printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperatives r 143264 4 4 6 5 91 wf, doc / 0 Ο 6 A7 V. Description of the Invention (#) Partial etching and removal of some metal substrates In order to reduce its thickness, it forms printed wires, chip holders and internal metal plugs. The wafer is adhered to the wafer holder 'and is electrically connected to the inner metal plug. Then, an insulating material is used to cover the wafer, the wafer holder and the inner metal plug. Next, the lower surface of the metal substrate is etched, exposing a part of the insulating material and the bottom of the wafer holder 'and forming an external metal plug, and the internal and external metal plugs are electrically connected by a printed wire. Then, a solder mask is formed on the surface of the chip package, covering the printed wiring 'and exposing the plating on the end face of the external metal plug. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings' as follows: Brief description of the drawings: Figure 1A to Figure 1E shows a schematic cross-sectional view of the manufacturing process of a conventional ball chip carrier package. Figures 2A to 2H show a ball with printed wires and metal pins according to a preferred embodiment of the present invention. Figure 3A and Figure 3B show a grid array package with a manufacturing process. A ball grid array package with printed wires and metal pins is shown in accordance with a preferred embodiment of the present invention. And a top view and a bottom view of the metal substrate after the plating is formed; FIG. 4 illustrates a preferred embodiment of the present invention, 'a ball grid array package with printed wires and metal pins, in the manufacturing process' Schematic diagram after forming a printed wire on a metal substrate; and Figure 5 shows a preferred embodiment of the present invention, a paper with the paper size applicable to China National Standard (CNS) A4 (210x297 mm) ) ---------— 11.-I ------ ^-— — — In — · ^ < Please read the notes on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperative r P4326 4 4 46S9t \ vf.doc.O06 Magic_B7_ V. Description of the invention (g) Ball grid array package with printed wires and metal bolts. In the manufacturing process, the metal substrate is bonded to the chip and Top view after wire bonding. _ Symbol description of the drawing: 100: copper substrates 102a, 102b: surface 104a, 104b: photoresist layer 106: spherical pin area 108: hemispherical cavity 110: gold tin 112, 216, wafer '114 : Gold wire 116: Resin 200: Metal substrate 202a, 202b: Metal substrate surface 206a: Wafer area 206b, _206c: Metal pin area 208a, 2 () 8b, 208c: Coating 210: Wafer base 212a, 212b: Metal bolts 214, 2 丨 4a, 2 丨 4b: Printed wire 218: Wire 220: Insulating material 222: Welding cover 224: Welding material This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ΐ Please read the precautions on the back before filling out this page.) Packing --------- Ordering !! ------ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 432644 465 ^ t \ v r.duc / 006 A7 ____B7__ V. Description of the invention (4) 226: Adhesive material Η: For examples of height differences, please refer to Figures 2A to 2Η, which show a preferred embodiment according to the present invention. A schematic sectional view of the manufacturing process of a ball grid array package for making wires and metal pins. As shown in FIG. 2A, the present invention has a ball grid array packaging process with printed wires and metal pins. First, a metal substrate 200 is provided, and the material includes copper ν iron, copper alloy (C151, C194, C7025, KCF125, EFTEC, etc.) ) Or iron-nickel alloy (Ni-Fe 42 Alloy) and so on. A photoresist is coated on the first surface 202a and the second surface 202b of the metal substrate 200, and a photolithography process such as exposure and development is used to define a wafer holder region 206a, a first metal plug region 206b, and a second metal inspection region. After 206c, a part of the surface of the metal substrate 200 is exposed to form a patterned first photoresist layer 204a and a second photoresist layer 204b. Referring to FIG. 2B, a plating process (Platmg) is performed, and a wafer holder plating layer 208a and a first plating layer 208b are respectively formed on the wafer holder region 206a and the first metal plug region 206b of the first surface 202a, and the second surface 202b The second metal plug region 206c forms a second plating layer 208c. The material of the wafer base plating layer 208a, the first plating layer 208b, and the second plating layer 208c includes gold (Au), silver (Ag), nickel (Ni), palladium (Pd), nickel-palladium alloy, or a composite plating layer composed of the above materials. . A better combination is to first electroplat a nickel layer ', then electroplating thereon to form a nickel-palladium layer, and finally electroplating a palladium layer on the surface. And if the role of the nickel layer is to prevent corrosion, the palladium layer also has a good joint. 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210x297 public love)-^ ---- '1 ---- --- Install! | Order · -------- Line, (Please read the precautions on the .t side before filling out this page) A7 B7 P43264 4 4659UVl \ doc / 〇06 V. Description of the Invention (/ y) Bondability , Encapsulation (Molding Compound Characteristic) and Solderability (SoiderabiHty). Please refer to FIG. 3A and FIG. 3B, which show a ball grid array package with printed wires and metal studs according to a preferred embodiment of the present invention. In the manufacturing process, the plated metal is formed. Top and bottom views of the substrate. As shown in the figure, several substrates required for packaging can be made simultaneously in a metal substrate. Figure 3A shows a top view of the metal substrate, that is, a top view similar to the first surface 202a in Figure 2B, in which the wafer holder plating layer 208a is arranged at the center of the wafer packaging area and covers the wafer holder area ' The first plating layer 208b is located on the periphery of the wafer holder region, and the remaining surface is covered by the photoresist layer 204a. Figure 3B shows the bottom view of the metal substrate, which is similar to the top view of the second surface 202b in Figure 2B. The second plating layer 208c is distributed in an area array, and the remaining surface is covered by the photoresist layer 204b. . The wafer base ore layer 208a and the first plating layer 208b in FIG. 3A are rectangular, and the second plating layer 208c in FIG. 3B is circular. In this embodiment, this configuration will be described. However, the wafer base plating layer 208a The first plating layer 208b or the second plating layer 208c may have other various shapes. Therefore, the shapes of the plating layers shown in the figures are not intended to limit the scope of the present invention. In addition, the first plating layer 208b and the second plating layer 208c are distributed in different types according to the requirements of the electrical connection and the number of contacts. For example, a single-layer ring-shaped distribution is formed on the periphery of the plating of the wafer base (as shown in FIG. 3A). , Or multilayered ring-shaped distribution (as shown in Figure 3B). However, the shovel layer distribution pattern not shown in the figure is used to illustrate the embodiment of the window, and is not intended to limit the scope of the present invention. '--.--- I ------ jf -------- Order --------.- line (Please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau Staff Consumer Cooperatives This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) _4 3264 4 4659t wl'.doc ΌΟΟ Printed by the Consumer Cooperatives of the Ministry of Economic Affairs Intellectual Property Bureau B7 V. Description of the invention (》) Next, please take the photo _ 2C 'to peel off the first photoresist layer 204a and the second photoresist layer 204b in FIG. 2B, and then apply a photoresist on the first surface 202a of the metal substrate 200 ( (Not shown in the figure), after exposure, development, and other lithographic processes, the positions of the required wafer base 210, the first metal plug 212a, and the printed wiring 2i4a are defined. Then, the metal substrate 200 is etched. For example, a part of the metal substrate 200 is removed by using a wet etching method to form a wafer base 210, a first metal pin 212a, and a printed wire 214a, and the printed wire 214a and the wafer are formed. A distance is maintained between the sockets 2 and 10, and an isolation region is formed around the wafer seat 210 to prevent unnecessary electrical connection between the wafer and the printed wiring 214a. The surface of the wafer base 210 is covered with a wafer base plating layer 208a, the surface of the first metal plug 212a is covered by the first plating layer 208b, and the printed wire 214a is used to electrically connect different metal plugs and contacts. Referring to FIG. 2D, the thickness of the area where the metal substrate 200 is not covered by the wafer seat plating layer 208a and the first plating layer 208b is reduced to reduce the height of the printed wiring 214a in FIG. 2C to form the required The printed wire 214b, the wafer holder 210, and the first metal pin 212a located around the printed wire 214b have a height difference between the first metal pin 212a and the printed wire 214b. The height difference Η is at least about 1 mil, that is, 0.025 millimeters (mm), and the preferred height difference 大于 is greater than 2 mils (0.05 mm). As shown in FIG. 2D, the method for reducing the thickness of the metal substrate, for example, uses the wafer holder plating layer 208a and the first plating layer 208b as the etching mask 1 to perform half Etching on the metal substrate 200 to etch the metal substrate. Material 200, removing a portion of the metal substrate 200 to form the required printed wires 214b ', the wafer base 210 and the first metal plug 212a. You can also use the coin method (1) 丨 丨 —— 丨 — I— —— — — — — — I — ^ — — — — — f (Please read the notes on the back before filling this page) This paper Zhang scale is applicable to China® Home Standard (CNS) A4 specification (2) 0 × 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 2 6 4 4 46 states, '' mountain 'with 0〇6 A7 _ B7 V. Description of the invention (q) Formula “For the area of the first surface 202a of the metal substrate 200 that is not covered with the wafer base plating layer 208a and the first plating layer 208b, press with a mold to reduce the thickness of the metal substrate. Form the required printed conductor 214b, wafer holder 2 and the first metal plug 212a. Please refer to FIG. 4 for a description of a preferred embodiment according to the invention of the invention 'A printed circuit conductor and metal In the manufacturing process of the ball grid array package of the bolt, the schematic diagram of the structure after forming the printed wire on the metal substrate is shown in FIG. 4 and referring to FIGS. 3A and 3B, which is similar to the metal in FIGS. Top view of the substrate 200, in which the wafer holder plating layer 208a is arranged on the wafer The center of the mounting area, and the printed wire 214 is a medium for electrically connecting the first plating layer 208b and the second plating layer 208c. Please refer to FIG. 2E for chip attachment (Chip Attach) and between the chip and the metal plug. Electrical connection. The wafer 216 is fixed on the surface of the plated layer 208a of the wafer holder 21, for example, using an adhesive material 226 such as an insulating adhesive, a conductive adhesive, or a tape, so that the wafer 216 is adhered to the surface of the plated plate 208a. The wafer bonding pad (not shown in the figure) and the first metal plug 212a 'are connected to the first pad 208b on the first metal plug 212a with a wire 218, for example, by wire bonding. The wire 218 The material is, for example, gold, aluminum, copper, etc. Please refer to FIG. 5 for a description of a ball grid array package with printed wires and metal pins according to a preferred embodiment of the present invention. The top view of the 'metal substrate after bonding the wafer and wire bonding. As shown in the figure', where the area of the wafer holder plating 208a is smaller than the wafer 216 it carries, the electrical conductivity between the wafer pad and the first plating layer 208b. Sexual connection 1 This paper size applies to China National Standard (CNS) A4 specifications (2) 〇X 297 public love) ------------- * I 1 ----- order ------- --- Lines <Please read the notes on the back before filling out this page) Γ Μ43 2 6 4 4 465ι) ΐννί'.ι3οο. 006 Magic ___ Β7__ 5. Description of the invention (/ 〇) is formed by, for example, using wire bonding The wire 2i8 is used to complete it, and the material of the wire 218 includes gold, inscription or copper. Please refer to FIG. 4 and FIG. 5 at the same time, the first plating layer 208b is distributed on the periphery of the wafer. However, the distribution pattern of the first plating layer 208b on the metal substrate is matched with the distribution of the wafer pads, so it can be in different types. The distribution of the first plating layer on the opposite sides of the wafer, for example, the distribution pattern of the first plating layer shown in the figure is an example, and is not intended to limit the scope of the present invention. Referring to FIG. 2F, a sealing process (Molding) is performed, and the conductive wire 218, the wafer 216, the wafer base plating layer 208a, the wafer base 210, the first plating layer 208b, the first metal plug 212a, and the printed wiring 214b are covered with an insulating material 220. The insulating materials used include resin (Resm), epoxy resin (Epoxy), etc. However, the sealing process is performed only on the first surface of the metal substrate 200, and the second surface 202b is completely exposed outside the insulating material 220. Then, referring to FIG. 2G, using the second plating layer 208c as an etching mask, the exposed portion of the second surface of the metal substrate 200 (202b in FIG. 2F) is etched, and a portion of the metal substrate is removed and exposed. Part of the insulating material 220 and the printed wire 214b are formed to form the second metal plug 212b, and the production of the printed wire and the metal plug is completed. The wafer base 210 forms a complete profile after etching, and has a lower surface approximately parallel to the bottom surface of the insulating material 224. The second metal bolt 212b can be electrically connected to the first metal bolt 212a by using the printed wire 214b as a medium. Please refer to Figure 2H and apply the solder mask material to the surface of the chip package. This paper is applicable to the national standard (CNS) A4 specification (210 X 297 mm), r_4 326 4 4 4 659t wr, doc / 006 V. Description of the Invention (//) A solder mask 222 is formed on the surface of the printed wiring 214b, and the second plating layer 208c is exposed. In the figure, the welding cover 222 only covers the exposed surface of the printed wiring 214b. However, the welding cover 222 is not limited to covering the printed wiring 222, and only the second plating layer 208c needs to be exposed. Therefore, the configuration of the welding cover in the figure is used to illustrate the embodiment, but not to limit the scope of the present invention. The material for forming the welding cover 222 in FIG. 2H is an insulating material, including photosensitive green paint and heat-hardening green paint, etc., and the method of coating the green paint to form the welding cover includes a roller coating method, a curtain A coating method (Cunam Coating), a screen printing method (Screen Printing), and a dry film (Dry Film) formation method. For example, a photosensitive green paint is used to form the solder mask 222. The green paint is first coated on the surface of the chip package, and the exposed surface of the printed wiring 214b is covered. After the first baking, exposure, development and second baking After the steps are completed, a desired solder mask 222 is formed. Another example is to use a heat-hardening green paint to form the welding cover 222. The green paint is applied to the exposed surface of the printed wire 214b according to the required welding cover pattern, and it is baked to harden to form the required welding. Cover 222. Please refer to FIG. 2H again. After the fabrication of the solder cover 222, the soldering material 224 can also be placed on the second plating layer 208c on the bottom surface of the package to provide a medium for the chip package to be electrically connected to other circuit substrates. 224 includes solder paste (Solder Paste), solder ball (Solder Ball), copper ball (Copper Ball), and the like. If solder balls or copper balls are planted on the second plating layer 208c, a ball grid array can be formed; if a solder paste is coated on the surface of the second plating layer 208c, a Land Grid Array (LGA) can be formed. Finally, it is divided by wafer dicing to complete the production of the packaged product. (Please read the precautions on the back before filling out this page) ---- • Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Online Economics The paper size is applicable to China National Standard (CNS) A4 Specifications (210x297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs • 432644 4 6 5 9 tw t .. doc / Ο 06 Λ7 V. Description of the Invention (h) As can be seen from Figure 2H, the application of the present invention has printing The ball grid array package of wires and metal pins has at least a chip holder 210 carrying a chip 216 in the package structure, a surface thereof has a plating layer 208a, and a bottom surface thereof can be exposed outside the insulating material 220. The second metal pins 212b are arranged on the periphery of the wafer holder 210 and are distributed in an area array. One end of the first metal plug 212a is buried in the insulating material 220 and is electrically connected to the chip pad; the other end is connected to the printed wire 2Ub, and is electrically connected to the second metal plug 2I2b through the printed wire 214b. . In addition, the first metal plug 212a and the second metal plug 212b have first plating layers 208b and second plating layers 208c on the end faces, respectively, to facilitate the processes of packaging bonding, sealing and subsequent surface welding techniques. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention has at least the following advantages: 1. The present invention has a ball grid array package with printed wires and metal pins, which uses metal pins as pins of the package to connect the chip to the outside The circuit can adopt area array configuration to improve the accumulation degree of the package. Moreover, the metal plug has better mechanical strength, which can improve the reliability of the package and the yield. 2. As the ball grid array package with printed wires and metal pins of the present invention uses a single sealing method, it has a thinner package thickness and can reduce the package volume. After the lower surface of the metal substrate is etched, the bottom surface of the wafer holder is exposed to the insulating material, which can improve the heat dissipation effect of the wafer. 3. In the ball grid array package with printed wires and metal pins of the present invention, a plating layer is arranged at one end of the gold pin, which can be used as a mask for the etching process. Appropriate selection of the coating material can make the metal plug have good jointability, encapsulation, and weldability, improve the yield of the product, and subsequent surface welding. The paper size applies the Chinese National Standard (CNS) A4 specification (2) 0 X 297 public love) ------------ ^ -------- Order --------- line < Please read the precautions on the back before filling the book Page} A7 B7 P4 32 6 4 4 4659t \ vi .doc / 0 {) 6 V. Description of the invention (丨 · >) Reliability during connection. 4. The ball grid array package with printed wires and metal plugs of the present invention can be used to form a ball grid array by soldering solder balls or copper balls on the end faces of the external metal plugs to electrically connect with other circuit substrates. The solder paste is coated on the end face of the external metal plug to form a solder pad array and connect to other circuit substrates. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. < Please read the unintentional matter on the back before filling in this page) Packing ---- Ordering -------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese National Standards (CNS) A4 size (210x297 mm)