TW410410B - An arrangement of data input/output circuits for use in a semiconductor memory device - Google Patents
An arrangement of data input/output circuits for use in a semiconductor memory device Download PDFInfo
- Publication number
- TW410410B TW410410B TW088103659A TW88103659A TW410410B TW 410410 B TW410410 B TW 410410B TW 088103659 A TW088103659 A TW 088103659A TW 88103659 A TW88103659 A TW 88103659A TW 410410 B TW410410 B TW 410410B
- Authority
- TW
- Taiwan
- Prior art keywords
- data input
- output
- circuits
- semiconductor memory
- memory cell
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980023610A KR100306967B1 (ko) | 1998-06-23 | 1998-06-23 | 반도체메모리집적회로장치의데이터입/출력회로배열 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW410410B true TW410410B (en) | 2000-11-01 |
Family
ID=19540414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088103659A TW410410B (en) | 1998-06-23 | 1999-03-10 | An arrangement of data input/output circuits for use in a semiconductor memory device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100306967B1 (ko) |
| TW (1) | TW410410B (ko) |
-
1998
- 1998-06-23 KR KR1019980023610A patent/KR100306967B1/ko not_active IP Right Cessation
-
1999
- 1999-03-10 TW TW088103659A patent/TW410410B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100306967B1 (ko) | 2001-11-30 |
| KR20000002716A (ko) | 2000-01-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |