TW383478B - Method of forming interconnection for semiconductor device - Google Patents

Method of forming interconnection for semiconductor device Download PDF

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Publication number
TW383478B
TW383478B TW087114421A TW87114421A TW383478B TW 383478 B TW383478 B TW 383478B TW 087114421 A TW087114421 A TW 087114421A TW 87114421 A TW87114421 A TW 87114421A TW 383478 B TW383478 B TW 383478B
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Taiwan
Prior art keywords
copper
item
thin film
forming
patent application
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TW087114421A
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English (en)
Inventor
Seung-Yun Lee
Yong-Sup Hwang
Chong-Ook Park
Dong-Won Kim
Sa-Kyun Rha
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Lg Semicon Co Ltd
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Publication of TW383478B publication Critical patent/TW383478B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

經济部中央#:準而货Η消費合作.#印製 A7 ----------- B7 五、發明説明（1) — 發明背景 發明領域 本發明係關於半導體裝置，特別係關於使用銅形成半 V體裝置之互連之方法’銅適合作為高度積禮及高功率半 導體裝置之互連村料。 背景討論 身又而5紹廣泛用作高度積體電路之電互連之導電材 料。 但隨著互連寬度之縮窄，鋁電阻對電路之電阻/電容 時間（RC時間）延遲有某種意義，也隨著尺寸之縮窄其設計 法則受限。 因此晚近鋼替代鋁作為半導體裝置之互連材料，原因 為其比電阻約比鋁低40%極具有極佳電遷移性。通常銅 藉鑲嵌法形成。 '、 現在參照附圖敘述形成習知半導體裝置之銅互連之方 法。 ·_ 第1圖中’絕緣層2形成於半導體基材1上，活性元件 整合於半導體基材上，及切槽2a成形於絕緣層2.銅薄膜3 藉濺鍍沈積法形成於包括切槽2a之絕緣層2。此處當藉濺 鍍沈積法連續沈積銅俾填補切槽2a時於切槽2a形成空隙5 ，如第2圖所示。 〆、人為了去除切槽2a之空隙5，其上沈積銅薄膜3於半 導體基材1置於真空爐内，及於50(TC或以上於氧/氫氣氛 下退火超過1小時。如此如第3圖所示，銅薄膜3流動入成 本紙張尺度通用中( CNS ) A4規格（2〗0X297公釐) '~~~ -- —---------J------、玎----,——Φ, (請先閲讀背面之注意Ϋ-項再填寫本頁} A7 五、 發明説明（2 B7 开^於切槽2a之空隙5，如此切槽2&被完全填補而無餘隙。 此處前述方法稱做鋼再流動法。 、$知形成半導體裝置之銅互連之方法係應用鋼再流動 法’其需要超過1小時之退火時間及溫度高於50(TC於氧/ 氫氣氛下俾形成毫無空隙的服貼銅層，如此降低半導體褽 置之生產力。 發明概述 如此本發明之主要目的係提供一種形成半導體裴置之 互連之方法，其比較先前技術可於較低退火溫度及較短退 火時間再流動沈積妥之銅薄膜。 本發明之其他優點及特點將陳述於後文說明，部份由 說明顯然易明。或可藉實施本發明習得。本發明之目的及 其他優點由書面說明及申請專利範圍及附圖特別指出之結 構可實現及達成。 為了達成如此處具體廣義說明之本發明之其他優點及 目的種形成半導體裝置之互連之方法，其包含下列步 驟： 形成一絕緣層具有一切槽於半導體基材上；.形成及沈 積一銅薄膜於包括該切槽之絕緣層上；及再流動該銅薄膜 立需瞭解前文概略說明及後文詳細說明係供舉例說明之 用意圖對如申請專利之本發明提供進一步解說。 圖式之簡單說明 附圖示例說明本發明之具體例連同詳細說明用來解釋 本紙張尺度適和中國國家椟準（CNS ) A4規格（210.X297公餐; 請 聞 背 面 之 注 項 再 4 % i- 頁 訂 經"·部中央樣牟而炅工消费合作拉印製 經濟部中央#準局贝X消贽告作衽印t A7 -----* B1 ' ~ —— M ___ 五、發明説明（3) ~ 本發明之原理，含括於此僅供進一步瞭解本發明故合併構 成本說明書之一部份。 附圖中： 第1至3圖為垂直剖面圖示例說明習知形成半導體裝置 之銅互連之方法； 第4及5圖為垂直剖面圖示例說明根據本發明形成半導 體裝置之鋼互連之方法；及 第6圖為表顯示銅及銅-齒化材料之熔點。 發明之詳細說明 現在參照本發明之較佳具體例詳細說明，其實例示例 說明於附圖。 第4及5圖為垂直剖面圖示例說明根據本發明形成半導 體裝置之銅互連之方法。 首先，第4圖中，具有切槽21之絕緣層2〇成形於半導 體裝置10上，其中活性元件整合於半導體裝置中，及鋼薄 •.膜30藉·濺鍍沈積法形成於包括切槽21之絕緣層2〇上。 此處為了完全填補切槽21，其上沈積銅薄膜2之半導 體基材10置於真空爐，於45(rc或以下於鹵素氣體氣氛下 退火少於30分鐘。至於另一種填補切槽21之方法，包於絕 緣層上形成銅薄膜時加入小量函素氣體，如此形成銅_鹵 素材料，所得半導體基材10於前述條件下退火。此處銅原 子之遷移增加，如此銅薄膜30再流動及切槽21被填補而毫 無任何空隙，如第5圖所示。鹵素氣體J?2，Cl2 , Br，j中 ，Fa及CL可成氣態植入，而]5]：或1可呈液態置於起泡器内 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） {請先閲讀背面之注意事項再填寫本頁) 訂 ΦΙ. A7 B7 五、 發明説明（ 及使用情性氣體Ar或He藉起泡方法呈氣態植入，或使用 液體贈或氣化器植人4素氣體於退火過程後係藉清 洗法去除。 請 閲 讀 背 面 之 注 意 事， 項 再 填 本 頁 根據於齒素氣體氣氛之銅再流動方法，植入爐内之鹵 素氣壓维持於W托耳及銅』化材料僅形成於銅薄膜表面 。如第6圖所示，因銅·鹵化材料之熔點顯著低於銅溶點， 故即使於〶於退火溫度，形成於銅薄膜表面之銅』化材 料流體化。 現在說明根據本發明之銅之再流動方法之原理。 當Κ為薄膜表面預定點之曲率時，表面各點之化學電 位/^ 0+邮（其中r為表s張力及Ω為原子體積）。第4 訂 圖中於藉親沈積法沈積鋼薄膜於半導體基材表面之例， 由於銅薄膜各點具有不同表面曲率，當施加熱能時依據表 面各點之化學電位梯度原子進行表面擴散而填補切槽毫無 空隙。 經境部中央樣卑而兵工消f合作社印製 气前述根據本發明經由使用銅形成半導體裝置互連之 方法可於低於450°c再流動沈積於具有高階表面之半導體 基材上的銅薄膜歷小於3〇分鐘，其比較先前技術顳示改良 之退火條件。此外，經由根據低溫方法減少熱能消耗，合 形成半導體裝置之互連時可允許銅不會快速擴散通過石夕基 材，電極等，如此改良半導體裝置之生產力。 業界人士顯然易知可於本發明之形成半導體裝置之互 連之方法做出多種修改及變化而未背離本發明之精體或範 圍。如此本發明意圖涵蓋屬於隨附之申請專利範圍及其相 本紙張尺度適财國國家標準（CNS)从規^；(训-幻97公酱）_ S83478 A7 B7 五、發明説明（ 當範圍之修改及變化。 元件標號對照 1.. .半導體基材 2.. .絕緣層 2a…切槽 3…銅薄膜 5.. .空隙 10.. .半導體基材 20.. .絕緣層 21…切槽 .---------;------1T------JI- (請先閲讀背面之注意事項再填寫本頁) 經"'部中央標率^1'只-·1'消贽合作拍印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ29?公釐）

Claims (1)

  1. A8 B8 C8 D8 S8S478 ------ 申請專利範圍 種形成半導體裝置 之互連之方法，其包含下列步 驟 形成一層具有—切槽之絕緣層於半導體基材上； 形成一銅薄膜於包括該切槽之絕緣層上；及 於。3彘素氣體氣氛下再流動銅薄膜。 2·如申請專利範圍第1 、〈万法，其中該銅薄膜係經由減 鏡沈積法’化學蒸氣沈積法或蒸發法形成。 3 .如申請專利範圍第1 ▲ …方法，其中該形成及再流動趣 缚膜之步驟係於同-腔室内進行。 4·如申請專利範圍第1項之方法，其中該銅薄膜係於45| c或以下再流動。 5.如申請專利範園第]货+ 項之方法，，其中植入之鹵素氣體超 自包括F2’Cl2, Br’或I或其组合。 6·如申睛專利範圍第1項之方法，其中該鹵素氣體與銅旁 、反應如此於銅薄膜表面形成鋼-鹵化材料。 • 7·如申請專利範圍笫〗货 ' 固弟1項之方法，其中卩2及(：12係呈氣I 植入。 經濟部中央裙準局員工消費合作社印製 申°月專利範圍第5項之方法，其中Br或I係，呈流體j /起泡内及使用心及取等惰性氣體藉起泡方法呈_ 態植人或經由使用液體峨或氣化器植入。 申:專利範圍第5項之方法，其中該腔室壓力於再^ 動銅薄膜之步驟係維持於低於！ 〇_2托耳俾使銅-齒化和 料僅於銅薄膜表面形成。 10·如申請專利範圍第丨項之方法，其中#沈_薄膜於色 ㈣槽之絕緣層時添加小量南素氣體。
TW087114421A 1998-02-07 1998-08-31 Method of forming interconnection for semiconductor device TW383478B (en)

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KR1019980003580A KR100259357B1 (ko) 1998-02-07 1998-02-07 반도체 소자의 배선형성방법

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US (1) US6057228A (zh)
JP (1) JPH11274159A (zh)
KR (1) KR100259357B1 (zh)
DE (1) DE19843173A1 (zh)
TW (1) TW383478B (zh)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
US11430692B2 (en) 2020-07-29 2022-08-30 Taiwan Semiconductor Manufacturing Company Limited Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same

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JP4669605B2 (ja) * 2000-11-20 2011-04-13 東京エレクトロン株式会社 半導体製造装置のクリーニング方法
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
JP5023505B2 (ja) * 2006-02-09 2012-09-12 東京エレクトロン株式会社 成膜方法、プラズマ成膜装置及び記憶媒体
US9337092B2 (en) 2011-09-30 2016-05-10 Ulvac, Inc. Method of manufacturing semiconductor device
US8796853B2 (en) 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity

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US5098516A (en) * 1990-12-31 1992-03-24 Air Products And Chemicals, Inc. Processes for the chemical vapor deposition of copper and etching of copper
US5144049A (en) * 1991-02-04 1992-09-01 Air Products And Chemicals, Inc. Volatile liquid precursors for the chemical vapor deposition of copper
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US5714418A (en) * 1995-11-08 1998-02-03 Intel Corporation Diffusion barrier for electrical interconnects in an integrated circuit
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Cited By (3)

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Publication number Priority date Publication date Assignee Title
US11430692B2 (en) 2020-07-29 2022-08-30 Taiwan Semiconductor Manufacturing Company Limited Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same
TWI801927B (zh) * 2020-07-29 2023-05-11 台灣積體電路製造股份有限公司 半導體結構與其形成方法
US12080594B2 (en) 2020-07-29 2024-09-03 Taiwan Semiconductor Manufacturing Company Limited Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same

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KR100259357B1 (ko) 2000-06-15
DE19843173A1 (de) 1999-08-19
JPH11274159A (ja) 1999-10-08
US6057228A (en) 2000-05-02
KR19990069376A (ko) 1999-09-06

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