TW373321B - Memory arrangement and the production method therefor - Google Patents

Memory arrangement and the production method therefor

Info

Publication number
TW373321B
TW373321B TW086113012A TW86113012A TW373321B TW 373321 B TW373321 B TW 373321B TW 086113012 A TW086113012 A TW 086113012A TW 86113012 A TW86113012 A TW 86113012A TW 373321 B TW373321 B TW 373321B
Authority
TW
Taiwan
Prior art keywords
electrodes
production method
memory arrangement
method therefor
areas
Prior art date
Application number
TW086113012A
Other languages
English (en)
Inventor
Walter Hartner
Carlos Mazure-Espejo
Gunther Schindler
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW373321B publication Critical patent/TW373321B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
TW086113012A 1996-09-27 1997-09-09 Memory arrangement and the production method therefor TW373321B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19639899A DE19639899B4 (de) 1996-09-27 1996-09-27 Verfahren zur Herstellung einer Speicheranordnung

Publications (1)

Publication Number Publication Date
TW373321B true TW373321B (en) 1999-11-01

Family

ID=7807173

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113012A TW373321B (en) 1996-09-27 1997-09-09 Memory arrangement and the production method therefor

Country Status (7)

Country Link
EP (1) EP0946984A1 (zh)
JP (1) JP2001511306A (zh)
KR (1) KR20000048659A (zh)
CN (1) CN1231766A (zh)
DE (1) DE19639899B4 (zh)
TW (1) TW373321B (zh)
WO (1) WO1998013877A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459362B2 (en) 2005-06-27 2008-12-02 Micron Technology, Inc. Methods of forming DRAM arrays
US7548407B2 (en) * 2005-09-12 2009-06-16 Qualcomm Incorporated Capacitor structure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2755591B2 (ja) * 1988-03-25 1998-05-20 株式会社東芝 半導体記憶装置
US5298775A (en) * 1990-02-26 1994-03-29 Nec Corporation Semiconductor memory device having stacked-type capacitor of large capacitance
US5241201A (en) * 1990-04-02 1993-08-31 Matsushita Electric Industrial Co., Ltd. Dram with concentric adjacent capacitors
JPH04181769A (ja) * 1990-11-15 1992-06-29 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
EP0508760A1 (en) * 1991-04-08 1992-10-14 STMicroelectronics, Inc. Dynamic random access memory cell
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure
JP3250257B2 (ja) * 1992-06-09 2002-01-28 セイコーエプソン株式会社 半導体装置及びその製造方法
KR0137229B1 (ko) * 1993-02-01 1998-04-29 모리시다 요이찌 반도체 기억장치 및 그 제조방법
JPH07193137A (ja) * 1993-12-27 1995-07-28 Hitachi Ltd 半導体記憶装置およびその製造方法
KR0180779B1 (ko) * 1995-02-27 1999-03-20 김주용 반도체소자의 캐패시터 제조방법

Also Published As

Publication number Publication date
DE19639899B4 (de) 2005-07-07
DE19639899A1 (de) 1998-04-02
KR20000048659A (ko) 2000-07-25
JP2001511306A (ja) 2001-08-07
CN1231766A (zh) 1999-10-13
EP0946984A1 (de) 1999-10-06
WO1998013877A1 (de) 1998-04-02

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