TW372359B - Manufacturing process for borderless vias with respect to underlying metal - Google Patents

Manufacturing process for borderless vias with respect to underlying metal

Info

Publication number
TW372359B
TW372359B TW085114883A TW85114883A TW372359B TW 372359 B TW372359 B TW 372359B TW 085114883 A TW085114883 A TW 085114883A TW 85114883 A TW85114883 A TW 85114883A TW 372359 B TW372359 B TW 372359B
Authority
TW
Taiwan
Prior art keywords
vias
metal
via fill
manufacturing process
chemical interaction
Prior art date
Application number
TW085114883A
Other languages
English (en)
Inventor
Sunil Mehta
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of TW372359B publication Critical patent/TW372359B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW085114883A 1996-02-01 1996-12-03 Manufacturing process for borderless vias with respect to underlying metal TW372359B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/595,150 US6577007B1 (en) 1996-02-01 1996-02-01 Manufacturing process for borderless vias with respect to underlying metal

Publications (1)

Publication Number Publication Date
TW372359B true TW372359B (en) 1999-10-21

Family

ID=24381947

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114883A TW372359B (en) 1996-02-01 1996-12-03 Manufacturing process for borderless vias with respect to underlying metal

Country Status (3)

Country Link
US (1) US6577007B1 (zh)
TW (1) TW372359B (zh)
WO (1) WO1997028563A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287959B1 (en) 1998-04-23 2001-09-11 Advanced Micro Devices, Inc. Deep submicron metallization using deep UV photoresist
EP1097473A1 (en) * 1998-07-10 2001-05-09 Applied Materials, Inc. Plasma process to deposit silicon nitride with high film quality and low hydrogen content
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US7948094B2 (en) * 2007-10-22 2011-05-24 Rohm Co., Ltd. Semiconductor device
US20090230557A1 (en) * 2008-03-17 2009-09-17 Infineon Technologies Ag Semiconductor Device and Method for Making Same
US8299625B2 (en) 2010-10-07 2012-10-30 International Business Machines Corporation Borderless interconnect line structure self-aligned to upper and lower level contact vias
JP5571030B2 (ja) 2011-04-13 2014-08-13 株式会社東芝 集積回路装置及びその製造方法
US9184111B2 (en) * 2013-11-09 2015-11-10 Delta Electronics, Inc. Wafer-level chip scale package

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2428373C2 (de) * 1974-06-12 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von weichlötbaren Anschlußkontakten auf einer Halbleiteranordnung
JPS63224240A (ja) * 1987-03-12 1988-09-19 Fuji Xerox Co Ltd 半導体集積回路装置
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
US4966870A (en) * 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
JPH0834304B2 (ja) * 1990-09-20 1996-03-29 富士通株式会社 半導体装置およびその製造方法
DE4115909C1 (zh) * 1991-05-15 1992-11-12 Siemens Ag, 8000 Muenchen, De
EP0523856A3 (en) 1991-06-28 1993-03-17 Sgs-Thomson Microelectronics, Inc. Method of via formation for multilevel interconnect integrated circuits
KR100220297B1 (ko) 1991-12-02 1999-09-15 김영환 다층금속 배선구조의 콘택제조방법
JP2755035B2 (ja) * 1992-03-28 1998-05-20 ヤマハ株式会社 多層配線形成法
GB9219267D0 (en) 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
JP3297220B2 (ja) * 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US5432128A (en) * 1994-05-27 1995-07-11 Texas Instruments Incorporated Reliability enhancement of aluminum interconnects by reacting aluminum leads with a strengthening gas

Also Published As

Publication number Publication date
WO1997028563A1 (en) 1997-08-07
US6577007B1 (en) 2003-06-10

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Legal Events

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