TW358965B - Method and apparatus for manufacturing semiconductor devices - Google Patents

Method and apparatus for manufacturing semiconductor devices

Info

Publication number
TW358965B
TW358965B TW086117868A TW86117868A TW358965B TW 358965 B TW358965 B TW 358965B TW 086117868 A TW086117868 A TW 086117868A TW 86117868 A TW86117868 A TW 86117868A TW 358965 B TW358965 B TW 358965B
Authority
TW
Taiwan
Prior art keywords
metal film
decomposed
insulation film
semiconductor devices
film
Prior art date
Application number
TW086117868A
Other languages
English (en)
Inventor
Akihiro Kajita
Katsuhiko Oya
Johta Fukuhara
Kenichi Otsuka
Hitoshi Itoh
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW358965B publication Critical patent/TW358965B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
TW086117868A 1996-11-29 1997-11-27 Method and apparatus for manufacturing semiconductor devices TW358965B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31965696 1996-11-29
JP9211979A JPH10214896A (ja) 1996-11-29 1997-08-06 半導体装置の製造方法及び製造装置

Publications (1)

Publication Number Publication Date
TW358965B true TW358965B (en) 1999-05-21

Family

ID=26518943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086117868A TW358965B (en) 1996-11-29 1997-11-27 Method and apparatus for manufacturing semiconductor devices

Country Status (4)

Country Link
US (1) US5990007A (zh)
JP (1) JPH10214896A (zh)
KR (1) KR100295567B1 (zh)
TW (1) TW358965B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2985858B2 (ja) * 1997-12-19 1999-12-06 日本電気株式会社 エッチング方法
US6187672B1 (en) * 1998-09-22 2001-02-13 Conexant Systems, Inc. Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
US6668445B1 (en) * 2000-01-11 2003-12-30 Lexmark International, Inc. Method of increasing tab bond strength using reactive ion etching
JP2001196373A (ja) 2000-01-13 2001-07-19 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
JP3516918B2 (ja) * 2000-01-19 2004-04-05 株式会社日立国際電気 半導体装置の製造方法及び半導体製造装置
ATE487604T1 (de) * 2000-05-22 2010-11-15 Seiko Epson Corp Kopfelement und verfahren zur tintenabweisenden behandlung
KR20020004539A (ko) * 2000-07-06 2002-01-16 박종섭 수소확산을 방지할 수 있는 강유전체 메모리 소자 제조 방법
US6218301B1 (en) * 2000-07-31 2001-04-17 Applied Materials, Inc. Deposition of tungsten films from W(CO)6
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Necエレクトロニクス株式会社 半導体装置の製造方法
KR100536808B1 (ko) * 2004-06-09 2005-12-14 동부아남반도체 주식회사 반도체 소자 및 그 제조 방법
JP4941921B2 (ja) 2005-03-14 2012-05-30 株式会社アルバック 選択W−CVD法及びCu多層配線の製作法
US7732329B2 (en) * 2006-08-30 2010-06-08 Ipgrip, Llc Method and apparatus for workpiece surface modification for selective material deposition
US7488687B2 (en) * 2006-09-12 2009-02-10 Samsung Electronics Co., Ltd. Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers
JP2008166062A (ja) * 2006-12-27 2008-07-17 Hitachi High-Technologies Corp 真空容器を持つ装置
JP5788274B2 (ja) 2011-09-14 2015-09-30 ルネサスエレクトロニクス株式会社 抵抗変化型不揮発記憶装置、半導体装置及び抵抗変化型不揮発記憶装置の製造方法
US10014213B2 (en) * 2015-10-15 2018-07-03 Tokyo Electron Limited Selective bottom-up metal feature filling for interconnects
US11410880B2 (en) * 2019-04-23 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Phase control in contact formation
US20230136499A1 (en) * 2021-10-31 2023-05-04 Applied Materials, Inc. Selective Passivation Of Damaged Nitride

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3211752C2 (de) * 1982-03-30 1985-09-26 Siemens AG, 1000 Berlin und 8000 München Verfahren zum selektiven Abscheiden von aus Siliziden hochschmelzender Metalle bestehenden Schichtstrukturen auf im wesentlichen aus Silizium bestehenden Substraten und deren Verwendung
JP2947818B2 (ja) * 1988-07-27 1999-09-13 株式会社日立製作所 微細孔への金属穴埋め方法
KR940000906B1 (ko) * 1988-11-21 1994-02-04 가부시키가이샤 도시바 반도체장치의 제조방법
EP0560617A3 (en) * 1992-03-13 1993-11-24 Kawasaki Steel Co Method of manufacturing insulating film on semiconductor device and apparatus for carrying out the same
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure

Also Published As

Publication number Publication date
KR100295567B1 (ko) 2001-09-07
JPH10214896A (ja) 1998-08-11
KR19980042907A (ko) 1998-08-17
US5990007A (en) 1999-11-23

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees